From: Raphael Poggi <poggi.raph@gmail.com>
To: barebox@lists.infradead.org
Cc: Raphael Poggi <poggi.raph@gmail.com>
Subject: [PATCH v2 10/12] arm: cpu: disable code portion in armv8 case
Date: Tue, 14 Jun 2016 09:06:44 +0200 [thread overview]
Message-ID: <1465888006-39463-11-git-send-email-poggi.raph@gmail.com> (raw)
In-Reply-To: <1465888006-39463-1-git-send-email-poggi.raph@gmail.com>
Enclosed by #if directive OMAP specific code
and mmu_disable (ARMv8 code will implemented it somewhere else).
Signed-off-by: Raphael Poggi <poggi.raph@gmail.com>
---
arch/arm/cpu/cpu.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index eb12166..cc54324 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -68,6 +68,7 @@ int icache_status(void)
return (get_cr () & CR_I) != 0;
}
+#if __LINUX_ARM_ARCH__ <= 7
/*
* SoC like the ux500 have the l2x0 always enable
* with or without MMU enable
@@ -86,6 +87,7 @@ void mmu_disable(void)
}
__mmu_cache_off();
}
+#endif
/**
* Disable MMU and D-cache, flush caches
@@ -100,6 +102,8 @@ static void arch_shutdown(void)
mmu_disable();
flush_icache();
+
+#if __LINUX_ARM_ARCH__ <= 7
/*
* barebox normally does not use interrupts, but some functionalities
* (eg. OMAP4_USBBOOT) require them enabled. So be sure interrupts are
@@ -108,6 +112,7 @@ static void arch_shutdown(void)
__asm__ __volatile__("mrs %0, cpsr" : "=r"(r));
r |= PSR_I_BIT;
__asm__ __volatile__("msr cpsr, %0" : : "r"(r));
+#endif
}
archshutdown_exitcall(arch_shutdown);
--
2.1.0
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next prev parent reply other threads:[~2016-06-14 7:07 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-14 7:06 Raphael Poggi
2016-06-14 7:06 ` [PATCH v2 01/12] arm: add armv8 Kconfig entries Raphael Poggi
2016-06-15 6:33 ` Sascha Hauer
2016-06-23 14:43 ` Raphaël Poggi
2016-06-14 7:06 ` [PATCH v2 02/12] arm: Makefile: rework makefile to handle armv8 Raphael Poggi
2016-06-14 7:06 ` [PATCH v2 03/12] arm: introduce lib64 for arm64 related stuff Raphael Poggi
2016-06-15 6:15 ` Sascha Hauer
2016-06-23 14:43 ` Raphaël Poggi
2016-06-14 7:06 ` [PATCH v2 04/12] arm: cpu: add arm64 specific code Raphael Poggi
2016-06-14 7:06 ` [PATCH v2 05/12] arm: include: system: add arm64 helper functions Raphael Poggi
2016-06-14 7:06 ` [PATCH v2 06/12] arm: cpu: start: arm64 does not support relocation Raphael Poggi
2016-06-14 7:06 ` [PATCH v2 07/12] arm: include: bitops: arm64 use generic __fls Raphael Poggi
2016-06-14 7:06 ` [PATCH v2 08/12] arm: include: system_info: add armv8 identification Raphael Poggi
2016-06-14 7:06 ` [PATCH v2 09/12] arm: cpu: cpuinfo: add armv8 support Raphael Poggi
2016-06-14 7:06 ` Raphael Poggi [this message]
2016-06-14 7:06 ` [PATCH v2 11/12] arm: cpu: add basic arm64 mmu support Raphael Poggi
2016-06-14 7:06 ` [PATCH v2 12/12] arm: boards: add mach-qemu and virt64 board Raphael Poggi
2016-06-24 8:17 ` Raphaël Poggi
2016-06-24 11:49 ` Re: Sascha Hauer
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