From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bK2Rq-0007tD-SN for barebox@lists.infradead.org; Mon, 04 Jul 2016 11:54:00 +0000 Received: by mail-wm0-x241.google.com with SMTP id 187so21129860wmz.1 for ; Mon, 04 Jul 2016 04:53:42 -0700 (PDT) From: Raphael Poggi Date: Mon, 4 Jul 2016 13:52:52 +0200 Message-Id: <1467633177-22478-10-git-send-email-poggi.raph@gmail.com> In-Reply-To: <1467633177-22478-1-git-send-email-poggi.raph@gmail.com> References: <1467633177-22478-1-git-send-email-poggi.raph@gmail.com> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" Errors-To: barebox-bounces+u.kleine-koenig=pengutronix.de@lists.infradead.org Subject: [PATCH v5 09/14] arm: cpu: disable code portion in armv8 case To: barebox@lists.infradead.org Cc: Raphael Poggi Enclosed by #if directive OMAP specific code and mmu_disable (ARMv8 code will implemented it somewhere else). Signed-off-by: Raphael Poggi --- arch/arm/cpu/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c index eb12166..cc54324 100644 --- a/arch/arm/cpu/cpu.c +++ b/arch/arm/cpu/cpu.c @@ -68,6 +68,7 @@ int icache_status(void) return (get_cr () & CR_I) != 0; } +#if __LINUX_ARM_ARCH__ <= 7 /* * SoC like the ux500 have the l2x0 always enable * with or without MMU enable @@ -86,6 +87,7 @@ void mmu_disable(void) } __mmu_cache_off(); } +#endif /** * Disable MMU and D-cache, flush caches @@ -100,6 +102,8 @@ static void arch_shutdown(void) mmu_disable(); flush_icache(); + +#if __LINUX_ARM_ARCH__ <= 7 /* * barebox normally does not use interrupts, but some functionalities * (eg. OMAP4_USBBOOT) require them enabled. So be sure interrupts are @@ -108,6 +112,7 @@ static void arch_shutdown(void) __asm__ __volatile__("mrs %0, cpsr" : "=r"(r)); r |= PSR_I_BIT; __asm__ __volatile__("msr cpsr, %0" : : "r"(r)); +#endif } archshutdown_exitcall(arch_shutdown); -- 2.1.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox