* [PATCH 1/3] ARM: imx6: split out IPU QoS setup
@ 2016-09-15 11:10 Lucas Stach
2016-09-15 11:10 ` [PATCH 2/3] ARM: imx6: don't execute IPU QoS setup on MX6 SX/SL Lucas Stach
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Lucas Stach @ 2016-09-15 11:10 UTC (permalink / raw)
To: barebox
Split into separate function and only call it after the chip type
and revision is known.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
arch/arm/mach-imx/imx6.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index ba8fb8964ac8..07d3f57d8dcc 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -31,10 +31,8 @@ void imx6_init_lowlevel(void)
{
void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR;
- void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
bool is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q;
bool is_imx6d = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6D;
- uint32_t val;
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
@@ -94,6 +92,13 @@ void imx6_init_lowlevel(void)
MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
}
+}
+
+void imx6_setup_ipu_qos(void)
+{
+ void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
+ uint32_t val;
+
val = readl(iomux + IOMUXC_GPR4);
val |= IMX6Q_GPR4_VPU_WR_CACHE_SEL | IMX6Q_GPR4_VPU_RD_CACHE_SEL |
IMX6Q_GPR4_VPU_P_WR_CACHE_VAL | IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
@@ -186,6 +191,8 @@ int imx6_init(void)
imx_set_silicon_revision(cputypestr, mx6_silicon_revision);
+ imx6_setup_ipu_qos();
+
return 0;
}
--
2.8.1
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^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH 2/3] ARM: imx6: don't execute IPU QoS setup on MX6 SX/SL
2016-09-15 11:10 [PATCH 1/3] ARM: imx6: split out IPU QoS setup Lucas Stach
@ 2016-09-15 11:10 ` Lucas Stach
2016-09-15 11:10 ` [PATCH 3/3] ARM: imx6qp: set NoC regulator to bypass Lucas Stach
2016-09-16 7:47 ` [PATCH 1/3] ARM: imx6: split out IPU QoS setup Sascha Hauer
2 siblings, 0 replies; 4+ messages in thread
From: Lucas Stach @ 2016-09-15 11:10 UTC (permalink / raw)
To: barebox
SX and SL variants only include the PXP and have no IPU, so
skip any IPU related QoS setup.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
arch/arm/mach-imx/imx6.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 07d3f57d8dcc..567559033770 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -99,6 +99,10 @@ void imx6_setup_ipu_qos(void)
void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
uint32_t val;
+ if (!cpu_mx6_is_mx6q() && !cpu_mx6_is_mx6d() &&
+ !cpu_mx6_is_mx6dl() && cpu_mx6_is_mx6s())
+ return;
+
val = readl(iomux + IOMUXC_GPR4);
val |= IMX6Q_GPR4_VPU_WR_CACHE_SEL | IMX6Q_GPR4_VPU_RD_CACHE_SEL |
IMX6Q_GPR4_VPU_P_WR_CACHE_VAL | IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
--
2.8.1
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^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 3/3] ARM: imx6qp: set NoC regulator to bypass
2016-09-15 11:10 [PATCH 1/3] ARM: imx6: split out IPU QoS setup Lucas Stach
2016-09-15 11:10 ` [PATCH 2/3] ARM: imx6: don't execute IPU QoS setup on MX6 SX/SL Lucas Stach
@ 2016-09-15 11:10 ` Lucas Stach
2016-09-16 7:47 ` [PATCH 1/3] ARM: imx6: split out IPU QoS setup Sascha Hauer
2 siblings, 0 replies; 4+ messages in thread
From: Lucas Stach @ 2016-09-15 11:10 UTC (permalink / raw)
To: barebox
The NoC regulator only passes the QoS signals through if it is
in bypass mode. This is a safe setting to give the IPU priority
over other requests. The kernel may change it to some other setting
once it knows the bandwidth requirements of the use-case.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
arch/arm/mach-imx/imx6.c | 11 +++++++++++
arch/arm/mach-imx/include/mach/imx6-regs.h | 3 +++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 567559033770..f90eec8bd2c8 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -97,6 +97,7 @@ void imx6_init_lowlevel(void)
void imx6_setup_ipu_qos(void)
{
void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
+ void __iomem *fast2 = (void *)MX6_FAST2_BASE_ADDR;
uint32_t val;
if (!cpu_mx6_is_mx6q() && !cpu_mx6_is_mx6d() &&
@@ -119,6 +120,16 @@ void imx6_setup_ipu_qos(void)
val &= ~(IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK | IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK);
val |= (0xf << 16) | (0x7 << 20);
writel(val, iomux + IOMUXC_GPR7);
+
+ /*
+ * On i.MX6 QP/DP the NoC regulator for the IPU ports needs to be in
+ * bypass mode for the above settings to take effect.
+ */
+ if ((cpu_mx6_is_mx6q() || cpu_mx6_is_mx6d()) &&
+ imx_silicon_revision() >= IMX_CHIP_REV_2_0) {
+ writel(0x2, fast2 + 0xb048c);
+ writel(0x2, fast2 + 0xb050c);
+ }
}
int imx6_init(void)
diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
index 68be43c9ab5b..e661c4ed120b 100644
--- a/arch/arm/mach-imx/include/mach/imx6-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx6-regs.h
@@ -3,6 +3,9 @@
#define MX6_GPMI_BASE_ADDR 0x00112000
+#define MX6_FAST1_BASE_ADDR 0x00c00000
+#define MX6_FAST2_BASE_ADDR 0x00b00000
+
#define MX6_AIPS1_ARB_BASE_ADDR 0x02000000
#define MX6_AIPS2_ARB_BASE_ADDR 0x02100000
--
2.8.1
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^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH 1/3] ARM: imx6: split out IPU QoS setup
2016-09-15 11:10 [PATCH 1/3] ARM: imx6: split out IPU QoS setup Lucas Stach
2016-09-15 11:10 ` [PATCH 2/3] ARM: imx6: don't execute IPU QoS setup on MX6 SX/SL Lucas Stach
2016-09-15 11:10 ` [PATCH 3/3] ARM: imx6qp: set NoC regulator to bypass Lucas Stach
@ 2016-09-16 7:47 ` Sascha Hauer
2 siblings, 0 replies; 4+ messages in thread
From: Sascha Hauer @ 2016-09-16 7:47 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On Thu, Sep 15, 2016 at 01:10:21PM +0200, Lucas Stach wrote:
> Split into separate function and only call it after the chip type
> and revision is known.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> arch/arm/mach-imx/imx6.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
Applied, thanks
Sascha
>
> diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
> index ba8fb8964ac8..07d3f57d8dcc 100644
> --- a/arch/arm/mach-imx/imx6.c
> +++ b/arch/arm/mach-imx/imx6.c
> @@ -31,10 +31,8 @@ void imx6_init_lowlevel(void)
> {
> void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
> void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR;
> - void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
> bool is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q;
> bool is_imx6d = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6D;
> - uint32_t val;
>
> /*
> * Set all MPROTx to be non-bufferable, trusted for R/W,
> @@ -94,6 +92,13 @@ void imx6_init_lowlevel(void)
> MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
> }
>
> +}
> +
> +void imx6_setup_ipu_qos(void)
> +{
> + void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
> + uint32_t val;
> +
> val = readl(iomux + IOMUXC_GPR4);
> val |= IMX6Q_GPR4_VPU_WR_CACHE_SEL | IMX6Q_GPR4_VPU_RD_CACHE_SEL |
> IMX6Q_GPR4_VPU_P_WR_CACHE_VAL | IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
> @@ -186,6 +191,8 @@ int imx6_init(void)
>
> imx_set_silicon_revision(cputypestr, mx6_silicon_revision);
>
> + imx6_setup_ipu_qos();
> +
> return 0;
> }
>
> --
> 2.8.1
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2016-09-15 11:10 [PATCH 1/3] ARM: imx6: split out IPU QoS setup Lucas Stach
2016-09-15 11:10 ` [PATCH 2/3] ARM: imx6: don't execute IPU QoS setup on MX6 SX/SL Lucas Stach
2016-09-15 11:10 ` [PATCH 3/3] ARM: imx6qp: set NoC regulator to bypass Lucas Stach
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