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From: "Thomas Hämmerle" <Thomas.Haemmerle@wolfvision.net>
To: "barebox@lists.infradead.org" <barebox@lists.infradead.org>
Cc: Michael Tretter <m.tretter@pengutronix.de>
Subject: [PATCH v2 4/4] firmware: zynqmp-fpga: print Xilinx bitstream header
Date: Fri, 25 Oct 2019 12:55:42 +0000	[thread overview]
Message-ID: <1572008129-24020-5-git-send-email-thomas.haemmerle@wolfvision.net> (raw)
In-Reply-To: <1572008129-24020-1-git-send-email-thomas.haemmerle@wolfvision.net>

From: Michael Tretter <m.tretter@pengutronix.de>

The bitstream header has 5 fields, that start with a char for the type.
Four fields have a big-ending length and a null-terminated string for
the design name, the part number, and the date and time of creation. The
last field is a big-endian 32 bit unsigned int for the size of the
bitstream.

Print this info when loading the bitstream.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 drivers/firmware/zynqmp-fpga.c | 51 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/drivers/firmware/zynqmp-fpga.c b/drivers/firmware/zynqmp-fpga.c
index 47862a7..8878658 100644
--- a/drivers/firmware/zynqmp-fpga.c
+++ b/drivers/firmware/zynqmp-fpga.c
@@ -45,6 +45,19 @@ struct fpgamgr {
 	u32 features;
 };
 
+struct bs_header {
+	__be16 length;
+	u8 padding[9];
+	__be16 size;
+	char entries[0];
+} __attribute__ ((packed));
+
+struct bs_header_entry {
+	char type;
+	__be16 length;
+	char data[0];
+} __attribute__ ((packed));
+
 /*
  * Xilinx KU040 Bitstream Composition:
  * Bitstream can be provided with an optinal header (`struct bs_header`).
@@ -143,6 +156,42 @@ static int get_header_length(const char *header, size_t size)
 	return -EINVAL;
 }
 
+static void zynqmp_fpga_show_header(const struct device_d *dev,
+			 struct bs_header *header, size_t size)
+{
+	struct bs_header_entry *entry;
+	unsigned int i;
+	unsigned int length;
+
+	for (i = 0; i < size - sizeof(*header); i += sizeof(*entry) + length) {
+		entry = (struct bs_header_entry *)&header->entries[i];
+		length = __be16_to_cpu(entry->length);
+
+		switch (entry->type) {
+		case 'a':
+			printf("Design: %s\n", entry->data);
+			break;
+		case 'b':
+			printf("Part number: %s\n", entry->data);
+			break;
+		case 'c':
+			printf("Date: %s\n", entry->data);
+			break;
+		case 'd':
+			printf("Time: %s\n", entry->data);
+			break;
+		case 'e':
+			/* Size entry does not have a length but is be32 int */
+			printf("Size: %d bytes\n",
+			       (length << 16) + (entry->data[0] << 8) + entry->data[1]);
+			return;
+		default:
+			dev_warn(dev, "Invalid header entry: %c", entry->type);
+			return;
+		}
+	}
+}
+
 static int fpgamgr_program_finish(struct firmware_handler *fh)
 {
 	struct fpgamgr *mgr = container_of(fh, struct fpgamgr, fh);
@@ -167,6 +216,8 @@ static int fpgamgr_program_finish(struct firmware_handler *fh)
 		status = header_length;
 		goto err_free;
 	}
+	zynqmp_fpga_show_header(&mgr->dev,
+			      (struct bs_header *)mgr->buf, header_length);
 
 	body = (u32 *)&mgr->buf[header_length];
 	body_length = mgr->size - header_length;
-- 
2.7.4


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  parent reply	other threads:[~2019-10-25 12:55 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-24 10:26 [PATCH 0/5] ARM: zynqmp: add support for bitstream loading Thomas Hämmerle
2019-10-24 10:26 ` [PATCH 1/5] ARM: zynqmp: dts: move firmware node to src tree Thomas Hämmerle
2019-10-24 12:56   ` Michael Tretter
2019-10-24 10:26 ` [PATCH 3/5] firmware: zynqmp-fpga: introduce driver to load bitstream to FPGA Thomas Hämmerle
2019-10-24 12:56   ` Michael Tretter
2019-10-24 10:26 ` [PATCH 4/5] ARM: zynqmp: dts: move pcap node to src tree Thomas Hämmerle
2019-10-24 10:26 ` [PATCH 2/5] firmware-zynqmp: extend driver with fpga relavant functions Thomas Hämmerle
2019-10-24 12:56   ` Michael Tretter
2019-10-24 10:26 ` [PATCH 5/5] firmware: zynqmp-fpga: print Xilinx bitstream header Thomas Hämmerle
2019-10-25 12:55 ` [PATCH v2 0/4] ARM: zynqmp: add support for bitstream loading Thomas Hämmerle
2019-10-25 12:55   ` [PATCH v2 2/4] firmware-zynqmp: extend driver with fpga relavant functions Thomas Hämmerle
2019-10-25 12:55   ` [PATCH v2 1/4] firmware-zynqmp: add macros for PMU and trustzone firmware versions Thomas Hämmerle
2019-10-25 12:55   ` Thomas Hämmerle [this message]
2019-10-25 12:55   ` [PATCH v2 3/4] firmware: zynqmp-fpga: introduce driver to load bitstream to FPGA Thomas Hämmerle
2019-10-28 11:00   ` [PATCH v2 0/4] ARM: zynqmp: add support for bitstream loading Sascha Hauer

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