From: Sascha Hauer <s.hauer@pengutronix.de>
To: barebox@lists.infradead.org, Thaison Phan <tsphan42@gmail.com>
Subject: Re: [PATCH] Patch to fix bootm barebox load address alignment to acomodate ADRP instruction
Date: Fri, 01 Mar 2024 10:25:40 +0100 [thread overview]
Message-ID: <170928514052.2408914.7181056061112959949.b4-ty@pengutronix.de> (raw)
In-Reply-To: <CAFPn3sTc_3q04koG_oPnqTmhGnejxtiva+B5KwYsCdC3czCmKw@mail.gmail.com>
On Tue, 06 Feb 2024 21:37:47 -0500, Thaison Phan wrote:
> The aarch64 bootm image handler for barebox can choose a load address
> that is not 4KB aligned. This can result in unexpected behavior with
> the ADRP instruction that is available in 64 bit ARM architectures.
> ADRP forms a PC-relative address to a 4KB page where the bottom 12
> bits of the current PC will be masked out. When the load address of
> the barebox image is not 4KB aligned ADRP can end up forming an
> address that starts from an invalid page of memory or the wrong page
> of memory that was expected to be formed. The following patch aligns
> the load address for the next barebox image to be 4KB aligned to
> accommodate the ADRP instruction.
>
> [...]
Applied, thanks!
[1/1] Patch to fix bootm barebox load address alignment to acomodate ADRP instruction
https://git.pengutronix.de/cgit/barebox/commit/?id=af694bdae717 (link may not be stable)
Best regards,
--
Sascha Hauer <s.hauer@pengutronix.de>
prev parent reply other threads:[~2024-03-01 9:26 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-07 2:37 Thaison Phan
2024-02-08 7:30 ` Sascha Hauer
2024-02-09 1:44 ` Thaison Phan
2024-03-01 9:25 ` Sascha Hauer [this message]
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