From: Sascha Hauer <s.hauer@pengutronix.de>
To: barebox@lists.infradead.org, Marco Felsch <m.felsch@pengutronix.de>
Subject: Re: [PATCH v2 1/2] ARM: aarch64: align scr_el3 register setup with U-Boot
Date: Mon, 17 Jun 2024 08:48:19 +0200 [thread overview]
Message-ID: <171860689973.259338.5476710075653560755.b4-ty@pengutronix.de> (raw)
In-Reply-To: <20240613130659.165278-1-m.felsch@pengutronix.de>
On Thu, 13 Jun 2024 15:06:58 +0200, Marco Felsch wrote:
> Currently we don't honor the setup done by the BootROM. Fix this by
> reading the scr_el3 first and update the corresponding bits afterwards.
>
> Furthermore also align the register settings:
> - Remove the register with (RW) setup since this is done by the EL3
> firmware (TF-A).
> - Set IRQ/FIQ/EA bits to make it possible to handle early exceptions
> within the PBL at EL3. Early exception handling requires platform
> support since it involves exception table and DAIF handling.
>
> [...]
Applied, thanks!
[1/2] ARM: aarch64: align scr_el3 register setup with U-Boot
https://git.pengutronix.de/cgit/barebox/commit/?id=678a5248ec00 (link may not be stable)
[2/2] ARM: i.MX8M: add support to handle ROM SError ERR050350
https://git.pengutronix.de/cgit/barebox/commit/?id=d50745ce72e0 (link may not be stable)
Best regards,
--
Sascha Hauer <s.hauer@pengutronix.de>
prev parent reply other threads:[~2024-06-17 6:49 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-13 13:06 Marco Felsch
2024-06-13 13:06 ` [PATCH v2 2/2] ARM: i.MX8M: add support to handle ROM SError ERR050350 Marco Felsch
2024-06-17 6:49 ` Sascha Hauer
2024-06-25 8:19 ` Marco Felsch
2024-06-17 6:48 ` Sascha Hauer [this message]
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