From: Sascha Hauer <s.hauer@pengutronix.de>
To: Barebox List <barebox@lists.infradead.org>,
Sascha Hauer <s.hauer@pengutronix.de>
Cc: Lars Schmidt <l.schmidt@pengutronix.de>
Subject: Re: [PATCH] mci: am654-sdhci: Clear SDHCI_CTRL_HISPD bit for some speed modes
Date: Tue, 27 May 2025 14:38:16 +0200 [thread overview]
Message-ID: <174834949645.83881.4811460348523768024.b4-ty@pengutronix.de> (raw)
In-Reply-To: <20250515143219.1633351-1-s.hauer@pengutronix.de>
On Thu, 15 May 2025 16:32:19 +0200, Sascha Hauer wrote:
> Normally we would set the SDHCI_CTRL_HISPD bit for MMC_TIMING_SD_HS and
> MMC_TIMING_MMC_HS. This however doesn't seem to work on AM62x and AM62L
> SoCs.
>
> Based on U-Boot commit 27a87c834fd ("mmc: am654_sdhci: Fix HISPD bit
> configuration in some lower speed modes") clear the SDHCI_CTRL_HISPD bit
> in these modes. Unfortunately I can't find the information in the data
> sheet referenced in that commit, so I can't verify it, but it seems
> to be necessary not only on AM6548, but on other SoCs as well.
>
> [...]
Applied, thanks!
[1/1] mci: am654-sdhci: Clear SDHCI_CTRL_HISPD bit for some speed modes
https://git.pengutronix.de/cgit/barebox/commit/?id=ddfc40f2137f (link may not be stable)
Best regards,
--
Sascha Hauer <s.hauer@pengutronix.de>
prev parent reply other threads:[~2025-05-27 12:38 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-15 14:32 Sascha Hauer
2025-05-27 12:38 ` Sascha Hauer [this message]
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