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* [PATCH 1/2] dma: apbh: pass integer, not pointer as value to writel
@ 2025-06-02  6:20 Ahmad Fatoum
  2025-06-02  6:20 ` [PATCH 2/2] ARM: Arria10: xload: don't check writel return value Ahmad Fatoum
  2025-06-02  7:43 ` [PATCH 1/2] dma: apbh: pass integer, not pointer as value to writel Sascha Hauer
  0 siblings, 2 replies; 3+ messages in thread
From: Ahmad Fatoum @ 2025-06-02  6:20 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

In preparation for enforcing that at least the value of writeX is an
integer, a number of places writing a pointer were noticed.

Add a virt_to_phys to paper over this with a comment that this is not
completely correct.

Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
 drivers/dma/apbh_dma.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index 298f706f1bcd..fb8b6b304cf0 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -103,6 +103,7 @@ int mxs_dma_go(int chan, struct mxs_dma_cmd *cmd, int ncmds)
 	struct apbh_dma *apbh = apbh_dma;
 	uint32_t timeout = 10000;
 	int i, ret, channel_bit;
+	dma_addr_t dma;
 
 	ret = mxs_dma_validate_chan(chan);
 	if (ret)
@@ -113,12 +114,18 @@ int mxs_dma_go(int chan, struct mxs_dma_cmd *cmd, int ncmds)
 		cmd[i].data |= MXS_DMA_DESC_CHAIN;
 	}
 
+	/*
+	 * TODO: cmd is in DMA coherent memory, but it uses DMA_ADDRESS_BROKEN,
+	 * and thus assumes a 1:1 mapping here
+	 */
+	dma = virt_to_phys(cmd);
+
 	if (apbh_dma_is_imx23(apbh)) {
-		writel(cmd, apbh->regs + HW_APBHX_CHn_NXTCMDAR_MX23(chan));
+		writel(dma, apbh->regs + HW_APBHX_CHn_NXTCMDAR_MX23(chan));
 		writel(1, apbh->regs + HW_APBHX_CHn_SEMA_MX23(chan));
 		channel_bit = chan + BP_APBH_CTRL0_CLKGATE_CHANNEL;
 	} else {
-		writel(cmd, apbh->regs + HW_APBHX_CHn_NXTCMDAR_MX28(chan));
+		writel(dma, apbh->regs + HW_APBHX_CHn_NXTCMDAR_MX28(chan));
 		writel(1, apbh->regs + HW_APBHX_CHn_SEMA_MX28(chan));
 		channel_bit = chan;
 	}
-- 
2.39.5




^ permalink raw reply	[flat|nested] 3+ messages in thread

* [PATCH 2/2] ARM: Arria10: xload: don't check writel return value
  2025-06-02  6:20 [PATCH 1/2] dma: apbh: pass integer, not pointer as value to writel Ahmad Fatoum
@ 2025-06-02  6:20 ` Ahmad Fatoum
  2025-06-02  7:43 ` [PATCH 1/2] dma: apbh: pass integer, not pointer as value to writel Sascha Hauer
  1 sibling, 0 replies; 3+ messages in thread
From: Ahmad Fatoum @ 2025-06-02  6:20 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

No one checks a10_update_bits()'s return value, which is good as
return value has no indication over operation success anyway.

Make it void and fix this.

Signed-off-by: Ahmad Fatoum <a.fatoum@barebox.org>
---
 arch/arm/mach-socfpga/arria10-xload.c | 7 ++-----
 include/mach/socfpga/arria10-xload.h  | 2 +-
 2 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-socfpga/arria10-xload.c b/arch/arm/mach-socfpga/arria10-xload.c
index fb87135ca94a..4c8f9c7f0e55 100644
--- a/arch/arm/mach-socfpga/arria10-xload.c
+++ b/arch/arm/mach-socfpga/arria10-xload.c
@@ -16,20 +16,17 @@
 #include <mach/socfpga/generic.h>
 #include <linux/sizes.h>
 
-int a10_update_bits(unsigned int reg, unsigned int mask,
+void a10_update_bits(unsigned int reg, unsigned int mask,
 		    unsigned int val)
 {
 	unsigned int tmp, orig;
-	int ret = 0;
 
 	orig = readl(ARRIA10_FPGAMGRREGS_ADDR + reg);
 	tmp = orig & ~mask;
 	tmp |= val & mask;
 
 	if (tmp != orig)
-		ret = writel(tmp, ARRIA10_FPGAMGRREGS_ADDR + reg);
-
-	return ret;
+		writel(tmp, ARRIA10_FPGAMGRREGS_ADDR + reg);
 }
 
 static uint32_t socfpga_a10_fpga_read_stat(void)
diff --git a/include/mach/socfpga/arria10-xload.h b/include/mach/socfpga/arria10-xload.h
index c58ab7f8cfd2..b7f100d90a96 100644
--- a/include/mach/socfpga/arria10-xload.h
+++ b/include/mach/socfpga/arria10-xload.h
@@ -6,7 +6,7 @@
 void arria10_init_mmc(void);
 int arria10_prepare_mmc(int barebox_part, int rbf_part);
 int arria10_read_blocks(void *dst, int blocknum, size_t len);
-int a10_update_bits(unsigned int reg, unsigned int mask, unsigned int val);
+void a10_update_bits(unsigned int reg, unsigned int mask, unsigned int val);
 
 struct partition {
 	uint64_t first_sec;
-- 
2.39.5




^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH 1/2] dma: apbh: pass integer, not pointer as value to writel
  2025-06-02  6:20 [PATCH 1/2] dma: apbh: pass integer, not pointer as value to writel Ahmad Fatoum
  2025-06-02  6:20 ` [PATCH 2/2] ARM: Arria10: xload: don't check writel return value Ahmad Fatoum
@ 2025-06-02  7:43 ` Sascha Hauer
  1 sibling, 0 replies; 3+ messages in thread
From: Sascha Hauer @ 2025-06-02  7:43 UTC (permalink / raw)
  To: barebox, Ahmad Fatoum


On Mon, 02 Jun 2025 08:20:19 +0200, Ahmad Fatoum wrote:
> In preparation for enforcing that at least the value of writeX is an
> integer, a number of places writing a pointer were noticed.
> 
> Add a virt_to_phys to paper over this with a comment that this is not
> completely correct.
> 
> 
> [...]

Applied, thanks!

[1/2] dma: apbh: pass integer, not pointer as value to writel
      https://git.pengutronix.de/cgit/barebox/commit/?id=5b273a2603da (link may not be stable)
[2/2] ARM: Arria10: xload: don't check writel return value
      https://git.pengutronix.de/cgit/barebox/commit/?id=b887a5b9297f (link may not be stable)

Best regards,
-- 
Sascha Hauer <s.hauer@pengutronix.de>




^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2025-06-02  7:44 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2025-06-02  6:20 [PATCH 1/2] dma: apbh: pass integer, not pointer as value to writel Ahmad Fatoum
2025-06-02  6:20 ` [PATCH 2/2] ARM: Arria10: xload: don't check writel return value Ahmad Fatoum
2025-06-02  7:43 ` [PATCH 1/2] dma: apbh: pass integer, not pointer as value to writel Sascha Hauer

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