From: Sascha Hauer <s.hauer@pengutronix.de>
To: barebox@lists.infradead.org,
Alexander Shiyan <eagle.alexander923@gmail.com>
Subject: Re: [PATCH] clk: rockchip: Fix CPLL setup on RK3588
Date: Mon, 29 Sep 2025 15:51:10 +0200 [thread overview]
Message-ID: <175915387016.3277379.11438170659820524492.b4-ty@pengutronix.de> (raw)
In-Reply-To: <20250929123239.838390-1-eagle.alexander923@gmail.com>
On Mon, 29 Sep 2025 15:32:39 +0300, Alexander Shiyan wrote:
> This patch fixes the CPLL clock setup issue on RK3588 SoCs by temporarily
> disabling the PLL source during PLL configuration. The fix is ported from
> Rockchip's U-Boot implementation [1].
>
> The issue occurs because CPLL requires its source to be disabled during
> configuration. We temporarily set the corresponding bit in the CRU
> register before PLL setup and restore it afterwards [2].
>
> [...]
Applied, thanks!
[1/1] clk: rockchip: Fix CPLL setup on RK3588
https://git.pengutronix.de/cgit/barebox/commit/?id=8b01023c3c7c (link may not be stable)
Best regards,
--
Sascha Hauer <s.hauer@pengutronix.de>
prev parent reply other threads:[~2025-09-29 13:52 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-29 12:32 Alexander Shiyan
2025-09-29 13:51 ` Sascha Hauer [this message]
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