From: Sascha Hauer <s.hauer@pengutronix.de>
To: Barebox List <barebox@lists.infradead.org>,
Sascha Hauer <s.hauer@pengutronix.de>
Cc: Michael Tretter <mtr@pengutronix.de>,
Alexander Shiyan <eagle.alexander923@gmail.com>
Subject: Re: [PATCH v2] clk: rockchip rk3588: configure CPLL in driver
Date: Fri, 14 Nov 2025 13:59:41 +0100 [thread overview]
Message-ID: <176312518155.3977625.17978250835273333874.b4-ty@pengutronix.de> (raw)
In-Reply-To: <20251028072625.2781087-1-s.hauer@pengutronix.de>
On Tue, 28 Oct 2025 08:26:25 +0100, Sascha Hauer wrote:
> The rk3588 CPLL should be configured to 1.5GHz and 09c87c85e0 ("ARM:
> dts: rockchip: Set CPLL frequency for RK3588") does this. It does it
> however after the assigned-clocks/assigned-clock-rates properties of the
> "rockchip,rk3588-cru" node have been evaluated which contain a setting
> of CLK_150M_SRC which is a child clock of the CPLL. Configuring the
> CPLL after CLK_150M_SRC alters the setting of the just configured 150M
> clock again.
>
> [...]
Applied, thanks!
[1/1] clk: rockchip rk3588: configure CPLL in driver
https://git.pengutronix.de/cgit/barebox/commit/?id=45b4b47cc650 (link may not be stable)
Best regards,
--
Sascha Hauer <s.hauer@pengutronix.de>
prev parent reply other threads:[~2025-11-14 13:00 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-28 7:26 Sascha Hauer
2025-10-28 10:00 ` Michael Tretter
2025-11-14 12:59 ` Sascha Hauer [this message]
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