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* [PATCH master] net: am65-cpsw-nuss: fix up PHY mode for fixed RGMII TX delay
@ 2026-02-25 14:02 Ahmad Fatoum
  2026-02-25 14:28 ` Sascha Hauer
  0 siblings, 1 reply; 2+ messages in thread
From: Ahmad Fatoum @ 2026-02-25 14:02 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

To restore compatibility with newer Linux device trees and fix network
breakage on Beagleplay, import following U-Boot commit:

| commit 4b10bcfdef9cb544ca80988fe36d307a622bcd21
| Author:     Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
| AuthorDate: Tue Sep 30 10:05:11 2025 +0200
| Commit:     Tom Rini <trini@konsulko.com>
| CommitDate: Fri Oct 10 11:07:44 2025 -0600
|
|     net: ethernet: ti: am65-cpsw: fix up PHY mode for fixed RGMII TX delay
|
|     The am65-cpsw driver currently sets the SEL_RGMII_IDMODE flag in a MAC's
|     mode register to enable or disable the TX delay. While this was supported
|     for earlier generations of the CPSW controller, the datasheets of all
|     modern TI SoCs using the am65-cpsw MAC state that the TX delay is fixed,
|     and the SEL_RGMII_IDMODE bit is documented as reserved in most of them.
|     Furthermore, while it was found that this bit does in fact disable the TX
|     delay, [1] states that this setting is truly unsupported by TI and not
|     just undocumented.
|
|     Following the clarification of the rgmii* phy-mode values in the Linux
|     DT bindings in [2], the Linux am65-cpsw driver was changed in [3] to
|     account for the fixed TX delay by fixing up the mode passed to the PHY
|     driver; a similar fixup already existed in the TI icssg-prueth driver.
|     [4] followed up on this by explicitly clearing the SEL_RGMII_IDMODE flag
|     to handle the case where it is set by the bootloader or other firmware
|     before Linux.
|
|     With the above changes, Device Trees that set the recommended "rgmii-id"
|     mode are now appearing in Linux 6.17+. Avoid setting the unsupported
|     SEL_RGMII_IDMODE flag for such Device Trees, and instead fix up the PHY
|     interface mode, thus aligning the U-Boot driver with the Linux kernel.
|
|     [1] https://www.spinics.net/lists/netdev/msg1112647.html
|     [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c360eb0c3ccb95306704fd221442283ee82f1f58
|     [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ca13b249f291f4920466638d1adbfb3f9c8db6e9
|     [4] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a22d3b0d49d411e64ed07e30c2095035ecb30ed2
|
|     Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>

Fixes: a3bf6c16f77d ("dts: update to v6.19-rc1")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 drivers/net/am65-cpsw-nuss.c | 43 +++++++++++++++++++++++-------------
 1 file changed, 28 insertions(+), 15 deletions(-)

diff --git a/drivers/net/am65-cpsw-nuss.c b/drivers/net/am65-cpsw-nuss.c
index 6b5a5d9533bf..66116338a96b 100644
--- a/drivers/net/am65-cpsw-nuss.c
+++ b/drivers/net/am65-cpsw-nuss.c
@@ -195,14 +195,11 @@ static void am65_cpsw_update_link(struct eth_device *edev)
 #define AM65_GMII_SEL_MODE_RGMII	2
 #define AM65_GMII_SEL_MODE_SGMII	3
 
-#define AM65_GMII_SEL_RGMII_IDMODE	BIT(4)
-
 static int am65_cpsw_gmii_sel_k3(struct am65_cpsw_port *port,
 				 phy_interface_t phy_mode)
 {
 	struct device *dev = &port->dev;
 	u32 offset, reg;
-	bool rgmii_id = false;
 	struct regmap *gmii_sel;
 	u32 mode = 0;
 	int ret;
@@ -229,12 +226,6 @@ static int am65_cpsw_gmii_sel_k3(struct am65_cpsw_port *port,
 		mode = AM65_GMII_SEL_MODE_RGMII;
 		break;
 
-	case PHY_INTERFACE_MODE_RGMII_ID:
-	case PHY_INTERFACE_MODE_RGMII_TXID:
-		mode = AM65_GMII_SEL_MODE_RGMII;
-		rgmii_id = true;
-		break;
-
 	case PHY_INTERFACE_MODE_SGMII:
 		mode = AM65_GMII_SEL_MODE_SGMII;
 		break;
@@ -249,9 +240,6 @@ static int am65_cpsw_gmii_sel_k3(struct am65_cpsw_port *port,
 		break;
 	};
 
-	if (rgmii_id)
-		mode |= AM65_GMII_SEL_RGMII_IDMODE;
-
 	reg = mode;
 	dev_dbg(dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n",
 		phy_mode, reg);
@@ -594,11 +582,36 @@ static int am65_cpsw_ofdata_parse_phy(struct am65_cpsw_port *port)
 {
 	int ret;
 
+
 	ret = of_get_phy_mode(port->device_node);
-	if (ret < 0)
+	if (ret < 0) {
+		dev_warn(&port->dev, "Invalid PHY mode, port %u\n", port->port_id);
 		port->interface = PHY_INTERFACE_MODE_MII;
-	else
-		port->interface = ret;
+		return 0;
+	}
+
+	port->interface = ret;
+
+	/* CPSW controllers supported by this driver have a fixed
+	 * internal TX delay in RGMII mode. Fix up PHY mode to account
+	 * for this and warn about Device Trees that claim to have a TX
+	 * delay on the PCB.
+	 */
+	switch (port->interface) {
+	case PHY_INTERFACE_MODE_RGMII_ID:
+		port->interface = PHY_INTERFACE_MODE_RGMII_RXID;
+		break;
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		port->interface = PHY_INTERFACE_MODE_RGMII;
+		break;
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+		dev_warn(&port->dev,
+			 "RGMII mode without internal TX delay unsupported; please fix your Device Tree\n");
+		break;
+	default:
+		break;
+	}
 
 	return 0;
 }
-- 
2.47.3




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2026-02-25 14:02 [PATCH master] net: am65-cpsw-nuss: fix up PHY mode for fixed RGMII TX delay Ahmad Fatoum
2026-02-25 14:28 ` Sascha Hauer

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