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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" X-SA-Exim-Connect-IP: 2001:8b0:10b:1:d65d:64ff:fe57:4e05 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-2.8 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: [PATCH 7/9] RISC-V: add initial LiteX SoC support X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) On Wed, 2021-05-05 at 13:08 +0300, Antony Pavlov wrote: > LiteX is a Migen-based System on Chip, supporting softcore > VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU. > > See https://github.com/enjoy-digital/litex and > https://github.com/litex-hub/linux-on-litex-vexriscv > for details. > > Signed-off-by: Antony Pavlov > --- > > > +config MACH_LITEX > + bool "litex family" > + select ARCH_RV32I > + select HAS_DEBUG_LL > + select HAS_NMON > + select USE_COMPRESSED_DTB > + select RISCV_SBI > + Hmm, there is also https://github.com/litex-hub/linux-on-litex-rocket/ which uses the 64-bit RocketChip CPU. How would that fit into this naming scheme? Would it be a different MACH? > +/dts-v1/; > + > +/ { > + compatible = "litex,vexriscv-soc-linux"; > + > + #address-cells = <1>; > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox