* [PATCH 2/5] Add EP93xx ethernet driver
@ 2010-01-12 19:30 Matthias Kaehlcke
0 siblings, 0 replies; 3+ messages in thread
From: Matthias Kaehlcke @ 2010-01-12 19:30 UTC (permalink / raw)
To: barebox
Added ethernet driver for EP93xx SoCs
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
---
drivers/net/Kconfig | 5 +
drivers/net/Makefile | 1 +
drivers/net/ep93xx.c | 676 ++++++++++++++++++++++++++++++++++++++++++++++++++
drivers/net/ep93xx.h | 147 +++++++++++
include/common.h | 1 +
5 files changed, 830 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/ep93xx.c
create mode 100644 drivers/net/ep93xx.h
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index ed7656e..0955562 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -64,6 +64,11 @@ config DRIVER_NET_FEC_IMX
depends on ARCH_HAS_FEC_IMX
select MIIPHY
+config DRIVER_NET_EP93XX
+ bool "EP93xx Ethernet driver"
+ depends on ARCH_EP93XX
+ select MIIPHY
+
config DRIVER_NET_MACB
bool "macb Ethernet driver"
depends on ARCH_AT91
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 6751920..1b6f104 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_DRIVER_NET_NETX) += netx_eth.o
obj-$(CONFIG_DRIVER_NET_AT91_ETHER) += at91_ether.o
obj-$(CONFIG_DRIVER_NET_MPC5200) += fec_mpc5200.o
obj-$(CONFIG_DRIVER_NET_FEC_IMX) += fec_imx.o
+obj-$(CONFIG_DRIVER_NET_EP93XX) += ep93xx.o
obj-$(CONFIG_DRIVER_NET_MACB) += macb.o
obj-$(CONFIG_DRIVER_NET_TAP) += tap.o
obj-$(CONFIG_MIIPHY) += miiphy.o
diff --git a/drivers/net/ep93xx.c b/drivers/net/ep93xx.c
new file mode 100644
index 0000000..aa1a005
--- /dev/null
+++ b/drivers/net/ep93xx.c
@@ -0,0 +1,676 @@
+/*
+ * Cirrus Logic EP93xx ethernet MAC / MII driver.
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver,
+ * which is
+ *
+ * (C) Copyright 2002 2003
+ * Adam Bezanson, Network Audio Technologies, Inc.
+ * <bezanson@netaudiotech.com>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <linux/types.h>
+#include <mach/ep93xx-regs.h>
+#include "ep93xx.h"
+
+static int ep93xx_eth_send_packet(struct eth_device *edev,
+ void *packet, int length);
+static int ep93xx_eth_rcv_packet(struct eth_device *edev);
+
+static int ep93xx_phy_read(struct miiphy_device *mdev, uint8_t phy_addr,
+ uint8_t phy_reg, uint16_t *value);
+static int ep93xx_phy_write(struct miiphy_device *mdev, uint8_t phy_addr,
+ uint8_t phy_reg, uint16_t value);
+
+static inline struct ep93xx_eth_priv *ep93xx_get_priv(struct eth_device *edev)
+{
+ return (struct ep93xx_eth_priv *)edev->priv;
+}
+
+static inline struct mac_regs *ep93xx_get_regs(struct eth_device *edev)
+{
+ struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
+
+ return priv->regs;
+}
+
+#if defined(EP93XX_MAC_DEBUG)
+/**
+ * Dump ep93xx_mac values to the terminal.
+ */
+inline void dump_dev(struct eth_device *edev)
+{
+ struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
+ int i;
+
+ printf("\ndump_dev()\n");
+ printf(" rx_dq.base %08X\n", priv->rx_dq.base);
+ printf(" rx_dq.current %08X\n", priv->rx_dq.current);
+ printf(" rx_dq.end %08X\n", priv->rx_dq.end);
+ printf(" rx_sq.base %08X\n", priv->rx_sq.base);
+ printf(" rx_sq.current %08X\n", priv->rx_sq.current);
+ printf(" rx_sq.end %08X\n", priv->rx_sq.end);
+
+ for (i = 0; i < NUMRXDESC; i++)
+ printf(" rx_buffer[%2.d] %08X\n", i, NetRxPackets[i]);
+
+ printf(" tx_dq.base %08X\n", priv->tx_dq.base);
+ printf(" tx_dq.current %08X\n", priv->tx_dq.current);
+ printf(" tx_dq.end %08X\n", priv->tx_dq.end);
+ printf(" tx_sq.base %08X\n", priv->tx_sq.base);
+ printf(" tx_sq.current %08X\n", priv->tx_sq.current);
+ printf(" tx_sq.end %08X\n", priv->tx_sq.end);
+}
+
+/**
+ * Dump all RX descriptor queue entries to the terminal.
+ */
+inline void dump_rx_descriptor_queue(struct eth_device *edev)
+{
+ struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
+ int i;
+
+ printf("\ndump_rx_descriptor_queue()\n");
+ printf(" descriptor address word1 word2\n");
+ for (i = 0; i < NUMRXDESC; i++) {
+ printf(" [ %08X ] %08X %08X\n",
+ (priv->rx_dq.base + i),
+ (priv->rx_dq.base + i)->word1,
+ (priv->rx_dq.base + i)->word2);
+ }
+}
+
+/**
+ * Dump all RX status queue entries to the terminal.
+ */
+inline void dump_rx_status_queue(void)
+{
+ struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
+ int i;
+
+ printf("\ndump_rx_status_queue()\n");
+ printf(" descriptor address word1 word2\n");
+ for (i = 0; i < NUMRXDESC; i++) {
+ printf(" [ %08X ] %08X %08X\n",
+ (priv->rx_sq.base + i),
+ (priv->rx_sq.base + i)->word1,
+ (priv->rx_sq.base + i)->word2);
+ }
+}
+
+/**
+ * Dump all TX descriptor queue entries to the terminal.
+ */
+inline void dump_tx_descriptor_queue(void)
+{
+ struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
+ int i;
+
+ printf("\ndump_tx_descriptor_queue()\n");
+ printf(" descriptor address word1 word2\n");
+ for (i = 0; i < NUMTXDESC; i++) {
+ printf(" [ %08X ] %08X %08X\n",
+ (priv->tx_dq.base + i),
+ (priv->tx_dq.base + i)->word1,
+ (priv->tx_dq.base + i)->word2);
+ }
+}
+
+/**
+ * Dump all TX status queue entries to the terminal.
+ */
+inline void dump_tx_status_queue(void)
+{
+ struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
+ int i;
+
+ printf("\ndump_tx_status_queue()\n");
+ printf(" descriptor address word1\n");
+ for (i = 0; i < NUMTXDESC; i++) {
+ printf(" [ %08X ] %08X\n",
+ (priv->rx_sq.base + i),
+ (priv->rx_sq.base + i)->word1);
+ }
+}
+#else
+#define dump_dev(x)
+#define dump_rx_descriptor_queue()
+#define dump_rx_status_queue()
+#define dump_tx_descriptor_queue()
+#define dump_tx_status_queue()
+#endif /* defined(EP93XX_MAC_DEBUG) */
+
+/**
+ * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
+ * it's cleared.
+ */
+static void ep93xx_eth_reset(struct eth_device *edev)
+{
+ struct mac_regs *regs = ep93xx_get_regs(edev);
+ uint32_t value;
+
+ pr_debug("+ep93xx_eth_reset\n");
+
+ value = readl(®s->selfctl);
+ value |= SELFCTL_RESET;
+ writel(value, ®s->selfctl);
+
+ while (readl(®s->selfctl) & SELFCTL_RESET)
+ ; /* noop */
+
+ pr_debug("-ep93xx_eth_reset\n");
+}
+
+static int ep93xx_eth_init_dev(struct eth_device *edev)
+{
+ pr_debug("+ep93xx_eth_init_dev\n");
+
+ pr_debug("-ep93xx_eth_init_dev\n");
+
+ return 0;
+}
+
+static int ep93xx_eth_open(struct eth_device *edev)
+{
+ struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
+ struct mac_regs *regs = ep93xx_get_regs(edev);
+ int i;
+
+ pr_debug("+ep93xx_eth_open\n");
+
+ ep93xx_eth_reset(edev);
+
+ /* Reset the descriptor queues' current and end address values */
+ priv->tx_dq.current = priv->tx_dq.base;
+ priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC);
+
+ priv->tx_sq.current = priv->tx_sq.base;
+ priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC);
+
+ priv->rx_dq.current = priv->rx_dq.base;
+ priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC);
+
+ priv->rx_sq.current = priv->rx_sq.base;
+ priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC);
+
+ /*
+ * Set the transmit descriptor and status queues' base address,
+ * current address, and length registers. Set the maximum frame
+ * length and threshold. Enable the transmit descriptor processor.
+ */
+ writel((uint32_t)priv->tx_dq.base, ®s->txdq.badd);
+ writel((uint32_t)priv->tx_dq.base, ®s->txdq.curadd);
+ writel(sizeof(struct tx_descriptor) * NUMTXDESC, ®s->txdq.blen);
+
+ writel((uint32_t)priv->tx_sq.base, ®s->txstsq.badd);
+ writel((uint32_t)priv->tx_sq.base, ®s->txstsq.curadd);
+ writel(sizeof(struct tx_status) * NUMTXDESC, ®s->txstsq.blen);
+
+ writel(0x00040000, ®s->txdthrshld);
+ writel(0x00040000, ®s->txststhrshld);
+
+ writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), ®s->maxfrmlen);
+ writel(BMCTL_TXEN, ®s->bmctl);
+
+ /*
+ * Set the receive descriptor and status queues' base address,
+ * current address, and length registers. Enable the receive
+ * descriptor processor.
+ */
+ writel((uint32_t)priv->rx_dq.base, ®s->rxdq.badd);
+ writel((uint32_t)priv->rx_dq.base, ®s->rxdq.curadd);
+ writel(sizeof(struct rx_descriptor) * NUMRXDESC, ®s->rxdq.blen);
+
+ writel((uint32_t)priv->rx_sq.base, ®s->rxstsq.badd);
+ writel((uint32_t)priv->rx_sq.base, ®s->rxstsq.curadd);
+ writel(sizeof(struct rx_status) * NUMRXDESC, ®s->rxstsq.blen);
+
+ writel(0x00040000, ®s->rxdthrshld);
+
+ writel(BMCTL_RXEN, ®s->bmctl);
+
+ writel(0x00040000, ®s->rxststhrshld);
+
+ /* Wait until the receive descriptor processor is active */
+ while (!(readl(®s->bmsts) & BMSTS_RXACT))
+ ; /* noop */
+
+ /*
+ * Initialize the RX descriptor queue. Clear the TX descriptor queue.
+ * Clear the RX and TX status queues. Enqueue the RX descriptor and
+ * status entries to the MAC.
+ */
+ for (i = 0; i < NUMRXDESC; i++) {
+ /* set buffer address */
+ (priv->rx_dq.base + i)->word1 = (uint32_t)NetRxPackets[i];
+
+ /* set buffer length, clear buffer index and NSOF */
+ (priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN;
+ }
+
+ memset(priv->tx_dq.base, 0,
+ (sizeof(struct tx_descriptor) * NUMTXDESC));
+ memset(priv->rx_sq.base, 0,
+ (sizeof(struct rx_status) * NUMRXDESC));
+ memset(priv->tx_sq.base, 0,
+ (sizeof(struct tx_status) * NUMTXDESC));
+
+ writel(NUMRXDESC, ®s->rxdqenq);
+ writel(NUMRXDESC, ®s->rxstsqenq);
+
+ /* Turn on RX and TX */
+ writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON |
+ RXCTL_RCRCA | RXCTL_MA, ®s->rxctl);
+ writel(TXCTL_STXON, ®s->txctl);
+
+ /* Dump data structures if we're debugging */
+ dump_dev();
+ dump_rx_descriptor_queue();
+ dump_rx_status_queue();
+ dump_tx_descriptor_queue();
+ dump_tx_status_queue();
+
+ pr_debug("-ep93xx_eth_open\n");
+
+ return 0;
+}
+
+/**
+ * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
+ * registers.
+ */
+static void ep93xx_eth_halt(struct eth_device *edev)
+{
+ struct mac_regs *regs = ep93xx_get_regs(edev);
+
+ pr_debug("+ep93xx_eth_halt\n");
+
+ writel(0x00000000, ®s->rxctl);
+ writel(0x00000000, ®s->txctl);
+
+ pr_debug("-ep93xx_eth_halt\n");
+}
+
+static int ep93xx_eth_get_ethaddr(struct eth_device *edev,
+ unsigned char *mac_addr)
+{
+ struct mac_regs *regs = ep93xx_get_regs(edev);
+ uint32_t value;
+
+ value = readl(®s->indad);
+ mac_addr[0] = value & 0xFF;
+ mac_addr[1] = (value >> 8) & 0xFF;
+ mac_addr[2] = (value >> 16) & 0xFF;
+ mac_addr[3] = (value >> 24) & 0xFF;
+
+ value = readl(®s->indad_upper);
+ mac_addr[4] = value & 0xFF;
+ mac_addr[5] = (value >> 8) & 0xFF;
+
+ return 0;
+}
+
+static int ep93xx_eth_set_ethaddr(struct eth_device *edev,
+ unsigned char *mac_addr)
+{
+ struct mac_regs *regs = ep93xx_get_regs(edev);
+
+ writel(AFP_IAPRIMARY, ®s->afp);
+
+ writel(mac_addr[0] | (mac_addr[1] << 8) |
+ (mac_addr[2] << 16) | (mac_addr[3] << 24),
+ ®s->indad);
+ writel(mac_addr[4] | (mac_addr[5] << 8), ®s->indad_upper);
+
+ return 0;
+}
+
+static int ep93xx_eth_probe(struct device_d *dev)
+{
+ struct eth_device *edev;
+ struct ep93xx_eth_priv *priv;
+ int ret = -1;
+
+ pr_debug("ep93xx_eth_probe()\n");
+
+ edev = xzalloc(sizeof(struct eth_device) +
+ sizeof(struct ep93xx_eth_priv));
+ dev->type_data = edev;
+ edev->priv = (struct ep93xx_eth_priv *)(edev + 1);
+
+ priv = edev->priv;
+ priv->regs = (struct mac_regs *)MAC_BASE;
+
+ edev->init = ep93xx_eth_init_dev;
+ edev->open = ep93xx_eth_open;
+ edev->send = ep93xx_eth_send_packet;
+ edev->recv = ep93xx_eth_rcv_packet;
+ edev->halt = ep93xx_eth_halt;
+ edev->get_ethaddr = ep93xx_eth_get_ethaddr;
+ edev->set_ethaddr = ep93xx_eth_set_ethaddr;
+
+ priv->miiphy.read = ep93xx_phy_read;
+ priv->miiphy.write = ep93xx_phy_write;
+ priv->miiphy.address = 0;
+ priv->miiphy.flags = 0;
+
+ priv->tx_dq.base = calloc(NUMTXDESC,
+ sizeof(struct tx_descriptor));
+ if (priv->tx_dq.base == NULL) {
+ pr_err("calloc() failed: tx_dq.base");
+ goto eth_probe_failed_0;
+ }
+
+ priv->tx_sq.base = calloc(NUMTXDESC,
+ sizeof(struct tx_status));
+ if (priv->tx_sq.base == NULL) {
+ pr_err("calloc() failed: tx_sq.base");
+ goto eth_probe_failed_1;
+ }
+
+ priv->rx_dq.base = calloc(NUMRXDESC,
+ sizeof(struct rx_descriptor));
+ if (priv->rx_dq.base == NULL) {
+ pr_err("calloc() failed: rx_dq.base");
+ goto eth_probe_failed_2;
+ }
+
+ priv->rx_sq.base = calloc(NUMRXDESC,
+ sizeof(struct rx_status));
+ if (priv->rx_sq.base == NULL) {
+ pr_err("calloc() failed: rx_sq.base");
+ goto eth_probe_failed_3;
+ }
+
+ miiphy_register(&priv->miiphy);
+ eth_register(edev);
+
+ ret = 0;
+
+ goto eth_probe_done;
+
+eth_probe_failed_3:
+ free(priv->rx_dq.base);
+ /* Fall through */
+
+eth_probe_failed_2:
+ free(priv->tx_sq.base);
+ /* Fall through */
+
+eth_probe_failed_1:
+ free(priv->tx_dq.base);
+ /* Fall through */
+
+eth_probe_failed_0:
+ /* Fall through */
+
+eth_probe_done:
+ return ret;
+}
+
+/**
+ * Copy a frame of data from the MAC into the protocol layer for further
+ * processing.
+ */
+static int ep93xx_eth_rcv_packet(struct eth_device *edev)
+{
+ struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
+ struct mac_regs *regs = ep93xx_get_regs(edev);
+ int ret = -1;
+
+ pr_debug("+ep93xx_eth_rcv_packet\n");
+
+ if (RX_STATUS_RFP(priv->rx_sq.current)) {
+ if (RX_STATUS_RWE(priv->rx_sq.current)) {
+ /*
+ * We have a good frame. Extract the frame's length
+ * from the current rx_status_queue entry, and copy
+ * the frame's data into NetRxPackets[] of the
+ * protocol stack. We track the total number of
+ * bytes in the frame (nbytes_frame) which will be
+ * used when we pass the data off to the protocol
+ * layer via NetReceive().
+ */
+ NetReceive((uchar *)priv->rx_dq.current->word1,
+ RX_STATUS_FRAME_LEN(priv->rx_sq.current));
+ pr_debug("reporting %d bytes...\n",
+ RX_STATUS_FRAME_LEN(priv->rx_sq.current));
+
+ ret = 0;
+
+ } else {
+ /* Do we have an erroneous packet? */
+ pr_err("packet rx error, status %08X %08X\n",
+ priv->rx_sq.current->word1,
+ priv->rx_sq.current->word2);
+ dump_rx_descriptor_queue();
+ dump_rx_status_queue();
+ }
+
+ /*
+ * Clear the associated status queue entry, and
+ * increment our current pointers to the next RX
+ * descriptor and status queue entries (making sure
+ * we wrap properly).
+ */
+ memset((void *)priv->rx_sq.current, 0,
+ sizeof(struct rx_status));
+
+ priv->rx_sq.current++;
+ if (priv->rx_sq.current >= priv->rx_sq.end)
+ priv->rx_sq.current = priv->rx_sq.base;
+
+ priv->rx_dq.current++;
+ if (priv->rx_dq.current >= priv->rx_dq.end)
+ priv->rx_dq.current = priv->rx_dq.base;
+
+ /*
+ * Finally, return the RX descriptor and status entries
+ * back to the MAC engine, and loop again, checking for
+ * more descriptors to process.
+ */
+ writel(1, ®s->rxdqenq);
+ writel(1, ®s->rxstsqenq);
+ } else {
+ ret = 0;
+ }
+
+ pr_debug("-ep93xx_eth_rcv_packet %d\n", ret);
+
+ return ret;
+}
+
+/**
+ * Send a block of data via ethernet.
+ */
+static int ep93xx_eth_send_packet(struct eth_device *edev,
+ void *packet, int length)
+{
+ struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
+ struct mac_regs *regs = ep93xx_get_regs(edev);
+ int ret = -1;
+
+ pr_debug("+ep93xx_eth_send_packet\n");
+
+ /*
+ * Initialize the TX descriptor queue with the new packet's info.
+ * Clear the associated status queue entry. Enqueue the packet
+ * to the MAC for transmission.
+ */
+
+ /* set buffer address */
+ priv->tx_dq.current->word1 = (uint32_t)packet;
+
+ /* set buffer length and EOF bit */
+ priv->tx_dq.current->word2 = length | TX_DESC_EOF;
+
+ /* clear tx status */
+ priv->tx_sq.current->word1 = 0;
+
+ /* enqueue the TX descriptor */
+ writel(1, ®s->txdqenq);
+
+ /* wait for the frame to become processed */
+ while (!TX_STATUS_TXFP(priv->tx_sq.current))
+ ; /* noop */
+
+ if (!TX_STATUS_TXWE(priv->tx_sq.current)) {
+ pr_err("packet tx error, status %08X\n",
+ priv->tx_sq.current->word1);
+ dump_tx_descriptor_queue();
+ dump_tx_status_queue();
+
+ /* TODO: Add better error handling? */
+ goto eth_send_failed_0;
+ }
+
+ ret = 0;
+ /* Fall through */
+
+eth_send_failed_0:
+ pr_debug("-ep93xx_eth_send_packet %d\n", ret);
+
+ return ret;
+}
+
+/* -----------------------------------------------------------------------------
+ * EP93xx ethernet MII functionality.
+ */
+
+/**
+ * Maximum MII address we support
+ */
+#define MII_ADDRESS_MAX (31)
+
+/**
+ * Maximum MII register address we support
+ */
+#define MII_REGISTER_MAX (31)
+
+/**
+ * Read a 16-bit value from an MII register.
+ */
+static int ep93xx_phy_read(struct miiphy_device *mdev, uint8_t phy_addr,
+ uint8_t phy_reg, uint16_t *value)
+{
+ struct mac_regs *regs = ep93xx_get_regs(mdev->edev);
+ int ret = -1;
+ uint32_t self_ctl;
+
+ pr_debug("+ep93xx_phy_read\n");
+
+ /*
+ * Save the current SelfCTL register value. Set MAC to suppress
+ * preamble bits. Wait for any previous MII command to complete
+ * before issuing the new command.
+ */
+ self_ctl = readl(®s->selfctl);
+#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) /* TODO */
+ writel(self_ctl & ~(1 << 8), ®s->selfctl);
+#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
+
+ while (readl(®s->miists) & MIISTS_BUSY)
+ ; /* noop */
+
+ /*
+ * Issue the MII 'read' command. Wait for the command to complete.
+ * Read the MII data value.
+ */
+ writel(MIICMD_OPCODE_READ | ((uint32_t)phy_addr << 5) |
+ (uint32_t)phy_reg, ®s->miicmd);
+ while (readl(®s->miists) & MIISTS_BUSY)
+ ; /* noop */
+
+ *value = (unsigned short)readl(®s->miidata);
+
+ /* Restore the saved SelfCTL value and return. */
+ writel(self_ctl, ®s->selfctl);
+
+ ret = 0;
+
+ pr_debug("-ep93xx_phy_read\n");
+
+ return ret;
+}
+
+/**
+ * Write a 16-bit value to an MII register.
+ */
+static int ep93xx_phy_write(struct miiphy_device *mdev, uint8_t phy_addr,
+ uint8_t phy_reg, uint16_t value)
+{
+ struct mac_regs *regs = ep93xx_get_regs(mdev->edev);
+ int ret = -1;
+ uint32_t self_ctl;
+
+ pr_debug("+ep93xx_phy_write\n");
+
+ /*
+ * Save the current SelfCTL register value. Set MAC to suppress
+ * preamble bits. Wait for any previous MII command to complete
+ * before issuing the new command.
+ */
+ self_ctl = readl(®s->selfctl);
+#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) /* TODO */
+ writel(self_ctl & ~(1 << 8), ®s->selfctl);
+#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
+
+ while (readl(®s->miists) & MIISTS_BUSY)
+ ; /* noop */
+
+ /* Issue the MII 'write' command. Wait for the command to complete. */
+ writel((uint32_t)value, ®s->miidata);
+ writel(MIICMD_OPCODE_WRITE | ((uint32_t)phy_addr << 5) | phy_reg,
+ ®s->miicmd);
+ while (readl(®s->miists) & MIISTS_BUSY)
+ ; /* noop */
+
+ /* Restore the saved SelfCTL value and return. */
+ writel(self_ctl, ®s->selfctl);
+
+ ret = 0;
+
+ pr_debug("-ep93xx_phy_write\n");
+
+ return ret;
+}
+
+static struct driver_d ep93xx_eth_driver = {
+ .name = "ep93xx_eth",
+ .probe = ep93xx_eth_probe,
+};
+
+static int ep93xx_eth_init(void)
+{
+ register_driver(&ep93xx_eth_driver);
+ return 0;
+}
+
+device_initcall(ep93xx_eth_init);
diff --git a/drivers/net/ep93xx.h b/drivers/net/ep93xx.h
new file mode 100644
index 0000000..ae45c54
--- /dev/null
+++ b/drivers/net/ep93xx.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ETH_H
+#define _ETH_H
+
+#include <net.h>
+
+/**
+ * #define this to dump device status and queue info during initialization and
+ * following errors.
+ */
+#undef EP93XX_MAC_DEBUG
+
+/**
+ * Number of descriptor and status entries in our RX queues.
+ * It must be power of 2 !
+ */
+#define NUMRXDESC PKTBUFSRX
+
+/**
+ * Number of descriptor and status entries in our TX queues.
+ */
+#define NUMTXDESC 1
+
+/**
+ * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT)
+ */
+#define TXSTARTMAX 944
+
+/**
+ * Receive descriptor queue entry
+ */
+struct rx_descriptor {
+ uint32_t word1;
+ uint32_t word2;
+} __attribute__((packed));
+
+/**
+ * Receive status queue entry
+ */
+struct rx_status {
+ uint32_t word1;
+ uint32_t word2;
+} __attribute__((packed));
+
+#define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01)
+#define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01)
+#define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF)
+
+
+/**
+ * Transmit descriptor queue entry
+ */
+struct tx_descriptor {
+ uint32_t word1;
+ uint32_t word2;
+} __attribute__((packed));
+
+#define TX_DESC_EOF (1 << 31)
+
+/**
+ * Transmit status queue entry
+ */
+struct tx_status {
+ uint32_t word1;
+} __attribute__((packed));
+
+#define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01)
+#define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01)
+
+/**
+ * Transmit descriptor queue
+ */
+struct tx_descriptor_queue {
+ struct tx_descriptor *base;
+ struct tx_descriptor *current;
+ struct tx_descriptor *end;
+};
+
+/**
+ * Transmit status queue
+ */
+struct tx_status_queue {
+ struct tx_status *base;
+ volatile struct tx_status *current;
+ struct tx_status *end;
+};
+
+/**
+ * Receive descriptor queue
+ */
+struct rx_descriptor_queue {
+ struct rx_descriptor *base;
+ struct rx_descriptor *current;
+ struct rx_descriptor *end;
+};
+
+/**
+ * Receive status queue
+ */
+struct rx_status_queue {
+ struct rx_status *base;
+ volatile struct rx_status *current;
+ struct rx_status *end;
+};
+
+/**
+ * EP93xx MAC private data structure
+ */
+struct ep93xx_eth_priv {
+ struct mac_regs *regs;
+
+ struct rx_descriptor_queue rx_dq;
+ struct rx_status_queue rx_sq;
+ void *rx_buffer[NUMRXDESC];
+
+ struct tx_descriptor_queue tx_dq;
+ struct tx_status_queue tx_sq;
+
+ struct miiphy_device miiphy;
+};
+
+#endif
diff --git a/include/common.h b/include/common.h
index 0c49d95..2b40954 100644
--- a/include/common.h
+++ b/include/common.h
@@ -31,6 +31,7 @@
#include <linux/types.h>
#include <linux/string.h>
#include <linux/kernel.h>
+#include <linux/stddef.h>
#include <asm/common.h>
#define pr_info(fmt, arg...) printf(fmt, ##arg)
--
1.6.3.1
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^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH 2/5] Add EP93xx ethernet driver
@ 2010-01-09 23:28 Matthias Kaehlcke
2010-01-11 10:12 ` Sascha Hauer
0 siblings, 1 reply; 3+ messages in thread
From: Matthias Kaehlcke @ 2010-01-09 23:28 UTC (permalink / raw)
To: barebox
Added ethernet driver for EP93xx SoCs
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
---
drivers/net/Kconfig | 5 +
drivers/net/Makefile | 1 +
drivers/net/ep93xx.c | 686 ++++++++++++++++++++++++++++++++++++++++++++++++++
drivers/net/ep93xx.h | 155 ++++++++++++
include/common.h | 1 +
5 files changed, 848 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/ep93xx.c
create mode 100644 drivers/net/ep93xx.h
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index ed7656e..0955562 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -64,6 +64,11 @@ config DRIVER_NET_FEC_IMX
depends on ARCH_HAS_FEC_IMX
select MIIPHY
+config DRIVER_NET_EP93XX
+ bool "EP93xx Ethernet driver"
+ depends on ARCH_EP93XX
+ select MIIPHY
+
config DRIVER_NET_MACB
bool "macb Ethernet driver"
depends on ARCH_AT91
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 6751920..1b6f104 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_DRIVER_NET_NETX) += netx_eth.o
obj-$(CONFIG_DRIVER_NET_AT91_ETHER) += at91_ether.o
obj-$(CONFIG_DRIVER_NET_MPC5200) += fec_mpc5200.o
obj-$(CONFIG_DRIVER_NET_FEC_IMX) += fec_imx.o
+obj-$(CONFIG_DRIVER_NET_EP93XX) += ep93xx.o
obj-$(CONFIG_DRIVER_NET_MACB) += macb.o
obj-$(CONFIG_DRIVER_NET_TAP) += tap.o
obj-$(CONFIG_MIIPHY) += miiphy.o
diff --git a/drivers/net/ep93xx.c b/drivers/net/ep93xx.c
new file mode 100644
index 0000000..63a0d1b
--- /dev/null
+++ b/drivers/net/ep93xx.c
@@ -0,0 +1,686 @@
+/*
+ * Cirrus Logic EP93xx ethernet MAC / MII driver.
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver,
+ * which is
+ *
+ * (C) Copyright 2002 2003
+ * Adam Bezanson, Network Audio Technologies, Inc.
+ * <bezanson@netaudiotech.com>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <linux/types.h>
+#include <mach/ep93xx-regs.h>
+#include "ep93xx.h"
+
+static int ep93xx_eth_send_packet(struct eth_device *edev,
+ void *packet, int length);
+static int ep93xx_eth_rcv_packet(struct eth_device *edev);
+
+static int ep93xx_phy_read(struct miiphy_device *mdev, uint8_t phy_addr,
+ uint8_t phy_reg, uint16_t *value);
+static int ep93xx_phy_write(struct miiphy_device *mdev, uint8_t phy_addr,
+ uint8_t phy_reg, uint16_t value);
+
+static inline struct ep93xx_eth_priv *ep93xx_get_priv(struct eth_device *edev)
+{
+ return (struct ep93xx_eth_priv *)edev->priv;
+}
+
+static inline struct mac_regs *ep93xx_get_regs(struct eth_device *edev)
+{
+ struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
+
+ return priv->regs;
+}
+
+#if defined(EP93XX_MAC_DEBUG)
+/**
+ * Dump ep93xx_mac values to the terminal.
+ */
+inline void dump_dev(struct eth_device *edev)
+{
+ struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
+ int i;
+
+ printf("\ndump_dev()\n");
+ printf(" rx_dq.base %08X\n", priv->rx_dq.base);
+ printf(" rx_dq.current %08X\n", priv->rx_dq.current);
+ printf(" rx_dq.end %08X\n", priv->rx_dq.end);
+ printf(" rx_sq.base %08X\n", priv->rx_sq.base);
+ printf(" rx_sq.current %08X\n", priv->rx_sq.current);
+ printf(" rx_sq.end %08X\n", priv->rx_sq.end);
+
+ for (i = 0; i < NUMRXDESC; i++)
+ printf(" rx_buffer[%2.d] %08X\n", i, NetRxPackets[i]);
+
+ printf(" tx_dq.base %08X\n", priv->tx_dq.base);
+ printf(" tx_dq.current %08X\n", priv->tx_dq.current);
+ printf(" tx_dq.end %08X\n", priv->tx_dq.end);
+ printf(" tx_sq.base %08X\n", priv->tx_sq.base);
+ printf(" tx_sq.current %08X\n", priv->tx_sq.current);
+ printf(" tx_sq.end %08X\n", priv->tx_sq.end);
+}
+
+/**
+ * Dump all RX descriptor queue entries to the terminal.
+ */
+inline void dump_rx_descriptor_queue(struct eth_device *edev)
+{
+ struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
+ int i;
+
+ printf("\ndump_rx_descriptor_queue()\n");
+ printf(" descriptor address word1 word2\n");
+ for (i = 0; i < NUMRXDESC; i++) {
+ printf(" [ %08X ] %08X %08X\n",
+ (priv->rx_dq.base + i),
+ (priv->rx_dq.base + i)->word1,
+ (priv->rx_dq.base + i)->word2);
+ }
+}
+
+/**
+ * Dump all RX status queue entries to the terminal.
+ */
+inline void dump_rx_status_queue(void)
+{
+ struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
+ int i;
+
+ printf("\ndump_rx_status_queue()\n");
+ printf(" descriptor address word1 word2\n");
+ for (i = 0; i < NUMRXDESC; i++) {
+ printf(" [ %08X ] %08X %08X\n",
+ (priv->rx_sq.base + i),
+ (priv->rx_sq.base + i)->word1,
+ (priv->rx_sq.base + i)->word2);
+ }
+}
+
+/**
+ * Dump all TX descriptor queue entries to the terminal.
+ */
+inline void dump_tx_descriptor_queue(void)
+{
+ struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
+ int i;
+
+ printf("\ndump_tx_descriptor_queue()\n");
+ printf(" descriptor address word1 word2\n");
+ for (i = 0; i < NUMTXDESC; i++) {
+ printf(" [ %08X ] %08X %08X\n",
+ (priv->tx_dq.base + i),
+ (priv->tx_dq.base + i)->word1,
+ (priv->tx_dq.base + i)->word2);
+ }
+}
+
+/**
+ * Dump all TX status queue entries to the terminal.
+ */
+inline void dump_tx_status_queue(void)
+{
+ struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
+ int i;
+
+ printf("\ndump_tx_status_queue()\n");
+ printf(" descriptor address word1\n");
+ for (i = 0; i < NUMTXDESC; i++) {
+ printf(" [ %08X ] %08X\n",
+ (priv->rx_sq.base + i),
+ (priv->rx_sq.base + i)->word1);
+ }
+}
+#else
+#define dump_dev(x)
+#define dump_rx_descriptor_queue()
+#define dump_rx_status_queue()
+#define dump_tx_descriptor_queue()
+#define dump_tx_status_queue()
+#endif /* defined(EP93XX_MAC_DEBUG) */
+
+/**
+ * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
+ * it's cleared.
+ */
+static void ep93xx_eth_reset(struct eth_device *edev)
+{
+ struct mac_regs *regs = ep93xx_get_regs(edev);
+ uint32_t value;
+
+ pr_debug("+ep93xx_eth_reset\n");
+
+ value = readl(®s->selfctl);
+ value |= SELFCTL_RESET;
+ writel(value, ®s->selfctl);
+
+ while (readl(®s->selfctl) & SELFCTL_RESET)
+ ; /* noop */
+
+ pr_debug("-ep93xx_eth_reset\n");
+}
+
+static int ep93xx_eth_init_dev(struct eth_device *edev)
+{
+ pr_debug("+ep93xx_eth_init_dev\n");
+
+ pr_debug("-ep93xx_eth_init_dev\n");
+
+ return 0;
+}
+
+static int ep93xx_eth_open(struct eth_device *edev)
+{
+ struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
+ struct mac_regs *regs = ep93xx_get_regs(edev);
+ int i;
+
+ pr_debug("+ep93xx_eth_open\n");
+
+ ep93xx_eth_reset(edev);
+
+ /* Reset the descriptor queues' current and end address values */
+ priv->tx_dq.current = priv->tx_dq.base;
+ priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC);
+
+ priv->tx_sq.current = priv->tx_sq.base;
+ priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC);
+
+ priv->rx_dq.current = priv->rx_dq.base;
+ priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC);
+
+ priv->rx_sq.current = priv->rx_sq.base;
+ priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC);
+
+ /*
+ * Set the transmit descriptor and status queues' base address,
+ * current address, and length registers. Set the maximum frame
+ * length and threshold. Enable the transmit descriptor processor.
+ */
+ writel((uint32_t)priv->tx_dq.base, ®s->txdq.badd);
+ writel((uint32_t)priv->tx_dq.base, ®s->txdq.curadd);
+ writel(sizeof(struct tx_descriptor) * NUMTXDESC, ®s->txdq.blen);
+
+ writel((uint32_t)priv->tx_sq.base, ®s->txstsq.badd);
+ writel((uint32_t)priv->tx_sq.base, ®s->txstsq.curadd);
+ writel(sizeof(struct tx_status) * NUMTXDESC, ®s->txstsq.blen);
+
+ writel(0x00040000, ®s->txdthrshld);
+ writel(0x00040000, ®s->txststhrshld);
+
+ writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), ®s->maxfrmlen);
+ writel(BMCTL_TXEN, ®s->bmctl);
+
+ /*
+ * Set the receive descriptor and status queues' base address,
+ * current address, and length registers. Enable the receive
+ * descriptor processor.
+ */
+ writel((uint32_t)priv->rx_dq.base, ®s->rxdq.badd);
+ writel((uint32_t)priv->rx_dq.base, ®s->rxdq.curadd);
+ writel(sizeof(struct rx_descriptor) * NUMRXDESC, ®s->rxdq.blen);
+
+ writel((uint32_t)priv->rx_sq.base, ®s->rxstsq.badd);
+ writel((uint32_t)priv->rx_sq.base, ®s->rxstsq.curadd);
+ writel(sizeof(struct rx_status) * NUMRXDESC, ®s->rxstsq.blen);
+
+ writel(0x00040000, ®s->rxdthrshld);
+
+ writel(BMCTL_RXEN, ®s->bmctl);
+
+ writel(0x00040000, ®s->rxststhrshld);
+
+ /* Wait until the receive descriptor processor is active */
+ while (!(readl(®s->bmsts) & BMSTS_RXACT))
+ ; /* noop */
+
+ /*
+ * Initialize the RX descriptor queue. Clear the TX descriptor queue.
+ * Clear the RX and TX status queues. Enqueue the RX descriptor and
+ * status entries to the MAC.
+ */
+ for (i = 0; i < NUMRXDESC; i++) {
+ /* set buffer address */
+ (priv->rx_dq.base + i)->word1 = (uint32_t)NetRxPackets[i];
+
+ /* set buffer length, clear buffer index and NSOF */
+ (priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN;
+ }
+
+ memset(priv->tx_dq.base, 0,
+ (sizeof(struct tx_descriptor) * NUMTXDESC));
+ memset(priv->rx_sq.base, 0,
+ (sizeof(struct rx_status) * NUMRXDESC));
+ memset(priv->tx_sq.base, 0,
+ (sizeof(struct tx_status) * NUMTXDESC));
+
+ writel(NUMRXDESC, ®s->rxdqenq);
+ writel(NUMRXDESC, ®s->rxstsqenq);
+
+ /* Turn on RX and TX */
+ writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON |
+ RXCTL_RCRCA | RXCTL_MA, ®s->rxctl);
+ writel(TXCTL_STXON, ®s->txctl);
+
+ /* Dump data structures if we're debugging */
+ dump_dev();
+ dump_rx_descriptor_queue();
+ dump_rx_status_queue();
+ dump_tx_descriptor_queue();
+ dump_tx_status_queue();
+
+ pr_debug("-ep93xx_eth_open\n");
+
+ return 0;
+}
+
+/**
+ * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
+ * registers.
+ */
+static void ep93xx_eth_halt(struct eth_device *edev)
+{
+ struct mac_regs *regs = ep93xx_get_regs(edev);
+
+ pr_debug("+ep93xx_eth_halt\n");
+
+ writel(0x00000000, ®s->rxctl);
+ writel(0x00000000, ®s->txctl);
+
+ pr_debug("-ep93xx_eth_halt\n");
+}
+
+static int ep93xx_eth_get_ethaddr(struct eth_device *edev,
+ unsigned char *mac_addr)
+{
+ struct mac_regs *regs = ep93xx_get_regs(edev);
+ uint32_t value;
+
+ value = readl(®s->indad);
+ mac_addr[0] = value & 0xFF;
+ mac_addr[1] = (value >> 8) & 0xFF;
+ mac_addr[2] = (value >> 16) & 0xFF;
+ mac_addr[3] = (value >> 24) & 0xFF;
+
+ value = readl(®s->indad_upper);
+ mac_addr[4] = value & 0xFF;
+ mac_addr[5] = (value >> 8) & 0xFF;
+
+ return 0;
+}
+
+static int ep93xx_eth_set_ethaddr(struct eth_device *edev,
+ unsigned char *mac_addr)
+{
+ struct mac_regs *regs = ep93xx_get_regs(edev);
+
+ writel(AFP_IAPRIMARY, ®s->afp);
+
+ writel(mac_addr[0] | (mac_addr[1] << 8) |
+ (mac_addr[2] << 16) | (mac_addr[3] << 24),
+ ®s->indad);
+ writel(mac_addr[4] | (mac_addr[5] << 8), ®s->indad_upper);
+
+ return 0;
+}
+
+static int ep93xx_eth_probe(struct device_d *dev)
+{
+ struct eth_device *edev;
+ struct ep93xx_eth_priv *priv;
+ int ret = ETH_STATUS_FAILURE;
+
+ pr_debug("ep93xx_eth_probe()\n");
+
+ edev = xzalloc(sizeof(struct eth_device) +
+ sizeof(struct ep93xx_eth_priv));
+ dev->type_data = edev;
+ edev->priv = (struct ep93xx_eth_priv *)(edev + 1);
+
+ priv = edev->priv;
+ priv->regs = (struct mac_regs *)MAC_BASE;
+
+ edev->init = ep93xx_eth_init_dev;
+ edev->open = ep93xx_eth_open;
+ edev->send = ep93xx_eth_send_packet;
+ edev->recv = ep93xx_eth_rcv_packet;
+ edev->halt = ep93xx_eth_halt;
+ edev->get_ethaddr = ep93xx_eth_get_ethaddr;
+ edev->set_ethaddr = ep93xx_eth_set_ethaddr;
+
+ priv->miiphy.read = ep93xx_phy_read;
+ priv->miiphy.write = ep93xx_phy_write;
+ priv->miiphy.address = 0;
+ priv->miiphy.flags = 0;
+
+ priv->tx_dq.base = calloc(NUMTXDESC,
+ sizeof(struct tx_descriptor));
+ if (priv->tx_dq.base == NULL) {
+ pr_err("calloc() failed: tx_dq.base");
+ goto eth_probe_failed_0;
+ }
+
+ priv->tx_sq.base = calloc(NUMTXDESC,
+ sizeof(struct tx_status));
+ if (priv->tx_sq.base == NULL) {
+ pr_err("calloc() failed: tx_sq.base");
+ goto eth_probe_failed_1;
+ }
+
+ priv->rx_dq.base = calloc(NUMRXDESC,
+ sizeof(struct rx_descriptor));
+ if (priv->rx_dq.base == NULL) {
+ pr_err("calloc() failed: rx_dq.base");
+ goto eth_probe_failed_2;
+ }
+
+ priv->rx_sq.base = calloc(NUMRXDESC,
+ sizeof(struct rx_status));
+ if (priv->rx_sq.base == NULL) {
+ pr_err("calloc() failed: rx_sq.base");
+ goto eth_probe_failed_3;
+ }
+
+ miiphy_register(&priv->miiphy);
+ eth_register(edev);
+
+ ret = ETH_STATUS_SUCCESS;
+
+ goto eth_probe_done;
+
+eth_probe_failed_3:
+ free(priv->rx_dq.base);
+ /* Fall through */
+
+eth_probe_failed_2:
+ free(priv->tx_sq.base);
+ /* Fall through */
+
+eth_probe_failed_1:
+ free(priv->tx_dq.base);
+ /* Fall through */
+
+eth_probe_failed_0:
+ /* Fall through */
+
+eth_probe_done:
+ return ret;
+}
+
+/**
+ * Copy a frame of data from the MAC into the protocol layer for further
+ * processing.
+ *
+ * TODO: Enhance this to deal with as many packets as are available at
+ * the MAC at one time? */
+static int ep93xx_eth_rcv_packet(struct eth_device *edev)
+{
+ struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
+ struct mac_regs *regs = ep93xx_get_regs(edev);
+ int ret = ETH_STATUS_FAILURE;
+
+ pr_debug("+ep93xx_eth_rcv_packet\n");
+
+ if (RX_STATUS_RFP(priv->rx_sq.current)) {
+ if (RX_STATUS_RWE(priv->rx_sq.current)) {
+ /*
+ * We have a good frame. Extract the frame's length
+ * from the current rx_status_queue entry, and copy
+ * the frame's data into NetRxPackets[] of the
+ * protocol stack. We track the total number of
+ * bytes in the frame (nbytes_frame) which will be
+ * used when we pass the data off to the protocol
+ * layer via NetReceive().
+ */
+ NetReceive((uchar *)priv->rx_dq.current->word1,
+ RX_STATUS_FRAME_LEN(priv->rx_sq.current));
+ pr_debug("reporting %d bytes...\n",
+ RX_STATUS_FRAME_LEN(priv->rx_sq.current));
+
+ ret = ETH_STATUS_SUCCESS;
+
+ } else {
+ /* Do we have an erroneous packet? */
+ pr_err("packet rx error, status %08X %08X\n",
+ priv->rx_sq.current->word1,
+ priv->rx_sq.current->word2);
+ dump_rx_descriptor_queue();
+ dump_rx_status_queue();
+ }
+
+ /*
+ * Clear the associated status queue entry, and
+ * increment our current pointers to the next RX
+ * descriptor and status queue entries (making sure
+ * we wrap properly).
+ */
+ memset((void *)priv->rx_sq.current, 0,
+ sizeof(struct rx_status));
+
+ priv->rx_sq.current++;
+ if (priv->rx_sq.current >= priv->rx_sq.end)
+ priv->rx_sq.current = priv->rx_sq.base;
+
+ priv->rx_dq.current++;
+ if (priv->rx_dq.current >= priv->rx_dq.end)
+ priv->rx_dq.current = priv->rx_dq.base;
+
+ /*
+ * Finally, return the RX descriptor and status entries
+ * back to the MAC engine, and loop again, checking for
+ * more descriptors to process.
+ */
+ writel(1, ®s->rxdqenq);
+ writel(1, ®s->rxstsqenq);
+ } else {
+ ret = ETH_STATUS_SUCCESS;
+ }
+
+ pr_debug("-ep93xx_eth_rcv_packet %d\n", ret);
+
+ return ret;
+}
+
+/**
+ * Send a block of data via ethernet.
+ *
+ * TODO: Enhance this to deal with as much data as are available at one time? */
+static int ep93xx_eth_send_packet(struct eth_device *edev,
+ void *packet, int length)
+{
+ struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
+ struct mac_regs *regs = ep93xx_get_regs(edev);
+ int ret = ETH_STATUS_FAILURE;
+
+ pr_debug("+ep93xx_eth_send_packet\n");
+
+ /*
+ * Initialize the TX descriptor queue with the new packet's info.
+ * Clear the associated status queue entry. Enqueue the packet
+ * to the MAC for transmission.
+ */
+
+ /* set buffer address */
+ priv->tx_dq.current->word1 = (uint32_t)packet;
+
+ /* set buffer length and EOF bit */
+ priv->tx_dq.current->word2 = length | TX_DESC_EOF;
+
+ /* clear tx status */
+ priv->tx_sq.current->word1 = 0;
+
+ /* enqueue the TX descriptor */
+ writel(1, ®s->txdqenq);
+
+ /* wait for the frame to become processed */
+ while (!TX_STATUS_TXFP(priv->tx_sq.current))
+ ; /* noop */
+
+ if (!TX_STATUS_TXWE(priv->tx_sq.current)) {
+ pr_err("packet tx error, status %08X\n",
+ priv->tx_sq.current->word1);
+ dump_tx_descriptor_queue();
+ dump_tx_status_queue();
+
+ /* TODO: Add better error handling? */
+ goto eth_send_failed_0;
+ }
+
+ ret = ETH_STATUS_SUCCESS;
+ /* Fall through */
+
+eth_send_failed_0:
+ pr_debug("-ep93xx_eth_send_packet %d\n", ret);
+ return ret;
+}
+
+/* -----------------------------------------------------------------------------
+ * EP93xx ethernet MII functionality.
+ */
+
+/**
+ * Maximum MII address we support
+ */
+#define MII_ADDRESS_MAX (31)
+
+/**
+ * Maximum MII register address we support
+ */
+#define MII_REGISTER_MAX (31)
+
+/**
+ * Ethernet MII interface return values for public functions.
+ */
+enum mii_status {
+ MII_STATUS_SUCCESS = 0,
+ MII_STATUS_FAILURE = 1,
+};
+
+/**
+ * Read a 16-bit value from an MII register.
+ */
+static int ep93xx_phy_read(struct miiphy_device *mdev, uint8_t phy_addr,
+ uint8_t phy_reg, uint16_t *value)
+{
+ struct mac_regs *regs = ep93xx_get_regs(mdev->edev);
+ int ret = MII_STATUS_FAILURE;
+ uint32_t self_ctl;
+
+ pr_debug("+ep93xx_phy_read\n");
+
+ /*
+ * Save the current SelfCTL register value. Set MAC to suppress
+ * preamble bits. Wait for any previous MII command to complete
+ * before issuing the new command.
+ */
+ self_ctl = readl(®s->selfctl);
+#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) /* TODO */
+ writel(self_ctl & ~(1 << 8), ®s->selfctl);
+#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
+
+ while (readl(®s->miists) & MIISTS_BUSY)
+ ; /* noop */
+
+ /*
+ * Issue the MII 'read' command. Wait for the command to complete.
+ * Read the MII data value.
+ */
+ writel(MIICMD_OPCODE_READ | ((uint32_t)phy_addr << 5) |
+ (uint32_t)phy_reg, ®s->miicmd);
+ while (readl(®s->miists) & MIISTS_BUSY)
+ ; /* noop */
+
+ *value = (unsigned short)readl(®s->miidata);
+
+ /* Restore the saved SelfCTL value and return. */
+ writel(self_ctl, ®s->selfctl);
+
+ ret = MII_STATUS_SUCCESS;
+ /* Fall through */
+
+ pr_debug("-ep93xx_phy_read\n");
+ return ret;
+}
+
+/**
+ * Write a 16-bit value to an MII register.
+ */
+static int ep93xx_phy_write(struct miiphy_device *mdev, uint8_t phy_addr,
+ uint8_t phy_reg, uint16_t value)
+{
+ struct mac_regs *regs = ep93xx_get_regs(mdev->edev);
+ int ret = MII_STATUS_FAILURE;
+ uint32_t self_ctl;
+
+ pr_debug("+ep93xx_phy_write\n");
+
+ /*
+ * Save the current SelfCTL register value. Set MAC to suppress
+ * preamble bits. Wait for any previous MII command to complete
+ * before issuing the new command.
+ */
+ self_ctl = readl(®s->selfctl);
+#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) /* TODO */
+ writel(self_ctl & ~(1 << 8), ®s->selfctl);
+#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
+
+ while (readl(®s->miists) & MIISTS_BUSY)
+ ; /* noop */
+
+ /* Issue the MII 'write' command. Wait for the command to complete. */
+ writel((uint32_t)value, ®s->miidata);
+ writel(MIICMD_OPCODE_WRITE | ((uint32_t)phy_addr << 5) | phy_reg,
+ ®s->miicmd);
+ while (readl(®s->miists) & MIISTS_BUSY)
+ ; /* noop */
+
+ /* Restore the saved SelfCTL value and return. */
+ writel(self_ctl, ®s->selfctl);
+
+ ret = MII_STATUS_SUCCESS;
+ /* Fall through */
+
+ pr_debug("-ep93xx_phy_write\n");
+ return ret;
+}
+
+static struct driver_d ep93xx_eth_driver = {
+ .name = "ep93xx_eth",
+ .probe = ep93xx_eth_probe,
+};
+
+static int ep93xx_eth_init(void)
+{
+ register_driver(&ep93xx_eth_driver);
+ return 0;
+}
+
+device_initcall(ep93xx_eth_init);
diff --git a/drivers/net/ep93xx.h b/drivers/net/ep93xx.h
new file mode 100644
index 0000000..827e28a
--- /dev/null
+++ b/drivers/net/ep93xx.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ETH_H
+#define _ETH_H
+
+#include <net.h>
+
+/**
+ * #define this to dump device status and queue info during initialization and
+ * following errors.
+ */
+#undef EP93XX_MAC_DEBUG
+
+/**
+ * Number of descriptor and status entries in our RX queues.
+ * It must be power of 2 !
+ */
+#define NUMRXDESC PKTBUFSRX
+
+/**
+ * Number of descriptor and status entries in our TX queues.
+ */
+#define NUMTXDESC 1
+
+/**
+ * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT)
+ */
+#define TXSTARTMAX 944
+
+/**
+ * Ethernet MAC interface return values for public functions.
+ */
+enum eth_status {
+ ETH_STATUS_SUCCESS = 0,
+ ETH_STATUS_FAILURE = 1,
+};
+
+/**
+ * Receive descriptor queue entry
+ */
+struct rx_descriptor {
+ uint32_t word1;
+ uint32_t word2;
+} __attribute__((packed));
+
+/**
+ * Receive status queue entry
+ */
+struct rx_status {
+ uint32_t word1;
+ uint32_t word2;
+} __attribute__((packed));
+
+#define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01)
+#define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01)
+#define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF)
+
+
+/**
+ * Transmit descriptor queue entry
+ */
+struct tx_descriptor {
+ uint32_t word1;
+ uint32_t word2;
+} __attribute__((packed));
+
+#define TX_DESC_EOF (1 << 31)
+
+/**
+ * Transmit status queue entry
+ */
+struct tx_status {
+ uint32_t word1;
+} __attribute__((packed));
+
+#define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01)
+#define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01)
+
+/**
+ * Transmit descriptor queue
+ */
+struct tx_descriptor_queue {
+ struct tx_descriptor *base;
+ struct tx_descriptor *current;
+ struct tx_descriptor *end;
+};
+
+/**
+ * Transmit status queue
+ */
+struct tx_status_queue {
+ struct tx_status *base;
+ volatile struct tx_status *current;
+ struct tx_status *end;
+};
+
+/**
+ * Receive descriptor queue
+ */
+struct rx_descriptor_queue {
+ struct rx_descriptor *base;
+ struct rx_descriptor *current;
+ struct rx_descriptor *end;
+};
+
+/**
+ * Receive status queue
+ */
+struct rx_status_queue {
+ struct rx_status *base;
+ volatile struct rx_status *current;
+ struct rx_status *end;
+};
+
+/**
+ * EP93xx MAC private data structure
+ */
+struct ep93xx_eth_priv {
+ struct mac_regs *regs;
+
+ struct rx_descriptor_queue rx_dq;
+ struct rx_status_queue rx_sq;
+ void *rx_buffer[NUMRXDESC];
+
+ struct tx_descriptor_queue tx_dq;
+ struct tx_status_queue tx_sq;
+
+ struct miiphy_device miiphy;
+};
+
+#endif
diff --git a/include/common.h b/include/common.h
index 0c49d95..2b40954 100644
--- a/include/common.h
+++ b/include/common.h
@@ -31,6 +31,7 @@
#include <linux/types.h>
#include <linux/string.h>
#include <linux/kernel.h>
+#include <linux/stddef.h>
#include <asm/common.h>
#define pr_info(fmt, arg...) printf(fmt, ##arg)
--
1.6.3.1
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^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH 2/5] Add EP93xx ethernet driver
2010-01-09 23:28 Matthias Kaehlcke
@ 2010-01-11 10:12 ` Sascha Hauer
0 siblings, 0 replies; 3+ messages in thread
From: Sascha Hauer @ 2010-01-11 10:12 UTC (permalink / raw)
To: Matthias Kaehlcke; +Cc: barebox
On Sun, Jan 10, 2010 at 12:28:52AM +0100, Matthias Kaehlcke wrote:
> Added ethernet driver for EP93xx SoCs
>
> Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
> ---
> drivers/net/Kconfig | 5 +
> drivers/net/Makefile | 1 +
> drivers/net/ep93xx.c | 686 ++++++++++++++++++++++++++++++++++++++++++++++++++
> drivers/net/ep93xx.h | 155 ++++++++++++
> include/common.h | 1 +
> 5 files changed, 848 insertions(+), 0 deletions(-)
> create mode 100644 drivers/net/ep93xx.c
> create mode 100644 drivers/net/ep93xx.h
>
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index ed7656e..0955562 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -64,6 +64,11 @@ config DRIVER_NET_FEC_IMX
> depends on ARCH_HAS_FEC_IMX
> select MIIPHY
>
> +config DRIVER_NET_EP93XX
> + bool "EP93xx Ethernet driver"
> + depends on ARCH_EP93XX
> + select MIIPHY
> +
> config DRIVER_NET_MACB
> bool "macb Ethernet driver"
> depends on ARCH_AT91
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index 6751920..1b6f104 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_DRIVER_NET_NETX) += netx_eth.o
> obj-$(CONFIG_DRIVER_NET_AT91_ETHER) += at91_ether.o
> obj-$(CONFIG_DRIVER_NET_MPC5200) += fec_mpc5200.o
> obj-$(CONFIG_DRIVER_NET_FEC_IMX) += fec_imx.o
> +obj-$(CONFIG_DRIVER_NET_EP93XX) += ep93xx.o
> obj-$(CONFIG_DRIVER_NET_MACB) += macb.o
> obj-$(CONFIG_DRIVER_NET_TAP) += tap.o
> obj-$(CONFIG_MIIPHY) += miiphy.o
> diff --git a/drivers/net/ep93xx.c b/drivers/net/ep93xx.c
> new file mode 100644
> index 0000000..63a0d1b
> --- /dev/null
> +++ b/drivers/net/ep93xx.c
[snip]
> +
> +/**
> + * Copy a frame of data from the MAC into the protocol layer for further
> + * processing.
> + *
> + * TODO: Enhance this to deal with as many packets as are available at
> + * the MAC at one time? */
Probably not. I do not know what the network stack does when NetReceive
is called multiple times. Even if it does handle it I do not expect any
performance gains.
> +static int ep93xx_eth_rcv_packet(struct eth_device *edev)
> +{
> + struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
> + struct mac_regs *regs = ep93xx_get_regs(edev);
> + int ret = ETH_STATUS_FAILURE;
> +
> + pr_debug("+ep93xx_eth_rcv_packet\n");
> +
> + if (RX_STATUS_RFP(priv->rx_sq.current)) {
> + if (RX_STATUS_RWE(priv->rx_sq.current)) {
> + /*
> + * We have a good frame. Extract the frame's length
> + * from the current rx_status_queue entry, and copy
> + * the frame's data into NetRxPackets[] of the
> + * protocol stack. We track the total number of
> + * bytes in the frame (nbytes_frame) which will be
> + * used when we pass the data off to the protocol
> + * layer via NetReceive().
> + */
> + NetReceive((uchar *)priv->rx_dq.current->word1,
> + RX_STATUS_FRAME_LEN(priv->rx_sq.current));
> + pr_debug("reporting %d bytes...\n",
> + RX_STATUS_FRAME_LEN(priv->rx_sq.current));
> +
> + ret = ETH_STATUS_SUCCESS;
> +
> + } else {
> + /* Do we have an erroneous packet? */
> + pr_err("packet rx error, status %08X %08X\n",
> + priv->rx_sq.current->word1,
> + priv->rx_sq.current->word2);
> + dump_rx_descriptor_queue();
> + dump_rx_status_queue();
> + }
> +
> + /*
> + * Clear the associated status queue entry, and
> + * increment our current pointers to the next RX
> + * descriptor and status queue entries (making sure
> + * we wrap properly).
> + */
> + memset((void *)priv->rx_sq.current, 0,
> + sizeof(struct rx_status));
> +
> + priv->rx_sq.current++;
> + if (priv->rx_sq.current >= priv->rx_sq.end)
> + priv->rx_sq.current = priv->rx_sq.base;
> +
> + priv->rx_dq.current++;
> + if (priv->rx_dq.current >= priv->rx_dq.end)
> + priv->rx_dq.current = priv->rx_dq.base;
> +
> + /*
> + * Finally, return the RX descriptor and status entries
> + * back to the MAC engine, and loop again, checking for
> + * more descriptors to process.
> + */
> + writel(1, ®s->rxdqenq);
> + writel(1, ®s->rxstsqenq);
> + } else {
> + ret = ETH_STATUS_SUCCESS;
> + }
> +
> + pr_debug("-ep93xx_eth_rcv_packet %d\n", ret);
> +
> + return ret;
> +}
> +
> +/**
> + * Send a block of data via ethernet.
> + *
> + * TODO: Enhance this to deal with as much data as are available at one time? */
You are only given one packet, so you can't send more here.
> +static int ep93xx_eth_send_packet(struct eth_device *edev,
> + void *packet, int length)
> +{
> + struct ep93xx_eth_priv *priv = ep93xx_get_priv(edev);
> + struct mac_regs *regs = ep93xx_get_regs(edev);
> + int ret = ETH_STATUS_FAILURE;
> +
> + pr_debug("+ep93xx_eth_send_packet\n");
> +
> + /*
> + * Initialize the TX descriptor queue with the new packet's info.
> + * Clear the associated status queue entry. Enqueue the packet
> + * to the MAC for transmission.
> + */
> +
> + /* set buffer address */
> + priv->tx_dq.current->word1 = (uint32_t)packet;
> +
> + /* set buffer length and EOF bit */
> + priv->tx_dq.current->word2 = length | TX_DESC_EOF;
> +
> + /* clear tx status */
> + priv->tx_sq.current->word1 = 0;
> +
> + /* enqueue the TX descriptor */
> + writel(1, ®s->txdqenq);
> +
> + /* wait for the frame to become processed */
> + while (!TX_STATUS_TXFP(priv->tx_sq.current))
> + ; /* noop */
> +
> + if (!TX_STATUS_TXWE(priv->tx_sq.current)) {
> + pr_err("packet tx error, status %08X\n",
> + priv->tx_sq.current->word1);
> + dump_tx_descriptor_queue();
> + dump_tx_status_queue();
> +
> + /* TODO: Add better error handling? */
> + goto eth_send_failed_0;
> + }
> +
> + ret = ETH_STATUS_SUCCESS;
> + /* Fall through */
> +
> +eth_send_failed_0:
> + pr_debug("-ep93xx_eth_send_packet %d\n", ret);
> + return ret;
> +}
> +
> +/* -----------------------------------------------------------------------------
> + * EP93xx ethernet MII functionality.
> + */
> +
> +/**
> + * Maximum MII address we support
> + */
> +#define MII_ADDRESS_MAX (31)
> +
> +/**
> + * Maximum MII register address we support
> + */
> +#define MII_REGISTER_MAX (31)
> +
> +/**
> + * Ethernet MII interface return values for public functions.
> + */
> +enum mii_status {
> + MII_STATUS_SUCCESS = 0,
> + MII_STATUS_FAILURE = 1,
> +};
> +
> +/**
> + * Read a 16-bit value from an MII register.
> + */
> +static int ep93xx_phy_read(struct miiphy_device *mdev, uint8_t phy_addr,
> + uint8_t phy_reg, uint16_t *value)
> +{
> + struct mac_regs *regs = ep93xx_get_regs(mdev->edev);
> + int ret = MII_STATUS_FAILURE;
> + uint32_t self_ctl;
> +
> + pr_debug("+ep93xx_phy_read\n");
> +
> + /*
> + * Save the current SelfCTL register value. Set MAC to suppress
> + * preamble bits. Wait for any previous MII command to complete
> + * before issuing the new command.
> + */
> + self_ctl = readl(®s->selfctl);
> +#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) /* TODO */
> + writel(self_ctl & ~(1 << 8), ®s->selfctl);
> +#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
> +
> + while (readl(®s->miists) & MIISTS_BUSY)
> + ; /* noop */
> +
> + /*
> + * Issue the MII 'read' command. Wait for the command to complete.
> + * Read the MII data value.
> + */
> + writel(MIICMD_OPCODE_READ | ((uint32_t)phy_addr << 5) |
> + (uint32_t)phy_reg, ®s->miicmd);
> + while (readl(®s->miists) & MIISTS_BUSY)
> + ; /* noop */
> +
> + *value = (unsigned short)readl(®s->miidata);
> +
> + /* Restore the saved SelfCTL value and return. */
> + writel(self_ctl, ®s->selfctl);
> +
> + ret = MII_STATUS_SUCCESS;
> + /* Fall through */
> +
> + pr_debug("-ep93xx_phy_read\n");
> + return ret;
You can return 0 unconditionally here, the function never returns an
error. Please remove the MII_STATUS_* and ETH_STATUS_* macros. If we
ever decide add timeouts to the while loops -ETIMEDOUT would be the
correct return value, not 1.
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 3+ messages in thread
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2010-01-12 19:30 [PATCH 2/5] Add EP93xx ethernet driver Matthias Kaehlcke
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2010-01-09 23:28 Matthias Kaehlcke
2010-01-11 10:12 ` Sascha Hauer
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