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Date: Wed, 19 Jan 2011 08:05:29 +0100
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Message-ID: <20110119070529.GY14798@game.jcrosoft.org>
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Subject: Re: [PATCH] at91sam9g45: fix ARCH_TEXT_BASE
To: Peter Korsgaard <jacmet@sunsite.dk>
Cc: barebox@lists.infradead.org

On 21:36 Tue 18 Jan     , Peter Korsgaard wrote:
> >>>>> "Jean-Christophe" == Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> writes:
> 
>  Jean-Christophe> it's 0x73f00000 not 0x23f00000 as the other at91
>  Jean-Christophe> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
>  Jean-Christophe> ---
>  Jean-Christophe>  arch/arm/mach-at91/Kconfig |    1 +
>  Jean-Christophe>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
>  Jean-Christophe> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
>  Jean-Christophe> index 4d35ebe..efaa256 100644
>  Jean-Christophe> --- a/arch/arm/mach-at91/Kconfig
>  Jean-Christophe> +++ b/arch/arm/mach-at91/Kconfig
>  Jean-Christophe> @@ -2,6 +2,7 @@ if ARCH_AT91
>  
>  Jean-Christophe>  config ARCH_TEXT_BASE
>  Jean-Christophe>  	hex
>  Jean-Christophe> +	default 0x73f00000 if ARCH_AT91SAM9G45
>  Jean-Christophe>  	default 0x23f00000
> 
> It can be 0x2xxxxxxx if the 2nd DDR controller is used.
> 
> I don't know the code, but how does this this work on boards with less
> than 64MB RAM?
the soc start on 0x7xxxxxxx so we use it
if your board is less DRR you have to adjust it

today we do not detect the ddr size but we may later

Best Regards,
J.

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