From: Roman Fietze <roman.fietze@telemotive.de>
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: barebox@lists.infradead.org
Subject: [PATCH] freescale-mx35-3-stack: support 256 MiB RAM
Date: Wed, 27 Apr 2011 10:38:46 +0200 [thread overview]
Message-ID: <201104271038.46439.roman.fietze@telemotive.de> (raw)
In-Reply-To: <20110426215630.GL14770@pengutronix.de>
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Hallo,
On Tuesday, 26.April.2011 23:56:30 Sascha Hauer wrote:
> There are at least two bugs in your flash header, see below.
I think I will need reading glasses pretty soon. :(
Here are the updated patches. And they seem to work on our two boards.
As far as I know there are different variants of the Freescale i.MX35
3-stack out there. It would be great if somebody using one of those
boards could double check the patches.
Here's the updated patch:
From ee2ed245651363f6cd6f1d5ad00e7a88c206b5b4 Mon Sep 17 00:00:00 2001
From: Roman Fietze <roman.fietze@telemotive.de>
Date: Wed, 27 Apr 2011 07:13:12 +0200
Subject: [PATCH] freescale-mx35-3-stack: support 256 MiB RAM
Extend DCD table and low level init routines. Add barebox SDRAM
device.
Signed-off-by: Roman Fietze <roman.fietze@telemotive.de>
---
arch/arm/boards/freescale-mx35-3-stack/3stack.c | 25 +++++++++++++++----
| 26 +++++++++++++++++++-
.../boards/freescale-mx35-3-stack/lowlevel_init.S | 17 +++++++-----
3 files changed, 55 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
index 7b61a24..2a12aaa 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
@@ -71,17 +71,30 @@ static struct fec_platform_data fec_info = {
.phy_addr = 0x1F,
};
-static struct memory_platform_data sdram_pdata = {
+static struct memory_platform_data sdram0_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
-static struct device_d sdram_dev = {
+static struct device_d sdram0_dev = {
.id = -1,
.name = "mem",
.map_base = IMX_SDRAM_CS0,
.size = 128 * 1024 * 1024,
- .platform_data = &sdram_pdata,
+ .platform_data = &sdram0_pdata,
+};
+
+static struct memory_platform_data sdram1_pdata = {
+ .name = "ram1",
+ .flags = DEVFS_RDWR,
+};
+
+static struct device_d sdram1_dev = {
+ .id = -1,
+ .name = "mem",
+ .map_base = IMX_SDRAM_CS1,
+ .size = 128 * 1024 * 1024,
+ .platform_data = &sdram1_pdata,
};
struct imx_nand_platform_data nand_info = {
@@ -209,10 +222,12 @@ static int f3s_devices_init(void)
imx35_add_mmc0(NULL);
- register_device(&sdram_dev);
+ register_device(&sdram0_dev);
+ register_device(&sdram1_dev);
imx35_add_fb(&ipu_fb_data);
- armlinux_add_dram(&sdram_dev);
+ armlinux_add_dram(&sdram0_dev);
+ armlinux_add_dram(&sdram1_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_MX35_3DS);
--git a/arch/arm/boards/freescale-mx35-3-stack/flash_header.c b/arch/arm/boards/freescale-mx35-3-stack/flash_header.c
index 4bee797..92f2142 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/flash_header.c
+++ b/arch/arm/boards/freescale-mx35-3-stack/flash_header.c
@@ -13,23 +13,47 @@ struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
{ .ptr_type = 4, .addr = 0xb8002050, .val = 0x0000d843, },
{ .ptr_type = 4, .addr = 0xB8002054, .val = 0x22252521, },
{ .ptr_type = 4, .addr = 0xB8002058, .val = 0x22220a00, },
+
{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000304, },
{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x0000030C, },
+
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc3f, },
+ { .ptr_type = 4, .addr = 0xB800100C, .val = 0x007ffc3f, },
+
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0x92220000, },
+ { .ptr_type = 4, .addr = 0xB8001008, .val = 0x92220000, },
+
{ .ptr_type = 4, .addr = 0x80000400, .val = 0x12345678, },
+ { .ptr_type = 4, .addr = 0x90000400, .val = 0x12345678, },
+
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0xA2220000, },
+ { .ptr_type = 4, .addr = 0xB8001008, .val = 0xA2220000, },
+
{ .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, },
+ { .ptr_type = 4, .addr = 0x90000000, .val = 0x87654321, },
+
{ .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, },
+ { .ptr_type = 4, .addr = 0x90000000, .val = 0x87654321, },
+
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0xB2220000, },
+ { .ptr_type = 4, .addr = 0xB8001008, .val = 0xB2220000, },
+
{ .ptr_type = 1, .addr = 0x80000233, .val = 0xda, },
+ { .ptr_type = 1, .addr = 0x90000233, .val = 0xda, },
+
{ .ptr_type = 1, .addr = 0x82000780, .val = 0xda, },
+ { .ptr_type = 1, .addr = 0x92000780, .val = 0xda, },
+
{ .ptr_type = 1, .addr = 0x82000400, .val = 0xda, },
+ { .ptr_type = 1, .addr = 0x92000400, .val = 0xda, },
+
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0x82226080, },
+ { .ptr_type = 4, .addr = 0xB8001008, .val = 0x82226080, },
+
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc3f, },
{ .ptr_type = 4, .addr = 0xB800100C, .val = 0x007ffc3f, },
+
{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000304, },
- { .ptr_type = 4, .addr = 0xB8001008, .val = 0x00002000, },
};
diff --git a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
index 1680579..413e04a 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
@@ -28,8 +28,8 @@
#include "board-mx35_3stack.h"
#define CSD0_BASE_ADDR 0x80000000
-#define ESDCTL_BASE_ADDR 0xB8001000
#define CSD1_BASE_ADDR 0x90000000
+#define ESDCTL_BASE_ADDR 0xB8001000
#define writel(val, reg) \
ldr r0, =reg; \
@@ -122,9 +122,9 @@ board_init_lowlevel:
str r1, [r0, #CCM_CGR1]
/* Skip SDRAM initialization if we run from RAM */
- cmp pc, #0x80000000
+ cmp pc, #CSD0_BASE_ADDR
bls 1f
- cmp pc, #0x90000000
+ cmp pc, #CSD1_BASE_ADDR
bhi 1f
mov pc, r10
@@ -138,14 +138,17 @@ board_init_lowlevel:
/* ip(r12) has used to save lr register in upper calling */
mov fp, lr
+ /* setup bank 0 */
mov r5, #0x00
mov r2, #0x00
mov r1, #CSD0_BASE_ADDR
bl setup_sdram_bank
- cmp r3, #0x0
- orreq r5, r5, #1
- eorne r2, r2, #0x1
- blne setup_sdram_bank
+
+ /* setup bank 1 */
+ mov r5, #0x00
+ mov r2, #0x00
+ mov r1, #CSD1_BASE_ADDR
+ bl setup_sdram_bank
mov lr, fp
--
1.7.4.2
Roman
--
Roman Fietze Telemotive AG Büro Mühlhausen
Breitwiesen 73347 Mühlhausen
Tel.: +49(0)7335/18493-45 http://www.telemotive.de
Amtsgericht Ulm HRB 541321
Vorstand:
Peter Kersten, Markus Fischer, Franz Diller, Markus Stolz
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next prev parent reply other threads:[~2011-04-27 8:38 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-26 12:30 Freescale i.MX35 using CSD1 and 256 MiB DDR2 Roman Fietze
2011-04-26 21:56 ` Sascha Hauer
2011-04-27 8:38 ` Roman Fietze [this message]
2011-04-27 9:14 ` [PATCH] freescale-mx35-3-stack: support 256 MiB RAM Marc Kleine-Budde
2011-04-27 10:32 ` Roman Fietze
2011-04-27 10:34 ` Marc Kleine-Budde
2012-01-20 15:04 ` Thomas Mayer
2012-01-23 9:26 ` Sascha Hauer
2012-01-23 14:04 ` Thomas Mayer
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