[PATCH] ARM: mx53loco: Fix DD3 initialization

[PATCH] ARM: mx53loco: Fix DD3 initialization

[Fabio Estevam]

Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011:

-change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz)

-change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from "0x092080b0". 

This changes write recovery from 8 clocks to 6 clocks(in line with ESDCFG1[tWR])

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 arch/arm/boards/freescale-mx53-loco/flash_header.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boards/freescale-mx53-loco/flash_header.c b/arch/arm/boards/freescale-mx53-loco/flash_header.c
index d6ff898..490e223 100644
--- a/arch/arm/boards/freescale-mx53-loco/flash_header.c
+++ b/arch/arm/boards/freescale-mx53-loco/flash_header.c
@@ -63,14 +63,14 @@ struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
 	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), },
 	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008033), },
 	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028031), },
-	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x092080b0), },
+	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x052080b0), },
 	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008040), },
 	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803a), },
 	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803b), },
 	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028039), },
-	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x09208138), },
+	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x05208138), },
 	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008048), },
-	{ .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00001800), },
+	{ .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), },
 	{ .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), },
 	{ .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00022227), },
 	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
-- 
1.7.1


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Re: [PATCH] ARM: mx53loco: Fix DD3 initialization

[Sascha Hauer]

Hi Fabio,

Welcome to barebox ;)

On Tue, Aug 23, 2011 at 09:11:04PM -0300, Fabio Estevam wrote:
> Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011:
> 
> -change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz)
> 
> -change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from "0x092080b0". 
> 
> This changes write recovery from 8 clocks to 6 clocks(in line with ESDCFG1[tWR])
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Applied to master.

Sascha

> ---
>  arch/arm/boards/freescale-mx53-loco/flash_header.c |    6 +++---
>  1 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boards/freescale-mx53-loco/flash_header.c b/arch/arm/boards/freescale-mx53-loco/flash_header.c
> index d6ff898..490e223 100644
> --- a/arch/arm/boards/freescale-mx53-loco/flash_header.c
> +++ b/arch/arm/boards/freescale-mx53-loco/flash_header.c
> @@ -63,14 +63,14 @@ struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
>  	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), },
>  	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008033), },
>  	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028031), },
> -	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x092080b0), },
> +	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x052080b0), },
>  	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008040), },
>  	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803a), },
>  	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803b), },
>  	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028039), },
> -	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x09208138), },
> +	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x05208138), },
>  	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008048), },
> -	{ .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00001800), },
> +	{ .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), },
>  	{ .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), },
>  	{ .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00022227), },
>  	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
> -- 
> 1.7.1
> 
> 

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