* Thumb-2 support
@ 2011-12-17 14:52 Sascha Hauer
2011-12-17 14:52 ` [PATCH 1/9] ARM i.MX5: prepare to add a imx51_lowlevel_init Sascha Hauer
` (8 more replies)
0 siblings, 9 replies; 20+ messages in thread
From: Sascha Hauer @ 2011-12-17 14:52 UTC (permalink / raw)
To: barebox
The following series adds Thumb-2 support to barebox. To do this
we have to update the Arm assembly functions which are from the
kernel anyway, so we just update them to newer versions. Some
boards may need additional updates for their lowlevel assembly
code. At least the babbage lowlevel code did not work in Thumb-2,
so this series contains an update for this board. If Omap works
in Thumb-2 remains to be tested.
This series was tested on a babbage board and reduces the binary
size by about 25%.
Sascha
Sascha Hauer (9):
ARM i.MX5: prepare to add a imx51_lowlevel_init
ARM i.MX51: implement a imx51_lowlevel_init
ARM i.MX51 babbage: use generic lowlevel init function
ARM eukrea i.MX51: use generic lowlevel init
ARM: update string functions from Linux Kernel
ARM cache-armv7: use thumb-2 instructions where necessary
ARM: move exception vectors away from start of binary
ARM: get runtime offset of board_init_lowlevel_return by using separate section
ARM: Allow to compile in thumb-2 mode
arch/arm/Kconfig | 12 +
arch/arm/Makefile | 11 +-
arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c | 3 +-
arch/arm/boards/eukrea_cpuimx35/flash_header.c | 3 +-
arch/arm/boards/eukrea_cpuimx51/Makefile | 1 -
arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c | 3 +
arch/arm/boards/eukrea_cpuimx51/flash_header.c | 3 +-
arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S | 216 --------------------
arch/arm/boards/freescale-mx25-3-stack/3stack.c | 3 +-
.../boards/freescale-mx35-3-stack/flash_header.c | 3 +-
arch/arm/boards/freescale-mx51-pdk/Makefile | 1 -
arch/arm/boards/freescale-mx51-pdk/board.c | 3 +
arch/arm/boards/freescale-mx51-pdk/flash_header.c | 3 +-
arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S | 216 --------------------
arch/arm/boards/freescale-mx53-loco/board.c | 2 +-
arch/arm/boards/freescale-mx53-loco/flash_header.c | 3 +-
arch/arm/boards/freescale-mx53-smd/board.c | 2 +-
arch/arm/boards/freescale-mx53-smd/flash_header.c | 3 +-
arch/arm/cpu/cache-armv7.S | 8 +-
arch/arm/cpu/cpu.c | 27 +++
arch/arm/cpu/exceptions.S | 1 +
arch/arm/cpu/mmu.c | 4 +-
arch/arm/cpu/start.c | 44 +++--
arch/arm/include/asm/barebox-arm-head.h | 29 +++
arch/arm/include/asm/barebox-arm.h | 3 +
arch/arm/include/asm/unified.h | 8 +-
arch/arm/lib/armlinux.c | 16 ++-
arch/arm/lib/barebox.lds.S | 7 +-
arch/arm/lib/copy_template.S | 24 ++-
arch/arm/lib/findbit.S | 84 +++++---
arch/arm/lib/io-writesw-armv4.S | 11 +-
arch/arm/lib/memcpy.S | 7 +-
arch/arm/mach-imx/Kconfig | 2 -
arch/arm/mach-imx/Makefile | 4 +-
arch/arm/mach-imx/imx51.c | 105 ++++++++++
arch/arm/mach-imx/imx53.c | 61 +-----
arch/arm/mach-imx/include/mach/imx5.h | 9 +
arch/arm/mach-imx/include/mach/imx53.h | 6 -
commands/go.c | 6 +-
common/misc.c | 3 +
include/common.h | 6 +
41 files changed, 387 insertions(+), 579 deletions(-)
delete mode 100644 arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
delete mode 100644 arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S
create mode 100644 arch/arm/include/asm/barebox-arm-head.h
create mode 100644 arch/arm/mach-imx/include/mach/imx5.h
delete mode 100644 arch/arm/mach-imx/include/mach/imx53.h
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 1/9] ARM i.MX5: prepare to add a imx51_lowlevel_init
2011-12-17 14:52 Thumb-2 support Sascha Hauer
@ 2011-12-17 14:52 ` Sascha Hauer
2011-12-18 14:03 ` Eric Bénard
2011-12-19 10:18 ` Sascha Hauer
2011-12-17 14:52 ` [PATCH 2/9] ARM i.MX51: implement " Sascha Hauer
` (7 subsequent siblings)
8 siblings, 2 replies; 20+ messages in thread
From: Sascha Hauer @ 2011-12-17 14:52 UTC (permalink / raw)
To: barebox
- move code which can be shared between i.MX53 and i.MX51
to a common file
- rename mx53_init_lowlevel to imx53_init_lowlevel
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/freescale-mx53-loco/board.c | 2 +-
arch/arm/boards/freescale-mx53-smd/board.c | 2 +-
arch/arm/mach-imx/Makefile | 4 +-
arch/arm/mach-imx/imx53.c | 61 +++-----------------------
arch/arm/mach-imx/include/mach/imx5.h | 8 ++++
arch/arm/mach-imx/include/mach/imx53.h | 6 ---
6 files changed, 19 insertions(+), 64 deletions(-)
create mode 100644 arch/arm/mach-imx/include/mach/imx5.h
delete mode 100644 arch/arm/mach-imx/include/mach/imx53.h
diff --git a/arch/arm/boards/freescale-mx53-loco/board.c b/arch/arm/boards/freescale-mx53-loco/board.c
index aec2254..8d1cbf5 100644
--- a/arch/arm/boards/freescale-mx53-loco/board.c
+++ b/arch/arm/boards/freescale-mx53-loco/board.c
@@ -34,7 +34,7 @@
#include <mach/gpio.h>
#include <mach/imx-nand.h>
#include <mach/iim.h>
-#include <mach/imx53.h>
+#include <mach/imx5.h>
#include <asm/armlinux.h>
#include <io.h>
diff --git a/arch/arm/boards/freescale-mx53-smd/board.c b/arch/arm/boards/freescale-mx53-smd/board.c
index 325458e..d14c1f2 100644
--- a/arch/arm/boards/freescale-mx53-smd/board.c
+++ b/arch/arm/boards/freescale-mx53-smd/board.c
@@ -34,7 +34,7 @@
#include <mach/gpio.h>
#include <mach/imx-nand.h>
#include <mach/iim.h>
-#include <mach/imx53.h>
+#include <mach/imx5.h>
#include <asm/armlinux.h>
#include <io.h>
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 0b3b781..a9aa9e2 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -5,8 +5,8 @@ obj-$(CONFIG_ARCH_IMX21) += speed-imx21.o imx21.o iomux-v1.o
obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o
obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o
obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o
-obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o
-obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o
+obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o imx5.o
+obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o imx5.o
obj-$(CONFIG_IMX_CLKO) += clko.o
obj-$(CONFIG_IMX_IIM) += iim.o
obj-$(CONFIG_NAND_IMX) += nand.o
diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c
index 64bec86..2fb18e7 100644
--- a/arch/arm/mach-imx/imx53.c
+++ b/arch/arm/mach-imx/imx53.c
@@ -19,6 +19,7 @@
#include <common.h>
#include <io.h>
#include <sizes.h>
+#include <mach/imx5.h>
#include <mach/imx53-regs.h>
#include <mach/clock-imx51_53.h>
@@ -45,63 +46,17 @@ static int imx53_init(void)
}
coredevice_initcall(imx53_init);
-static void setup_pll(void __iomem *base, int freq, u32 op, u32 mfd, u32 mfn)
-{
- u32 r;
-
- /*
- * If freq < 300MHz, we need to set dpdck0_2_en to 0
- */
- r = 0x00000232;
- if (freq >= 300)
- r |= 0x1000;
-
- writel(r, base + MX5_PLL_DP_CTL);
-
- writel(0x2, base + MX5_PLL_DP_CONFIG);
-
- writel(op, base + MX5_PLL_DP_OP);
- writel(op, base + MX5_PLL_DP_HFS_OP);
-
- writel(mfd, base + MX5_PLL_DP_MFD);
- writel(mfd, base + MX5_PLL_DP_HFS_MFD);
-
- writel(mfn, base + MX5_PLL_DP_MFN);
- writel(mfn, base + MX5_PLL_DP_HFS_MFN);
+#define setup_pll_1000(base) imx5_setup_pll((base), 1000, ((10 << 4) + ((1 - 1) << 0)), (12 - 1), 5)
+#define setup_pll_400(base) imx5_setup_pll((base), 400, ((8 << 4) + ((2 - 1) << 0)), (3 - 1), 1)
+#define setup_pll_455(base) imx5_setup_pll((base), 455, ((9 << 4) + ((2 - 1) << 0)), (48 - 1), 23)
+#define setup_pll_216(base) imx5_setup_pll((base), 216, ((8 << 4) + ((2 - 1) << 0)), (1 - 1), 1)
- writel(0x00001232, base + MX5_PLL_DP_CTL);
-
- while (!(readl(base + MX5_PLL_DP_CTL) & 1));
-}
-
-#define setup_pll_1000(base) setup_pll((base), 1000, ((10 << 4) + ((1 - 1) << 0)), (12 - 1), 5)
-#define setup_pll_400(base) setup_pll((base), 400, ((8 << 4) + ((2 - 1) << 0)), (3 - 1), 1)
-#define setup_pll_455(base) setup_pll((base), 455, ((9 << 4) + ((2 - 1) << 0)), (48 - 1), 23)
-#define setup_pll_216(base) setup_pll((base), 216, ((8 << 4) + ((2 - 1) << 0)), (1 - 1), 1)
-
-int mx53_init_lowlevel(void)
+void imx53_init_lowlevel(void)
{
void __iomem *ccm = (void __iomem *)MX53_CCM_BASE_ADDR;
u32 r;
- /* ARM errata ID #468414 */
- __asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r));
- r |= (1 << 5); /* enable L1NEON bit */
- r &= ~(1 << 1); /* explicitly disable L2 cache */
- __asm__ __volatile__("mcr 15, 0, %0, c1, c0, 1" : : "r"(r));
-
- /* reconfigure L2 cache aux control reg */
- r = 0xc0 | /* tag RAM */
- 0x4 | /* data RAM */
- (1 << 24) | /* disable write allocate delay */
- (1 << 23) | /* disable write allocate combine */
- (1 << 22); /* disable write allocate */
-
- __asm__ __volatile__("mcr 15, 1, %0, c9, c0, 2" : : "r"(r));
-
- __asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r));
- r |= 1 << 1; /* enable L2 cache */
- __asm__ __volatile__("mcr 15, 0, %0, c1, c0, 1" : : "r"(r));
+ imx5_init_lowlevel();
/*
* AIPS setup - Only setup MPROTx registers.
@@ -195,6 +150,4 @@ int mx53_init_lowlevel(void)
writel(0xffffffff, ccm + MX53_CCM_CCGR7);
writel(0, ccm + MX5_CCM_CCDR);
-
- return 0;
}
diff --git a/arch/arm/mach-imx/include/mach/imx5.h b/arch/arm/mach-imx/include/mach/imx5.h
new file mode 100644
index 0000000..d034082
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx5.h
@@ -0,0 +1,8 @@
+#ifndef __MACH_MX5_H
+#define __MACH_MX5_H
+
+void imx53_init_lowlevel(void);
+void imx5_setup_pll(void __iomem *base, int freq, u32 op, u32 mfd, u32 mfn);
+void imx5_init_lowlevel(void);
+
+#endif /* __MACH_MX53_H */
diff --git a/arch/arm/mach-imx/include/mach/imx53.h b/arch/arm/mach-imx/include/mach/imx53.h
deleted file mode 100644
index b1f30d3..0000000
--- a/arch/arm/mach-imx/include/mach/imx53.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __MACH_MX53_H
-#define __MACH_MX53_H
-
-int mx53_init_lowlevel(void);
-
-#endif /* __MACH_MX53_H */
--
1.7.7.3
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 2/9] ARM i.MX51: implement a imx51_lowlevel_init
2011-12-17 14:52 Thumb-2 support Sascha Hauer
2011-12-17 14:52 ` [PATCH 1/9] ARM i.MX5: prepare to add a imx51_lowlevel_init Sascha Hauer
@ 2011-12-17 14:52 ` Sascha Hauer
2011-12-17 14:52 ` [PATCH 3/9] ARM i.MX51 babbage: use generic lowlevel init function Sascha Hauer
` (6 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2011-12-17 14:52 UTC (permalink / raw)
To: barebox
Reimplement the code from lowlevel.S in C. It is run
from SDRAM anyway, so we can safely do this initialization
in a regular barebox environment instead in Assembly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/imx51.c | 105 +++++++++++++++++++++++++++++++++
arch/arm/mach-imx/include/mach/imx5.h | 1 +
2 files changed, 106 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index 2c1efed..2431e61 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -21,6 +21,8 @@
#include <environment.h>
#include <io.h>
#include <mach/imx51-regs.h>
+#include <mach/imx5.h>
+#include <mach/clock-imx51_53.h>
#include "gpio.h"
@@ -176,3 +178,106 @@ static int imx51_boot_save_loc(void)
}
coredevice_initcall(imx51_boot_save_loc);
+
+#define setup_pll_1000(base) imx5_setup_pll((base), 1000, ((10 << 4) + ((1 - 1) << 0)), (12 - 1), 5)
+#define setup_pll_800(base) imx5_setup_pll((base), 800, ((8 << 4) + ((1 - 1) << 0)), (3 - 1), 1)
+#define setup_pll_665(base) imx5_setup_pll((base), 665, ((6 << 4) + ((1 - 1) << 0)), (96 - 1), 89)
+#define setup_pll_400(base) imx5_setup_pll((base), 400, ((8 << 4) + ((2 - 1) << 0)), (3 - 1), 1)
+#define setup_pll_455(base) imx5_setup_pll((base), 455, ((9 << 4) + ((2 - 1) << 0)), (48 - 1), 23)
+#define setup_pll_216(base) imx5_setup_pll((base), 216, ((6 << 4) + ((3 - 1) << 0)), (4 - 1), 3)
+
+void imx51_init_lowlevel(void)
+{
+ void __iomem *ccm = (void __iomem *)MX51_CCM_BASE_ADDR;
+ u32 r;
+
+ imx5_init_lowlevel();
+
+ /* disable write combine for TO 2 and lower revs */
+ if (imx_silicon_revision() < MX51_CHIP_REV_3_0) {
+ __asm__ __volatile__("mrc 15, 1, %0, c9, c0, 1":"=r"(r));
+ r |= (1 << 25);
+ __asm__ __volatile__("mcr 15, 1, %0, c9, c0, 1" : : "r"(r));
+ }
+
+ /* Gate of clocks to the peripherals first */
+ writel(0x3fffffff, ccm + MX5_CCM_CCGR0);
+ writel(0x00000000, ccm + MX5_CCM_CCGR1);
+ writel(0x00000000, ccm + MX5_CCM_CCGR2);
+ writel(0x00000000, ccm + MX5_CCM_CCGR3);
+ writel(0x00030000, ccm + MX5_CCM_CCGR4);
+ writel(0x00fff030, ccm + MX5_CCM_CCGR5);
+ writel(0x00000300, ccm + MX5_CCM_CCGR6);
+
+ /* Disable IPU and HSC dividers */
+ writel(0x00060000, ccm + MX5_CCM_CCDR);
+
+ /* Make sure to switch the DDR away from PLL 1 */
+ writel(0x19239145, ccm + MX5_CCM_CBCDR);
+ /* make sure divider effective */
+ while (readl(ccm + MX5_CCM_CDHIPR));
+
+ /* Switch ARM to step clock */
+ writel(0x4, ccm + MX5_CCM_CCSR);
+
+ setup_pll_800((void __iomem *)MX51_PLL1_BASE_ADDR);
+ setup_pll_665((void __iomem *)MX51_PLL3_BASE_ADDR);
+
+ /* Switch peripheral to PLL 3 */
+ writel(0x000010C0, ccm + MX5_CCM_CBCMR);
+ writel(0x13239145, ccm + MX5_CCM_CBCDR);
+
+ setup_pll_665((void __iomem *)MX51_PLL2_BASE_ADDR);
+
+ /* Switch peripheral to PLL2 */
+ writel(0x19239145, ccm + MX5_CCM_CBCDR);
+ writel(0x000020C0, ccm + MX5_CCM_CBCMR);
+
+ setup_pll_216((void __iomem *)MX51_PLL3_BASE_ADDR);
+
+ /* Set the platform clock dividers */
+ writel(0x00000124, MX51_ARM_BASE_ADDR + 0x14);
+
+ /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
+ if (imx_silicon_revision() == MX51_CHIP_REV_3_0)
+ writel(0x0, ccm + MX5_CCM_CACRR);
+ else
+ writel(0x1, ccm + MX5_CCM_CACRR);
+
+ /* Switch ARM back to PLL 1 */
+ writel(0x0, ccm + MX5_CCM_CCSR);
+
+ /* setup the rest */
+ /* Use lp_apm (24MHz) source for perclk */
+ writel(0x000020C2, ccm + MX5_CCM_CBCMR);
+ /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
+ writel(0x59239100, ccm + MX5_CCM_CBCDR);
+
+ /* Restore the default values in the Gate registers */
+ writel(0xffffffff, ccm + MX5_CCM_CCGR0);
+ writel(0xffffffff, ccm + MX5_CCM_CCGR1);
+ writel(0xffffffff, ccm + MX5_CCM_CCGR2);
+ writel(0xffffffff, ccm + MX5_CCM_CCGR3);
+ writel(0xffffffff, ccm + MX5_CCM_CCGR4);
+ writel(0xffffffff, ccm + MX5_CCM_CCGR5);
+ writel(0xffffffff, ccm + MX5_CCM_CCGR6);
+
+ /* Use PLL 2 for UART's, get 66.5MHz from it */
+ writel(0xA5A2A020, ccm + MX5_CCM_CSCMR1);
+ writel(0x00C30321, ccm + MX5_CCM_CSCDR1);
+
+ /* make sure divider effective */
+ while (readl(ccm + MX5_CCM_CDHIPR));
+
+ writel(0x0, ccm + MX5_CCM_CCDR);
+
+ writel(0x1, 0x73fa8074);
+
+ r = readl(0x73f88000);
+ r |= 0x40;
+ writel(r, 0x73f88000);
+
+ r = readl(0x73f88004);
+ r |= 0x40;
+ writel(r, 0x73f88004);
+}
diff --git a/arch/arm/mach-imx/include/mach/imx5.h b/arch/arm/mach-imx/include/mach/imx5.h
index d034082..0491179 100644
--- a/arch/arm/mach-imx/include/mach/imx5.h
+++ b/arch/arm/mach-imx/include/mach/imx5.h
@@ -2,6 +2,7 @@
#define __MACH_MX5_H
void imx53_init_lowlevel(void);
+void imx51_init_lowlevel(void);
void imx5_setup_pll(void __iomem *base, int freq, u32 op, u32 mfd, u32 mfn);
void imx5_init_lowlevel(void);
--
1.7.7.3
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 3/9] ARM i.MX51 babbage: use generic lowlevel init function
2011-12-17 14:52 Thumb-2 support Sascha Hauer
2011-12-17 14:52 ` [PATCH 1/9] ARM i.MX5: prepare to add a imx51_lowlevel_init Sascha Hauer
2011-12-17 14:52 ` [PATCH 2/9] ARM i.MX51: implement " Sascha Hauer
@ 2011-12-17 14:52 ` Sascha Hauer
2011-12-17 14:52 ` [PATCH 4/9] ARM eukrea i.MX51: use generic lowlevel init Sascha Hauer
` (5 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2011-12-17 14:52 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/freescale-mx51-pdk/Makefile | 1 -
arch/arm/boards/freescale-mx51-pdk/board.c | 3 +
arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S | 216 --------------------
arch/arm/mach-imx/Kconfig | 1 -
4 files changed, 3 insertions(+), 218 deletions(-)
delete mode 100644 arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S
diff --git a/arch/arm/boards/freescale-mx51-pdk/Makefile b/arch/arm/boards/freescale-mx51-pdk/Makefile
index 8e0c87c..b56ce7f 100644
--- a/arch/arm/boards/freescale-mx51-pdk/Makefile
+++ b/arch/arm/boards/freescale-mx51-pdk/Makefile
@@ -1,3 +1,2 @@
-obj-y += lowlevel_init.o
obj-y += board.o
obj-y += flash_header.o
diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c
index d56effa..e6781f3 100644
--- a/arch/arm/boards/freescale-mx51-pdk/board.c
+++ b/arch/arm/boards/freescale-mx51-pdk/board.c
@@ -34,6 +34,7 @@
#include <mfd/mc13892.h>
#include <io.h>
#include <asm/mmu.h>
+#include <mach/imx5.h>
#include <mach/imx-nand.h>
#include <mach/spi.h>
#include <mach/generic.h>
@@ -265,6 +266,8 @@ static int f3s_console_init(void)
{
mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads));
+ imx51_init_lowlevel();
+
writel(0, 0x73fa8228);
writel(0, 0x73fa822c);
writel(0, 0x73fa8230);
diff --git a/arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S b/arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S
deleted file mode 100644
index 0b3726f..0000000
--- a/arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * This code is based on the ecos babbage startup code
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <mach/imx-regs.h>
-#include <mach/clock-imx51_53.h>
-
-#define ROM_SI_REV_OFFSET 0x48
-
-.macro setup_pll pll, freq
- ldr r2, =\pll
- ldr r1, =0x00001232
- str r1, [r2, #MX5_PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
- mov r1, #0x2
- str r1, [r2, #MX5_PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
-
- str r3, [r2, #MX5_PLL_DP_OP]
- str r3, [r2, #MX5_PLL_DP_HFS_OP]
-
- str r4, [r2, #MX5_PLL_DP_MFD]
- str r4, [r2, #MX5_PLL_DP_HFS_MFD]
-
- str r5, [r2, #MX5_PLL_DP_MFN]
- str r5, [r2, #MX5_PLL_DP_HFS_MFN]
-
- ldr r1, =0x00001232
- str r1, [r2, #MX5_PLL_DP_CTL]
-1: ldr r1, [r2, #MX5_PLL_DP_CTL]
- ands r1, r1, #0x1
- beq 1b
-.endm
-
-#define writel(val, reg) \
- ldr r0, =reg; \
- ldr r1, =val; \
- str r1, [r0];
-
-#define IMX51_TO_2
-
-.globl board_init_lowlevel
-board_init_lowlevel:
- mov r10, lr
-
- /* explicitly disable L2 cache */
- mrc 15, 0, r0, c1, c0, 1
- bic r0, r0, #0x2
- mcr 15, 0, r0, c1, c0, 1
-
- /* reconfigure L2 cache aux control reg */
- mov r0, #0xC0 /* tag RAM */
- add r0, r0, #0x4 /* data RAM */
- orr r0, r0, #(1 << 24) /* disable write allocate delay */
- orr r0, r0, #(1 << 23) /* disable write allocate combine */
- orr r0, r0, #(1 << 22) /* disable write allocate */
-
- ldr r1, =MX51_IROM_BASE_ADDR
- ldr r3, [r1, #ROM_SI_REV_OFFSET]
- cmp r3, #0x10
- orrls r0, r0, #(1 << 25) /* disable write combine for TO 2 and lower revs */
-
- mcr 15, 1, r0, c9, c0, 2
-
- ldr r0, =MX51_CCM_BASE_ADDR
-
- /* Gate of clocks to the peripherals first */
- ldr r1, =0x3FFFFFFF
- str r1, [r0, #MX5_CCM_CCGR0]
- ldr r1, =0x0
- str r1, [r0, #MX5_CCM_CCGR1]
- str r1, [r0, #MX5_CCM_CCGR2]
- str r1, [r0, #MX5_CCM_CCGR3]
-
- ldr r1, =0x00030000
- str r1, [r0, #MX5_CCM_CCGR4]
- ldr r1, =0x00FFF030
- str r1, [r0, #MX5_CCM_CCGR5]
- ldr r1, =0x00000300
- str r1, [r0, #MX5_CCM_CCGR6]
-
- /* Disable IPU and HSC dividers */
- mov r1, #0x60000
- str r1, [r0, #MX5_CCM_CCDR]
-
-#ifdef IMX51_TO_2
- /* Make sure to switch the DDR away from PLL 1 */
- ldr r1, =0x19239145
- str r1, [r0, #MX5_CCM_CBCDR]
- /* make sure divider effective */
-1: ldr r1, [r0, #MX5_CCM_CDHIPR]
- cmp r1, #0x0
- bne 1b
-#endif
-
- /* Switch ARM to step clock */
- mov r1, #0x4
- str r1, [r0, #MX5_CCM_CCSR]
-
- mov r3, #MX5_PLL_DP_OP_800
- mov r4, #MX5_PLL_DP_MFD_800
- mov r5, #MX5_PLL_DP_MFN_800
- setup_pll MX51_PLL1_BASE_ADDR
-
- mov r3, #MX5_PLL_DP_OP_665
- mov r4, #MX5_PLL_DP_MFD_665
- mov r5, #MX5_PLL_DP_MFN_665
- setup_pll MX51_PLL3_BASE_ADDR
-
- /* Switch peripheral to PLL 3 */
- ldr r1, =0x000010C0
- str r1, [r0, #MX5_CCM_CBCMR]
- ldr r1, =0x13239145
- str r1, [r0, #MX5_CCM_CBCDR]
-
- mov r3, #MX5_PLL_DP_OP_665
- mov r4, #MX5_PLL_DP_MFD_665
- mov r5, #MX5_PLL_DP_MFN_665
- setup_pll MX51_PLL2_BASE_ADDR
-
- /* Switch peripheral to PLL2 */
- ldr r1, =0x19239145
- str r1, [r0, #MX5_CCM_CBCDR]
- ldr r1, =0x000020C0
- str r1, [r0, #MX5_CCM_CBCMR]
-
- mov r3, #MX5_PLL_DP_OP_216
- mov r4, #MX5_PLL_DP_MFD_216
- mov r5, #MX5_PLL_DP_MFN_216
- setup_pll MX51_PLL3_BASE_ADDR
-
- /* Set the platform clock dividers */
- ldr r2, =MX51_ARM_BASE_ADDR
- ldr r1, =0x00000124
- str r1, [r2, #0x14]
-
- /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
- ldr r1, =MX51_IROM_BASE_ADDR
- ldr r3, [r1, #ROM_SI_REV_OFFSET]
- cmp r3, #0x10
- movls r1, #0x1
- movhi r1, #0
- str r1, [r0, #MX5_CCM_CACRR]
-
- /* Switch ARM back to PLL 1 */
- mov r1, #0
- str r1, [r0, #MX5_CCM_CCSR]
-
- /* setup the rest */
- /* Use lp_apm (24MHz) source for perclk */
-#ifdef IMX51_TO_2
- ldr r1, =0x000020C2
- str r1, [r0, #MX5_CCM_CBCMR]
- // ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
- ldr r1, =0x59239100
- str r1, [r0, #MX5_CCM_CBCDR]
-#else
- ldr r1, =0x0000E3C2
- str r1, [r0, #MX5_CCM_CBCMR]
- // emi=ahb, all perclk dividers are 1 since using 24MHz
- // DDR divider=6 to have 665/6=110MHz
- ldr r1, =0x013B9100
- str r1, [r0, #MX5_CCM_CBCDR]
-#endif
-
- /* Restore the default values in the Gate registers */
- ldr r1, =0xFFFFFFFF
- str r1, [r0, #MX5_CCM_CCGR0]
- str r1, [r0, #MX5_CCM_CCGR1]
- str r1, [r0, #MX5_CCM_CCGR2]
- str r1, [r0, #MX5_CCM_CCGR3]
- str r1, [r0, #MX5_CCM_CCGR4]
- str r1, [r0, #MX5_CCM_CCGR5]
- str r1, [r0, #MX5_CCM_CCGR6]
-
- /* Use PLL 2 for UART's, get 66.5MHz from it */
- ldr r1, =0xA5A2A020
- str r1, [r0, #MX5_CCM_CSCMR1]
- ldr r1, =0x00C30321
- str r1, [r0, #MX5_CCM_CSCDR1]
-
- /* make sure divider effective */
- 1: ldr r1, [r0, #MX5_CCM_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- mov r1, #0x0
- str r1, [r0, #MX5_CCM_CCDR]
-
- writel(0x1, 0x73fa8074)
- ldr r0, =0x73f88000
- ldr r1, [r0]
- orr r1, #0x40
- str r1, [r0]
-
- ldr r0, =0x73f88004
- ldr r1, [r0]
- orr r1, #0x40
- str r1, [r0]
-
- mov pc, r10
-
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 27bf386..fa3b184 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -372,7 +372,6 @@ choice
config MACH_FREESCALE_MX51_PDK
bool "Freescale i.MX51 PDK"
- select MACH_HAS_LOWLEVEL_INIT
config MACH_EUKREA_CPUIMX51SD
bool "EUKREA CPUIMX51"
--
1.7.7.3
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 4/9] ARM eukrea i.MX51: use generic lowlevel init
2011-12-17 14:52 Thumb-2 support Sascha Hauer
` (2 preceding siblings ...)
2011-12-17 14:52 ` [PATCH 3/9] ARM i.MX51 babbage: use generic lowlevel init function Sascha Hauer
@ 2011-12-17 14:52 ` Sascha Hauer
2011-12-17 14:52 ` [PATCH 5/9] ARM: update string functions from Linux Kernel Sascha Hauer
` (4 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2011-12-17 14:52 UTC (permalink / raw)
To: barebox
The lowlevel init function was a 1:1 copy from the babbage
baord, so it should be safe to switch to the generic C
lowlevel init.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Eric Benard <eric@eukrea.com>
---
arch/arm/boards/eukrea_cpuimx51/Makefile | 1 -
arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c | 3 +
arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S | 216 ---------------------
arch/arm/mach-imx/Kconfig | 1 -
4 files changed, 3 insertions(+), 218 deletions(-)
delete mode 100644 arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
diff --git a/arch/arm/boards/eukrea_cpuimx51/Makefile b/arch/arm/boards/eukrea_cpuimx51/Makefile
index 0f506a3..0f781c0 100644
--- a/arch/arm/boards/eukrea_cpuimx51/Makefile
+++ b/arch/arm/boards/eukrea_cpuimx51/Makefile
@@ -1,3 +1,2 @@
-obj-y += lowlevel_init.o
obj-y += eukrea_cpuimx51.o
obj-y += flash_header.o
diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
index a2db6d9..153ad2f 100644
--- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
+++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
@@ -39,6 +39,7 @@
#include <mach/imx-nand.h>
#include <mach/spi.h>
#include <mach/generic.h>
+#include <mach/imx5.h>
#include <mach/iomux-mx51.h>
#include <mach/devices-imx51.h>
@@ -139,6 +140,8 @@ static int eukrea_cpuimx51_console_init(void)
{
mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads, ARRAY_SIZE(eukrea_cpuimx51_pads));
+ imx51_init_lowlevel();
+
writel(0, 0x73fa8228);
writel(0, 0x73fa822c);
writel(0, 0x73fa8230);
diff --git a/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
deleted file mode 100644
index 0b3726f..0000000
--- a/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * This code is based on the ecos babbage startup code
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <mach/imx-regs.h>
-#include <mach/clock-imx51_53.h>
-
-#define ROM_SI_REV_OFFSET 0x48
-
-.macro setup_pll pll, freq
- ldr r2, =\pll
- ldr r1, =0x00001232
- str r1, [r2, #MX5_PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
- mov r1, #0x2
- str r1, [r2, #MX5_PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
-
- str r3, [r2, #MX5_PLL_DP_OP]
- str r3, [r2, #MX5_PLL_DP_HFS_OP]
-
- str r4, [r2, #MX5_PLL_DP_MFD]
- str r4, [r2, #MX5_PLL_DP_HFS_MFD]
-
- str r5, [r2, #MX5_PLL_DP_MFN]
- str r5, [r2, #MX5_PLL_DP_HFS_MFN]
-
- ldr r1, =0x00001232
- str r1, [r2, #MX5_PLL_DP_CTL]
-1: ldr r1, [r2, #MX5_PLL_DP_CTL]
- ands r1, r1, #0x1
- beq 1b
-.endm
-
-#define writel(val, reg) \
- ldr r0, =reg; \
- ldr r1, =val; \
- str r1, [r0];
-
-#define IMX51_TO_2
-
-.globl board_init_lowlevel
-board_init_lowlevel:
- mov r10, lr
-
- /* explicitly disable L2 cache */
- mrc 15, 0, r0, c1, c0, 1
- bic r0, r0, #0x2
- mcr 15, 0, r0, c1, c0, 1
-
- /* reconfigure L2 cache aux control reg */
- mov r0, #0xC0 /* tag RAM */
- add r0, r0, #0x4 /* data RAM */
- orr r0, r0, #(1 << 24) /* disable write allocate delay */
- orr r0, r0, #(1 << 23) /* disable write allocate combine */
- orr r0, r0, #(1 << 22) /* disable write allocate */
-
- ldr r1, =MX51_IROM_BASE_ADDR
- ldr r3, [r1, #ROM_SI_REV_OFFSET]
- cmp r3, #0x10
- orrls r0, r0, #(1 << 25) /* disable write combine for TO 2 and lower revs */
-
- mcr 15, 1, r0, c9, c0, 2
-
- ldr r0, =MX51_CCM_BASE_ADDR
-
- /* Gate of clocks to the peripherals first */
- ldr r1, =0x3FFFFFFF
- str r1, [r0, #MX5_CCM_CCGR0]
- ldr r1, =0x0
- str r1, [r0, #MX5_CCM_CCGR1]
- str r1, [r0, #MX5_CCM_CCGR2]
- str r1, [r0, #MX5_CCM_CCGR3]
-
- ldr r1, =0x00030000
- str r1, [r0, #MX5_CCM_CCGR4]
- ldr r1, =0x00FFF030
- str r1, [r0, #MX5_CCM_CCGR5]
- ldr r1, =0x00000300
- str r1, [r0, #MX5_CCM_CCGR6]
-
- /* Disable IPU and HSC dividers */
- mov r1, #0x60000
- str r1, [r0, #MX5_CCM_CCDR]
-
-#ifdef IMX51_TO_2
- /* Make sure to switch the DDR away from PLL 1 */
- ldr r1, =0x19239145
- str r1, [r0, #MX5_CCM_CBCDR]
- /* make sure divider effective */
-1: ldr r1, [r0, #MX5_CCM_CDHIPR]
- cmp r1, #0x0
- bne 1b
-#endif
-
- /* Switch ARM to step clock */
- mov r1, #0x4
- str r1, [r0, #MX5_CCM_CCSR]
-
- mov r3, #MX5_PLL_DP_OP_800
- mov r4, #MX5_PLL_DP_MFD_800
- mov r5, #MX5_PLL_DP_MFN_800
- setup_pll MX51_PLL1_BASE_ADDR
-
- mov r3, #MX5_PLL_DP_OP_665
- mov r4, #MX5_PLL_DP_MFD_665
- mov r5, #MX5_PLL_DP_MFN_665
- setup_pll MX51_PLL3_BASE_ADDR
-
- /* Switch peripheral to PLL 3 */
- ldr r1, =0x000010C0
- str r1, [r0, #MX5_CCM_CBCMR]
- ldr r1, =0x13239145
- str r1, [r0, #MX5_CCM_CBCDR]
-
- mov r3, #MX5_PLL_DP_OP_665
- mov r4, #MX5_PLL_DP_MFD_665
- mov r5, #MX5_PLL_DP_MFN_665
- setup_pll MX51_PLL2_BASE_ADDR
-
- /* Switch peripheral to PLL2 */
- ldr r1, =0x19239145
- str r1, [r0, #MX5_CCM_CBCDR]
- ldr r1, =0x000020C0
- str r1, [r0, #MX5_CCM_CBCMR]
-
- mov r3, #MX5_PLL_DP_OP_216
- mov r4, #MX5_PLL_DP_MFD_216
- mov r5, #MX5_PLL_DP_MFN_216
- setup_pll MX51_PLL3_BASE_ADDR
-
- /* Set the platform clock dividers */
- ldr r2, =MX51_ARM_BASE_ADDR
- ldr r1, =0x00000124
- str r1, [r2, #0x14]
-
- /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
- ldr r1, =MX51_IROM_BASE_ADDR
- ldr r3, [r1, #ROM_SI_REV_OFFSET]
- cmp r3, #0x10
- movls r1, #0x1
- movhi r1, #0
- str r1, [r0, #MX5_CCM_CACRR]
-
- /* Switch ARM back to PLL 1 */
- mov r1, #0
- str r1, [r0, #MX5_CCM_CCSR]
-
- /* setup the rest */
- /* Use lp_apm (24MHz) source for perclk */
-#ifdef IMX51_TO_2
- ldr r1, =0x000020C2
- str r1, [r0, #MX5_CCM_CBCMR]
- // ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
- ldr r1, =0x59239100
- str r1, [r0, #MX5_CCM_CBCDR]
-#else
- ldr r1, =0x0000E3C2
- str r1, [r0, #MX5_CCM_CBCMR]
- // emi=ahb, all perclk dividers are 1 since using 24MHz
- // DDR divider=6 to have 665/6=110MHz
- ldr r1, =0x013B9100
- str r1, [r0, #MX5_CCM_CBCDR]
-#endif
-
- /* Restore the default values in the Gate registers */
- ldr r1, =0xFFFFFFFF
- str r1, [r0, #MX5_CCM_CCGR0]
- str r1, [r0, #MX5_CCM_CCGR1]
- str r1, [r0, #MX5_CCM_CCGR2]
- str r1, [r0, #MX5_CCM_CCGR3]
- str r1, [r0, #MX5_CCM_CCGR4]
- str r1, [r0, #MX5_CCM_CCGR5]
- str r1, [r0, #MX5_CCM_CCGR6]
-
- /* Use PLL 2 for UART's, get 66.5MHz from it */
- ldr r1, =0xA5A2A020
- str r1, [r0, #MX5_CCM_CSCMR1]
- ldr r1, =0x00C30321
- str r1, [r0, #MX5_CCM_CSCDR1]
-
- /* make sure divider effective */
- 1: ldr r1, [r0, #MX5_CCM_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- mov r1, #0x0
- str r1, [r0, #MX5_CCM_CCDR]
-
- writel(0x1, 0x73fa8074)
- ldr r0, =0x73f88000
- ldr r1, [r0]
- orr r1, #0x40
- str r1, [r0]
-
- ldr r0, =0x73f88004
- ldr r1, [r0]
- orr r1, #0x40
- str r1, [r0]
-
- mov pc, r10
-
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index fa3b184..7da39cb 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -375,7 +375,6 @@ config MACH_FREESCALE_MX51_PDK
config MACH_EUKREA_CPUIMX51SD
bool "EUKREA CPUIMX51"
- select MACH_HAS_LOWLEVEL_INIT
help
Say Y here if you are using Eukrea's CPUIMX51 equipped
with a Freescale i.MX51 Processor
--
1.7.7.3
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 5/9] ARM: update string functions from Linux Kernel
2011-12-17 14:52 Thumb-2 support Sascha Hauer
` (3 preceding siblings ...)
2011-12-17 14:52 ` [PATCH 4/9] ARM eukrea i.MX51: use generic lowlevel init Sascha Hauer
@ 2011-12-17 14:52 ` Sascha Hauer
2011-12-17 14:52 ` [PATCH 6/9] ARM cache-armv7: use thumb-2 instructions where necessary Sascha Hauer
` (3 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2011-12-17 14:52 UTC (permalink / raw)
To: barebox
The newer versions contain fixes for Thumb-2 mode.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/lib/copy_template.S | 24 ++++++++++-
arch/arm/lib/findbit.S | 84 ++++++++++++++++++++++++---------------
arch/arm/lib/io-writesw-armv4.S | 11 +++--
arch/arm/lib/memcpy.S | 7 ++-
4 files changed, 85 insertions(+), 41 deletions(-)
diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
index 61b6e54..d8eb063 100644
--- a/arch/arm/lib/copy_template.S
+++ b/arch/arm/lib/copy_template.S
@@ -57,6 +57,13 @@
*
* Restore registers with the values previously saved with the
* 'preserv' macro. Called upon code termination.
+ *
+ * LDR1W_SHIFT
+ * STR1W_SHIFT
+ *
+ * Correction to be applied to the "ip" register when branching into
+ * the ldr1w or str1w instructions (some of these macros may expand to
+ * than one 32bit instruction in Thumb-2)
*/
@@ -99,9 +106,15 @@
5: ands ip, r2, #28
rsb ip, ip, #32
+#if LDR1W_SHIFT > 0
+ lsl ip, ip, #LDR1W_SHIFT
+#endif
addne pc, pc, ip @ C is always clear here
b 7f
-6: nop
+6:
+ .rept (1 << LDR1W_SHIFT)
+ W(nop)
+ .endr
ldr1w r1, r3, abort=20f
ldr1w r1, r4, abort=20f
ldr1w r1, r5, abort=20f
@@ -110,9 +123,16 @@
ldr1w r1, r8, abort=20f
ldr1w r1, lr, abort=20f
+#if LDR1W_SHIFT < STR1W_SHIFT
+ lsl ip, ip, #STR1W_SHIFT - LDR1W_SHIFT
+#elif LDR1W_SHIFT > STR1W_SHIFT
+ lsr ip, ip, #LDR1W_SHIFT - STR1W_SHIFT
+#endif
add pc, pc, ip
nop
- nop
+ .rept (1 << STR1W_SHIFT)
+ W(nop)
+ .endr
str1w r0, r3, abort=20f
str1w r0, r4, abort=20f
str1w r0, r5, abort=20f
diff --git a/arch/arm/lib/findbit.S b/arch/arm/lib/findbit.S
index 7fa93a5..ef4caff 100644
--- a/arch/arm/lib/findbit.S
+++ b/arch/arm/lib/findbit.S
@@ -14,18 +14,22 @@
* also call with zero size.
* Reworked by rmk.
*/
- .section .text.basic_bit_functions
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+ .text
/*
* Purpose : Find a 'zero' bit
* Prototype: int find_first_zero_bit(void *addr, unsigned int maxbit);
*/
- .globl _find_first_zero_bit_le;
-_find_first_zero_bit_le:
+ENTRY(_find_first_zero_bit_le)
teq r1, #0
beq 3f
mov r2, #0
-1: ldrb r3, [r0, r2, lsr #3]
+1:
+ ARM( ldrb r3, [r0, r2, lsr #3] )
+ THUMB( lsr r3, r2, #3 )
+ THUMB( ldrb r3, [r0, r3] )
eors r3, r3, #0xff @ invert bits
bne .L_found @ any now set - found zero bit
add r2, r2, #8 @ next bit pointer
@@ -33,36 +37,40 @@ _find_first_zero_bit_le:
blo 1b
3: mov r0, r1 @ no free bits
mov pc, lr
+ENDPROC(_find_first_zero_bit_le)
/*
* Purpose : Find next 'zero' bit
- * Prototype: int find_next_zero_bit(void *addr, unsigned int maxbit,
- * int offset)
+ * Prototype: int find_next_zero_bit(void *addr, unsigned int maxbit, int offset)
*/
- .globl _find_next_zero_bit_le;
-_find_next_zero_bit_le:
+ENTRY(_find_next_zero_bit_le)
teq r1, #0
beq 3b
ands ip, r2, #7
beq 1b @ If new byte, goto old routine
- ldrb r3, [r0, r2, lsr #3]
+ ARM( ldrb r3, [r0, r2, lsr #3] )
+ THUMB( lsr r3, r2, #3 )
+ THUMB( ldrb r3, [r0, r3] )
eor r3, r3, #0xff @ now looking for a 1 bit
movs r3, r3, lsr ip @ shift off unused bits
bne .L_found
orr r2, r2, #7 @ if zero, then no bits here
add r2, r2, #1 @ align bit pointer
b 2b @ loop for next bit
+ENDPROC(_find_next_zero_bit_le)
/*
* Purpose : Find a 'one' bit
- * Prototype: int find_first_bit(const unsigned long *addr, unsigned int maxbit)
+ * Prototype: int find_first_bit(const unsigned long *addr, unsigned int maxbit);
*/
- .globl _find_first_bit_le;
-_find_first_bit_le:
+ENTRY(_find_first_bit_le)
teq r1, #0
beq 3f
mov r2, #0
-1: ldrb r3, [r0, r2, lsr #3]
+1:
+ ARM( ldrb r3, [r0, r2, lsr #3] )
+ THUMB( lsr r3, r2, #3 )
+ THUMB( ldrb r3, [r0, r3] )
movs r3, r3
bne .L_found @ any now set - found zero bit
add r2, r2, #8 @ next bit pointer
@@ -70,34 +78,37 @@ _find_first_bit_le:
blo 1b
3: mov r0, r1 @ no free bits
mov pc, lr
+ENDPROC(_find_first_bit_le)
/*
* Purpose : Find next 'one' bit
- * Prototype: int find_next_zero_bit(void *addr, unsigned int maxbit,
- * int offset)
+ * Prototype: int find_next_zero_bit(void *addr, unsigned int maxbit, int offset)
*/
- .globl _find_next_bit_le;
-_find_next_bit_le:
+ENTRY(_find_next_bit_le)
teq r1, #0
beq 3b
ands ip, r2, #7
beq 1b @ If new byte, goto old routine
- ldrb r3, [r0, r2, lsr #3]
+ ARM( ldrb r3, [r0, r2, lsr #3] )
+ THUMB( lsr r3, r2, #3 )
+ THUMB( ldrb r3, [r0, r3] )
movs r3, r3, lsr ip @ shift off unused bits
bne .L_found
orr r2, r2, #7 @ if zero, then no bits here
add r2, r2, #1 @ align bit pointer
b 2b @ loop for next bit
+ENDPROC(_find_next_bit_le)
#ifdef __ARMEB__
- .globl _find_first_zero_bit_be;
-_find_first_zero_bit_be:
+ENTRY(_find_first_zero_bit_be)
teq r1, #0
beq 3f
mov r2, #0
1: eor r3, r2, #0x18 @ big endian byte ordering
- ldrb r3, [r0, r3, lsr #3]
+ ARM( ldrb r3, [r0, r3, lsr #3] )
+ THUMB( lsr r3, #3 )
+ THUMB( ldrb r3, [r0, r3] )
eors r3, r3, #0xff @ invert bits
bne .L_found @ any now set - found zero bit
add r2, r2, #8 @ next bit pointer
@@ -105,29 +116,33 @@ _find_first_zero_bit_be:
blo 1b
3: mov r0, r1 @ no free bits
mov pc, lr
+ENDPROC(_find_first_zero_bit_be)
- .globl _find_next_zero_bit_be;
-_find_next_zero_bit_be:
+ENTRY(_find_next_zero_bit_be)
teq r1, #0
beq 3b
ands ip, r2, #7
beq 1b @ If new byte, goto old routine
eor r3, r2, #0x18 @ big endian byte ordering
- ldrb r3, [r0, r3, lsr #3]
+ ARM( ldrb r3, [r0, r3, lsr #3] )
+ THUMB( lsr r3, #3 )
+ THUMB( ldrb r3, [r0, r3] )
eor r3, r3, #0xff @ now looking for a 1 bit
movs r3, r3, lsr ip @ shift off unused bits
bne .L_found
orr r2, r2, #7 @ if zero, then no bits here
add r2, r2, #1 @ align bit pointer
b 2b @ loop for next bit
+ENDPROC(_find_next_zero_bit_be)
- .globl _find_first_bit_be;
-_find_first_bit_be:
+ENTRY(_find_first_bit_be)
teq r1, #0
beq 3f
mov r2, #0
1: eor r3, r2, #0x18 @ big endian byte ordering
- ldrb r3, [r0, r3, lsr #3]
+ ARM( ldrb r3, [r0, r3, lsr #3] )
+ THUMB( lsr r3, #3 )
+ THUMB( ldrb r3, [r0, r3] )
movs r3, r3
bne .L_found @ any now set - found zero bit
add r2, r2, #8 @ next bit pointer
@@ -135,20 +150,23 @@ _find_first_bit_be:
blo 1b
3: mov r0, r1 @ no free bits
mov pc, lr
+ENDPROC(_find_first_bit_be)
- .globl _find_next_bit_be;
-_find_next_bit_be:
+ENTRY(_find_next_bit_be)
teq r1, #0
beq 3b
ands ip, r2, #7
beq 1b @ If new byte, goto old routine
eor r3, r2, #0x18 @ big endian byte ordering
- ldrb r3, [r0, r3, lsr #3]
+ ARM( ldrb r3, [r0, r3, lsr #3] )
+ THUMB( lsr r3, #3 )
+ THUMB( ldrb r3, [r0, r3] )
movs r3, r3, lsr ip @ shift off unused bits
bne .L_found
orr r2, r2, #7 @ if zero, then no bits here
add r2, r2, #1 @ align bit pointer
b 2b @ loop for next bit
+ENDPROC(_find_next_bit_be)
#endif
@@ -157,8 +175,8 @@ _find_next_bit_be:
*/
.L_found:
#if __LINUX_ARM_ARCH__ >= 5
- rsb r1, r3, #0
- and r3, r3, r1
+ rsb r0, r3, #0
+ and r3, r3, r0
clz r3, r3
rsb r3, r3, #31
add r0, r2, r3
@@ -173,5 +191,7 @@ _find_next_bit_be:
addeq r2, r2, #1
mov r0, r2
#endif
+ cmp r1, r0 @ Clamp to maxbit
+ movlo r0, r1
mov pc, lr
diff --git a/arch/arm/lib/io-writesw-armv4.S b/arch/arm/lib/io-writesw-armv4.S
index cd0aa7f..ff4f71b 100644
--- a/arch/arm/lib/io-writesw-armv4.S
+++ b/arch/arm/lib/io-writesw-armv4.S
@@ -22,8 +22,6 @@
#endif
.endm
-.section .text.writesw
-
.Loutsw_align: movs ip, r1, lsl #31
bne .Loutsw_noalign
@@ -31,7 +29,7 @@
sub r2, r2, #1
strh r3, [r0]
-ENTRY(writesw)
+ENTRY(__raw_writesw)
teq r2, #0
moveq pc, lr
ands r3, r1, #3
@@ -77,7 +75,10 @@ ENTRY(writesw)
#endif
.Loutsw_noalign:
- ldr r3, [r1, -r3]!
+ ARM( ldr r3, [r1, -r3]! )
+ THUMB( rsb r3, r3, #0 )
+ THUMB( ldr r3, [r1, r3] )
+ THUMB( sub r1, r3 )
subcs r2, r2, #1
bcs 2f
subs r2, r2, #2
@@ -96,4 +97,4 @@ ENTRY(writesw)
3: movne ip, r3, lsr #8
strneh ip, [r0]
mov pc, lr
-ENDPROC(writesw)
+ENDPROC(__raw_writesw)
diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index 513ed64..5123691 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -13,8 +13,11 @@
#include <linux/linkage.h>
#include <asm/assembler.h>
+#define LDR1W_SHIFT 0
+#define STR1W_SHIFT 0
+
.macro ldr1w ptr reg abort
- ldr \reg, [\ptr], #4
+ W(ldr) \reg, [\ptr], #4
.endm
.macro ldr4w ptr reg1 reg2 reg3 reg4 abort
@@ -30,7 +33,7 @@
.endm
.macro str1w ptr reg abort
- str \reg, [\ptr], #4
+ W(str) \reg, [\ptr], #4
.endm
.macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
--
1.7.7.3
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 6/9] ARM cache-armv7: use thumb-2 instructions where necessary
2011-12-17 14:52 Thumb-2 support Sascha Hauer
` (4 preceding siblings ...)
2011-12-17 14:52 ` [PATCH 5/9] ARM: update string functions from Linux Kernel Sascha Hauer
@ 2011-12-17 14:52 ` Sascha Hauer
2011-12-17 14:52 ` [PATCH 7/9] ARM: move exception vectors away from start of binary Sascha Hauer
` (2 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2011-12-17 14:52 UTC (permalink / raw)
To: barebox
Copied from the Kernel
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/cache-armv7.S | 8 ++++++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index 5b8491e..f25dcfa 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -84,8 +84,12 @@ loop1:
loop2:
mov r9, r4 @ create working copy of max way size
loop3:
- orr r11, r10, r9, lsl r5 @ factor way and cache number into r11
- orr r11, r11, r7, lsl r2 @ factor index number into r11
+ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
+ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
+THUMB( lsl r6, r9, r5 )
+THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
+THUMB( lsl r6, r7, r2 )
+THUMB( orr r11, r11, r6 ) @ factor index number into r11
mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
subs r9, r9, #1 @ decrement the way
bge loop3
--
1.7.7.3
_______________________________________________
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 7/9] ARM: move exception vectors away from start of binary
2011-12-17 14:52 Thumb-2 support Sascha Hauer
` (5 preceding siblings ...)
2011-12-17 14:52 ` [PATCH 6/9] ARM cache-armv7: use thumb-2 instructions where necessary Sascha Hauer
@ 2011-12-17 14:52 ` Sascha Hauer
2011-12-18 23:43 ` Peter Korsgaard
` (2 more replies)
2011-12-17 14:52 ` [PATCH 8/9] ARM: get runtime offset of board_init_lowlevel_return by using separate section Sascha Hauer
2011-12-17 14:52 ` [PATCH 9/9] ARM: Allow to compile in thumb-2 mode Sascha Hauer
8 siblings, 3 replies; 20+ messages in thread
From: Sascha Hauer @ 2011-12-17 14:52 UTC (permalink / raw)
To: barebox
Traditionally U-Boot and barebox have the exception vectors at
the start of the binary. There is no real reason in doing so,
because in the majority of cases this data will not be at 0x0
where it could be used as vectors directly anyway.
This patch puts the vectors into a separate linker section and
defines an head function which is placed at the start of the
image instead. Putting this in a separate function also has
the advantage that it can be placed at the start of images
which require an additional header like several Freescale i.MX
images. As the head function contains the barebox arm magic
those images can now also be detected aas barebox images.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c | 3 ++-
| 3 ++-
| 3 ++-
arch/arm/boards/freescale-mx25-3-stack/3stack.c | 3 ++-
| 3 ++-
| 3 ++-
| 3 ++-
| 3 ++-
arch/arm/cpu/mmu.c | 4 ++--
arch/arm/cpu/start.c | 14 +++++++-------
arch/arm/include/asm/barebox-arm-head.h | 17 +++++++++++++++++
arch/arm/include/asm/barebox-arm.h | 2 ++
arch/arm/lib/barebox.lds.S | 5 ++++-
13 files changed, 48 insertions(+), 18 deletions(-)
create mode 100644 arch/arm/include/asm/barebox-arm-head.h
diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
index 162c117..7717210 100644
--- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
+++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
@@ -46,13 +46,14 @@
#include <usb/fsl_usb2.h>
#include <mach/usb.h>
#include <mach/devices-imx25.h>
+#include <asm/barebox-arm-head.h>
extern unsigned long _stext;
extern void exception_vectors(void);
void __naked __flash_header_start go(void)
{
- __asm__ __volatile__("b exception_vectors\n");
+ barebox_arm_head();
}
struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
--git a/arch/arm/boards/eukrea_cpuimx35/flash_header.c b/arch/arm/boards/eukrea_cpuimx35/flash_header.c
index 93c8348..f8ed5d4 100644
--- a/arch/arm/boards/eukrea_cpuimx35/flash_header.c
+++ b/arch/arm/boards/eukrea_cpuimx35/flash_header.c
@@ -1,12 +1,13 @@
#include <common.h>
#include <mach/imx-flash-header.h>
#include <mach/imx-regs.h>
+#include <asm/barebox-arm-head.h>
extern void exception_vectors(void);
void __naked __flash_header_start go(void)
{
- __asm__ __volatile__("b exception_vectors\n");
+ barebox_arm_head();
}
struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
--git a/arch/arm/boards/eukrea_cpuimx51/flash_header.c b/arch/arm/boards/eukrea_cpuimx51/flash_header.c
index f953b09..ac6bbdc 100644
--- a/arch/arm/boards/eukrea_cpuimx51/flash_header.c
+++ b/arch/arm/boards/eukrea_cpuimx51/flash_header.c
@@ -1,11 +1,12 @@
#include <common.h>
#include <mach/imx-flash-header.h>
+#include <asm/barebox-arm-head.h>
extern unsigned long _stext;
void __naked __flash_header_start go(void)
{
- __asm__ __volatile__("b exception_vectors\n");
+ barebox_arm_head();
}
struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
index 5aa54e4..d7e24cf 100644
--- a/arch/arm/boards/freescale-mx25-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
@@ -42,13 +42,14 @@
#include <i2c/i2c.h>
#include <mfd/mc34704.h>
#include <mach/devices-imx25.h>
+#include <asm/barebox-arm-head.h>
extern unsigned long _stext;
extern void exception_vectors(void);
void __naked __flash_header_start go(void)
{
- __asm__ __volatile__("b exception_vectors\n");
+ barebox_arm_head();
}
struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
--git a/arch/arm/boards/freescale-mx35-3-stack/flash_header.c b/arch/arm/boards/freescale-mx35-3-stack/flash_header.c
index 4bee797..312568e 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/flash_header.c
+++ b/arch/arm/boards/freescale-mx35-3-stack/flash_header.c
@@ -1,12 +1,13 @@
#include <common.h>
#include <mach/imx-flash-header.h>
#include <mach/imx-regs.h>
+#include <asm/barebox-arm-head.h>
extern void exception_vectors(void);
void __naked __flash_header_start go(void)
{
- __asm__ __volatile__("b exception_vectors\n");
+ barebox_arm_head();
}
struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
--git a/arch/arm/boards/freescale-mx51-pdk/flash_header.c b/arch/arm/boards/freescale-mx51-pdk/flash_header.c
index 5f94506..297dca1 100644
--- a/arch/arm/boards/freescale-mx51-pdk/flash_header.c
+++ b/arch/arm/boards/freescale-mx51-pdk/flash_header.c
@@ -1,11 +1,12 @@
#include <common.h>
#include <mach/imx-flash-header.h>
+#include <asm/barebox-arm-head.h>
extern unsigned long _stext;
void __naked __flash_header_start go(void)
{
- __asm__ __volatile__("b exception_vectors\n");
+ barebox_arm_head();
}
struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
--git a/arch/arm/boards/freescale-mx53-loco/flash_header.c b/arch/arm/boards/freescale-mx53-loco/flash_header.c
index 490e223..b459640 100644
--- a/arch/arm/boards/freescale-mx53-loco/flash_header.c
+++ b/arch/arm/boards/freescale-mx53-loco/flash_header.c
@@ -16,10 +16,11 @@
#include <common.h>
#include <asm/byteorder.h>
#include <mach/imx-flash-header.h>
+#include <asm/barebox-arm-head.h>
void __naked __flash_header_start go(void)
{
- __asm__ __volatile__("b exception_vectors\n");
+ barebox_arm_head();
}
struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
--git a/arch/arm/boards/freescale-mx53-smd/flash_header.c b/arch/arm/boards/freescale-mx53-smd/flash_header.c
index 490e223..b459640 100644
--- a/arch/arm/boards/freescale-mx53-smd/flash_header.c
+++ b/arch/arm/boards/freescale-mx53-smd/flash_header.c
@@ -16,10 +16,11 @@
#include <common.h>
#include <asm/byteorder.h>
#include <mach/imx-flash-header.h>
+#include <asm/barebox-arm-head.h>
void __naked __flash_header_start go(void)
{
- __asm__ __volatile__("b exception_vectors\n");
+ barebox_arm_head();
}
struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 8e4e81a..ac60e41 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -4,6 +4,7 @@
#include <errno.h>
#include <sizes.h>
#include <asm/memory.h>
+#include <asm/barebox-arm.h>
#include <asm/system.h>
#include <memory.h>
@@ -170,7 +171,6 @@ static void vectors_init(void)
{
u32 *exc, *zero = NULL;
void *vectors;
- extern unsigned long exception_vectors;
u32 cr;
cr = get_cr();
@@ -198,7 +198,7 @@ static void vectors_init(void)
vectors = xmemalign(PAGE_SIZE, PAGE_SIZE);
memset(vectors, 0, PAGE_SIZE);
- memcpy(vectors, &exception_vectors, ARM_VECTORS_SIZE);
+ memcpy(vectors, __exceptions_start, __exceptions_stop - __exceptions_start);
if (cr & CR_V)
exc[256 - 16] = (u32)vectors | PTE_TYPE_SMALL | PTE_FLAGS_CACHED;
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index 5e09300..b3a0419 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -23,11 +23,17 @@
#include <common.h>
#include <init.h>
#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
#include <asm/system.h>
#include <asm-generic/memory_layout.h>
#include <asm/sections.h>
-void __naked __section(.text_entry) exception_vectors(void)
+void __naked __section(.text_entry) start(void)
+{
+ barebox_arm_head();
+}
+
+void __naked __section(.text_exceptions) exception_vectors(void)
{
__asm__ __volatile__ (
"b reset\n" /* reset */
@@ -48,12 +54,6 @@ void __naked __section(.text_entry) exception_vectors(void)
"1: bne 1b\n" /* irq (interrupt) */
"1: bne 1b\n" /* fiq (fast interrupt) */
#endif
- ".word 0x65726162\n" /* 'bare' */
- ".word 0x00786f62\n" /* 'box' */
- ".word _text\n" /* text base. If copied there,
- * barebox can skip relocation
- */
- ".word _barebox_image_size\n" /* image size to copy */
);
}
diff --git a/arch/arm/include/asm/barebox-arm-head.h b/arch/arm/include/asm/barebox-arm-head.h
new file mode 100644
index 0000000..ec4a68c
--- /dev/null
+++ b/arch/arm/include/asm/barebox-arm-head.h
@@ -0,0 +1,17 @@
+
+static inline void barebox_arm_head(void)
+{
+ __asm__ __volatile__ (
+ "b reset\n"
+ ".rept 7\n"
+ ".word 0x0\n"
+ ".endr\n"
+ ".word 0x65726162\n" /* 'bare' */
+ ".word 0x00786f62\n" /* 'box' */
+ ".word _text\n" /* text base. If copied there,
+ * barebox can skip relocation
+ */
+ ".word _barebox_image_size\n" /* image size to copy */
+ );
+}
+
diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
index 7bb1af1..3339782 100644
--- a/arch/arm/include/asm/barebox-arm.h
+++ b/arch/arm/include/asm/barebox-arm.h
@@ -36,6 +36,8 @@ int cleanup_before_linux(void);
int board_init(void);
int dram_init (void);
+extern char __exceptions_start[], __exceptions_stop[];
+
void board_init_lowlevel(void);
void board_init_lowlevel_return(void);
void arch_init_lowlevel(void);
diff --git a/arch/arm/lib/barebox.lds.S b/arch/arm/lib/barebox.lds.S
index f05f345..db876af 100644
--- a/arch/arm/lib/barebox.lds.S
+++ b/arch/arm/lib/barebox.lds.S
@@ -26,7 +26,7 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
-ENTRY(exception_vectors)
+ENTRY(start)
SECTIONS
{
. = TEXT_BASE;
@@ -45,6 +45,9 @@ SECTIONS
LONG(0x53555243) /* 'CRUS' */
#endif
*(.text_bare_init*)
+ __exceptions_start = .;
+ KEEP(*(.text_exceptions*))
+ __exceptions_stop = .;
*(.text*)
}
--
1.7.7.3
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 8/9] ARM: get runtime offset of board_init_lowlevel_return by using separate section
2011-12-17 14:52 Thumb-2 support Sascha Hauer
` (6 preceding siblings ...)
2011-12-17 14:52 ` [PATCH 7/9] ARM: move exception vectors away from start of binary Sascha Hauer
@ 2011-12-17 14:52 ` Sascha Hauer
2011-12-17 14:52 ` [PATCH 9/9] ARM: Allow to compile in thumb-2 mode Sascha Hauer
8 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2011-12-17 14:52 UTC (permalink / raw)
To: barebox
We used to get the runtime offset of the board_init_lowlevel_return
by doing a &board_init_lowlevel_return. This does not work in thumb-2
mode, so use a separate linker section for this function instead.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/start.c | 4 ++--
arch/arm/include/asm/barebox-arm.h | 1 +
arch/arm/lib/barebox.lds.S | 2 ++
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index b3a0419..1f4fdd2 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -100,7 +100,7 @@ void __naked __bare_init reset(void)
* Board code can jump here by either returning from board_init_lowlevel
* or by calling this funtion directly.
*/
-void __naked __bare_init board_init_lowlevel_return(void)
+void __naked __section(.text_ll_return) board_init_lowlevel_return(void)
{
uint32_t r, addr;
@@ -115,7 +115,7 @@ void __naked __bare_init board_init_lowlevel_return(void)
__asm__ __volatile__("mov sp, %0" : : "r"(r));
/* Get start of binary image */
- addr -= (uint32_t)&board_init_lowlevel_return - TEXT_BASE;
+ addr -= (uint32_t)&__ll_return - TEXT_BASE;
/* relocate to link address if necessary */
if (addr != TEXT_BASE)
diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
index 3339782..b880dd4 100644
--- a/arch/arm/include/asm/barebox-arm.h
+++ b/arch/arm/include/asm/barebox-arm.h
@@ -37,6 +37,7 @@ int board_init(void);
int dram_init (void);
extern char __exceptions_start[], __exceptions_stop[];
+extern char __ll_return[];
void board_init_lowlevel(void);
void board_init_lowlevel_return(void);
diff --git a/arch/arm/lib/barebox.lds.S b/arch/arm/lib/barebox.lds.S
index db876af..cc30f16 100644
--- a/arch/arm/lib/barebox.lds.S
+++ b/arch/arm/lib/barebox.lds.S
@@ -39,6 +39,8 @@ SECTIONS
_stext = .;
_text = .;
*(.text_entry*)
+ __ll_return = .;
+ *(.text_ll_return*)
#ifdef CONFIG_ARCH_EP93XX
/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
. = 0x1000;
--
1.7.7.3
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 9/9] ARM: Allow to compile in thumb-2 mode
2011-12-17 14:52 Thumb-2 support Sascha Hauer
` (7 preceding siblings ...)
2011-12-17 14:52 ` [PATCH 8/9] ARM: get runtime offset of board_init_lowlevel_return by using separate section Sascha Hauer
@ 2011-12-17 14:52 ` Sascha Hauer
8 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2011-12-17 14:52 UTC (permalink / raw)
To: barebox
This shrinks the resulting binary size by ~25%. Exceptions
are still handled in arm mode, so we have to explicitely
put .arm directives into the exception code. Thumb-2 mode
has been tested on i.MX51 Babbage board.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/Kconfig | 12 ++++++++++++
arch/arm/Makefile | 11 +++++++++--
arch/arm/cpu/cpu.c | 27 +++++++++++++++++++++++++++
arch/arm/cpu/exceptions.S | 1 +
arch/arm/cpu/start.c | 26 ++++++++++++++++++--------
arch/arm/include/asm/barebox-arm-head.h | 12 ++++++++++++
arch/arm/include/asm/unified.h | 8 ++++----
arch/arm/lib/armlinux.c | 16 +++++++++++++++-
commands/go.c | 6 +++++-
common/misc.c | 3 +++
include/common.h | 6 ++++++
11 files changed, 112 insertions(+), 16 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 40677a3..4ad10fe 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -100,6 +100,18 @@ config AEABI
To use this you need GCC version 4.0.0 or later.
+config THUMB2_BAREBOX
+ select ARM_ASM_UNIFIED
+ depends on CPU_V7
+ bool "Compile barebox in thumb-2 mode (read help)"
+ help
+ This enables compilation of barebox in thumb-2 mode which generates
+ ~25% smaller binaries. Arm Assembly code needs some fixups to be able
+ to work correctly in thumb-2 mode. the barebox core should have these
+ fixups since most assembly code is derived from the Kernel. However,
+ your board lowlevel init code may break in thumb-2 mode. You have been
+ warned.
+
endmenu
menu "Arm specific settings "
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index a3e12e6..edb1a0d 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -39,8 +39,15 @@ ifeq ($(CONFIG_ARM_UNWIND),y)
CFLAGS_ABI +=-funwind-tables
endif
-CPPFLAGS += $(CFLAGS_ABI) $(arch-y) $(tune-y) -msoft-float
-AFLAGS += -include asm/unified.h -msoft-float
+ifeq ($(CONFIG_THUMB2_BAREBOX),y)
+AFLAGS_AUTOIT :=$(call as-option,-Wa$(comma)-mimplicit-it=always,-Wa$(comma)-mauto-it)
+AFLAGS_NOWARN :=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W)
+CFLAGS_THUMB2 :=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN)
+AFLAGS_THUMB2 :=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb
+endif
+
+CPPFLAGS += $(CFLAGS_ABI) $(arch-y) $(tune-y) -msoft-float $(CFLAGS_THUMB2)
+AFLAGS += -include asm/unified.h -msoft-float $(AFLAGS_THUMB2)
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index 14bb6d1..a7b55d4 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -26,6 +26,7 @@
*/
#include <common.h>
+#include <init.h>
#include <command.h>
#include <cache.h>
#include <asm/mmu.h>
@@ -89,3 +90,29 @@ void arch_shutdown(void)
);
#endif
}
+
+#ifdef CONFIG_THUMB2_BAREBOX
+static void thumb2_execute(void *func, int argc, char *argv[])
+{
+ /*
+ * Switch back to arm mode before executing external
+ * programs.
+ */
+ __asm__ __volatile__ (
+ "mov r0, #0\n"
+ "mov r1, %0\n"
+ "mov r2, %1\n"
+ "bx %2\n"
+ :
+ : "r" (argc - 1), "r" (&argv[1]), "r" (func)
+ : "r0", "r1", "r2"
+ );
+}
+
+static int execute_init(void)
+{
+ do_execute = thumb2_execute;
+ return 0;
+}
+postcore_initcall(execute_init);
+#endif
diff --git a/arch/arm/cpu/exceptions.S b/arch/arm/cpu/exceptions.S
index 6f35d40..c08537a 100644
--- a/arch/arm/cpu/exceptions.S
+++ b/arch/arm/cpu/exceptions.S
@@ -106,6 +106,7 @@ _STACK_START:
* exception handlers
*/
.section ".text","ax"
+ .arm
.align 5
.globl undefined_instruction
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index 1f4fdd2..ff0081a 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -33,26 +33,36 @@ void __naked __section(.text_entry) start(void)
barebox_arm_head();
}
+#ifdef CONFIG_THUMB2_BAREBOX
+#define STOP \
+ "1: bne 1b\n" \
+ "nop\n"
+#else
+#define STOP \
+ "1: bne 1b\n"
+#endif
+
void __naked __section(.text_exceptions) exception_vectors(void)
{
__asm__ __volatile__ (
+ ".arm\n"
"b reset\n" /* reset */
#ifdef CONFIG_ARM_EXCEPTIONS
"ldr pc, =undefined_instruction\n" /* undefined instruction */
"ldr pc, =software_interrupt\n" /* software interrupt (SWI) */
"ldr pc, =prefetch_abort\n" /* prefetch abort */
"ldr pc, =data_abort\n" /* data abort */
- "1: bne 1b\n" /* (reserved) */
+ STOP /* (reserved) */
"ldr pc, =irq\n" /* irq (interrupt) */
"ldr pc, =fiq\n" /* fiq (fast interrupt) */
#else
- "1: bne 1b\n" /* undefined instruction */
- "1: bne 1b\n" /* software interrupt (SWI) */
- "1: bne 1b\n" /* prefetch abort */
- "1: bne 1b\n" /* data abort */
- "1: bne 1b\n" /* (reserved) */
- "1: bne 1b\n" /* irq (interrupt) */
- "1: bne 1b\n" /* fiq (fast interrupt) */
+ STOP /* undefined instruction */
+ STOP /* software interrupt (SWI) */
+ STOP /* prefetch abort */
+ STOP /* data abort */
+ STOP /* (reserved) */
+ STOP /* irq (interrupt) */
+ STOP /* fiq (fast interrupt) */
#endif
);
}
diff --git a/arch/arm/include/asm/barebox-arm-head.h b/arch/arm/include/asm/barebox-arm-head.h
index ec4a68c..dc0acb1 100644
--- a/arch/arm/include/asm/barebox-arm-head.h
+++ b/arch/arm/include/asm/barebox-arm-head.h
@@ -2,10 +2,22 @@
static inline void barebox_arm_head(void)
{
__asm__ __volatile__ (
+#ifdef CONFIG_THUMB2_BAREBOX
+ ".arm\n"
+ "adr r9, 1f + 1\n"
+ "bx r9\n"
+ ".thumb\n"
+ "1:\n"
+ "bl reset\n"
+ ".rept 10\n"
+ "nop\n"
+ ".endr\n"
+#else
"b reset\n"
".rept 7\n"
".word 0x0\n"
".endr\n"
+#endif
".word 0x65726162\n" /* 'bare' */
".word 0x00786f62\n" /* 'box' */
".word _text\n" /* text base. If copied there,
diff --git a/arch/arm/include/asm/unified.h b/arch/arm/include/asm/unified.h
index bc63116..4d855c8 100644
--- a/arch/arm/include/asm/unified.h
+++ b/arch/arm/include/asm/unified.h
@@ -24,10 +24,10 @@
.syntax unified
#endif
-#ifdef CONFIG_THUMB2_KERNEL
+#ifdef CONFIG_THUMB2_BAREBOX
#if __GNUC__ < 4
-#error Thumb-2 kernel requires gcc >= 4
+#error Thumb-2 barebox requires gcc >= 4
#endif
/* The CPSR bit describing the instruction set (Thumb) */
@@ -40,7 +40,7 @@
#endif
#define BSYM(sym) sym + 1
-#else /* !CONFIG_THUMB2_KERNEL */
+#else /* !CONFIG_THUMB2_BAREBOX */
/* The CPSR bit describing the instruction set (ARM) */
#define PSR_ISETSTATE 0
@@ -52,7 +52,7 @@
#endif
#define BSYM(sym) sym
-#endif /* CONFIG_THUMB2_KERNEL */
+#endif /* CONFIG_THUMB2_BAREBOX */
#ifndef CONFIG_ARM_ASM_UNIFIED
diff --git a/arch/arm/lib/armlinux.c b/arch/arm/lib/armlinux.c
index bd9b72a..3fafb4b 100644
--- a/arch/arm/lib/armlinux.c
+++ b/arch/arm/lib/armlinux.c
@@ -253,6 +253,8 @@ void start_linux(void *adr, int swap, struct image_data *data)
{
void (*kernel)(int zero, int arch, void *params) = adr;
void *params = NULL;
+ int architecture = armlinux_get_architecture();
+
#ifdef CONFIG_OFTREE
params = of_get_fixed_tree();
if (params)
@@ -271,5 +273,17 @@ void start_linux(void *adr, int swap, struct image_data *data)
__asm__ __volatile__("mcr p15, 0, %0, c1, c0" :: "r" (reg));
}
- kernel(0, armlinux_get_architecture(), params);
+#ifdef CONFIG_THUMB2_BAREBOX
+ __asm__ __volatile__ (
+ "mov r0, #0\n"
+ "mov r1, %0\n"
+ "mov r2, %1\n"
+ "bx %2\n"
+ :
+ : "r" (architecture), "r" (params), "r" (kernel)
+ : "r0", "r1", "r2"
+ );
+#else
+ kernel(0, architecture, params);
+#endif
}
diff --git a/commands/go.c b/commands/go.c
index 6082fe5..bc984c8 100644
--- a/commands/go.c
+++ b/commands/go.c
@@ -62,7 +62,11 @@ static int do_go(struct command *cmdtp, int argc, char *argv[])
func = addr;
shutdown_barebox();
- func(argc - 1, &argv[1]);
+
+ if (do_execute)
+ do_execute(func, argc - 1, &argv[1]);
+ else
+ func(argc - 1, &argv[1]);
/*
* The application returned. Since we have shutdown barebox and
diff --git a/common/misc.c b/common/misc.c
index 7edf536..9263f4a 100644
--- a/common/misc.c
+++ b/common/misc.c
@@ -125,3 +125,6 @@ void perror(const char *s)
#endif
}
EXPORT_SYMBOL(perror);
+
+void (*do_execute)(void *func, int argc, char *argv[]);
+EXPORT_SYMBOL(do_execute);
diff --git a/include/common.h b/include/common.h
index 2f37dd8..aa84539 100644
--- a/include/common.h
+++ b/include/common.h
@@ -137,6 +137,12 @@ unsigned long strtoul_suffix(const char *str, char **endp, int base);
void start_barebox(void);
void shutdown_barebox(void);
+/*
+ * architectures which have special calling conventions for
+ * executing programs should set this. Used by the 'go' command
+ */
+extern void (*do_execute)(void *func, int argc, char *argv[]);
+
void arch_shutdown(void);
int run_shell(void);
--
1.7.7.3
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 1/9] ARM i.MX5: prepare to add a imx51_lowlevel_init
2011-12-17 14:52 ` [PATCH 1/9] ARM i.MX5: prepare to add a imx51_lowlevel_init Sascha Hauer
@ 2011-12-18 14:03 ` Eric Bénard
2011-12-19 10:18 ` Sascha Hauer
1 sibling, 0 replies; 20+ messages in thread
From: Eric Bénard @ 2011-12-18 14:03 UTC (permalink / raw)
To: barebox
Hi Sascha,
Le 17/12/2011 15:52, Sascha Hauer a écrit :
> - move code which can be shared between i.MX53 and i.MX51
> to a common file
> - rename mx53_init_lowlevel to imx53_init_lowlevel
>
> Signed-off-by: Sascha Hauer<s.hauer@pengutronix.de>
> ---
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index 0b3b781..a9aa9e2 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -5,8 +5,8 @@ obj-$(CONFIG_ARCH_IMX21) += speed-imx21.o imx21.o iomux-v1.o
> obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o
> obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o
> obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o
> -obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o
> -obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o
> +obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o imx5.o
> +obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o imx5.o
> obj-$(CONFIG_IMX_CLKO) += clko.o
> obj-$(CONFIG_IMX_IIM) += iim.o
> obj-$(CONFIG_NAND_IMX) += nand.o
imx5.c is missing leading to :
make[1]: *** No rule to make target `arch/arm/mach-imx/imx5.o', needed by
`arch/arm/mach-imx/built-in.o'. Stop.
make: *** [arch/arm/mach-imx] Error 2
Eric
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 7/9] ARM: move exception vectors away from start of binary
2011-12-17 14:52 ` [PATCH 7/9] ARM: move exception vectors away from start of binary Sascha Hauer
@ 2011-12-18 23:43 ` Peter Korsgaard
2011-12-20 14:07 ` Jean-Christophe PLAGNIOL-VILLARD
2012-01-01 4:37 ` Jean-Christophe PLAGNIOL-VILLARD
2 siblings, 0 replies; 20+ messages in thread
From: Peter Korsgaard @ 2011-12-18 23:43 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
>>>>> "Sascha" == Sascha Hauer <s.hauer@pengutronix.de> writes:
Sascha> those images can now also be detected aas barebox images.
s/aas/as/
--
Bye, Peter Korsgaard
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 1/9] ARM i.MX5: prepare to add a imx51_lowlevel_init
2011-12-17 14:52 ` [PATCH 1/9] ARM i.MX5: prepare to add a imx51_lowlevel_init Sascha Hauer
2011-12-18 14:03 ` Eric Bénard
@ 2011-12-19 10:18 ` Sascha Hauer
1 sibling, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2011-12-19 10:18 UTC (permalink / raw)
To: barebox
Here is an updated version, with imx5.c added this time.
Sascha
8<----------------------------------------------------
ARM i.MX5: prepare to add a imx51_lowlevel_init
- move code which can be shared between i.MX53 and i.MX51
to a common file
- rename mx53_init_lowlevel to imx53_init_lowlevel
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/freescale-mx53-loco/board.c | 2 +-
arch/arm/boards/freescale-mx53-smd/board.c | 2 +-
arch/arm/mach-imx/Makefile | 2 +-
arch/arm/mach-imx/imx5.c | 58 +++++++++++++++++++++++++
arch/arm/mach-imx/imx53.c | 61 +++-----------------------
arch/arm/mach-imx/include/mach/imx5.h | 8 ++++
arch/arm/mach-imx/include/mach/imx53.h | 6 ---
7 files changed, 76 insertions(+), 63 deletions(-)
create mode 100644 arch/arm/mach-imx/imx5.c
create mode 100644 arch/arm/mach-imx/include/mach/imx5.h
delete mode 100644 arch/arm/mach-imx/include/mach/imx53.h
diff --git a/arch/arm/boards/freescale-mx53-loco/board.c b/arch/arm/boards/freescale-mx53-loco/board.c
index aec2254..8d1cbf5 100644
--- a/arch/arm/boards/freescale-mx53-loco/board.c
+++ b/arch/arm/boards/freescale-mx53-loco/board.c
@@ -34,7 +34,7 @@
#include <mach/gpio.h>
#include <mach/imx-nand.h>
#include <mach/iim.h>
-#include <mach/imx53.h>
+#include <mach/imx5.h>
#include <asm/armlinux.h>
#include <io.h>
diff --git a/arch/arm/boards/freescale-mx53-smd/board.c b/arch/arm/boards/freescale-mx53-smd/board.c
index 325458e..d14c1f2 100644
--- a/arch/arm/boards/freescale-mx53-smd/board.c
+++ b/arch/arm/boards/freescale-mx53-smd/board.c
@@ -34,7 +34,7 @@
#include <mach/gpio.h>
#include <mach/imx-nand.h>
#include <mach/iim.h>
-#include <mach/imx53.h>
+#include <mach/imx5.h>
#include <asm/armlinux.h>
#include <io.h>
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 0b3b781..38de346 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -6,7 +6,7 @@ obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o
obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o
obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o
obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o
-obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o
+obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o imx5.o
obj-$(CONFIG_IMX_CLKO) += clko.o
obj-$(CONFIG_IMX_IIM) += iim.o
obj-$(CONFIG_NAND_IMX) += nand.o
diff --git a/arch/arm/mach-imx/imx5.c b/arch/arm/mach-imx/imx5.c
new file mode 100644
index 0000000..9ec78b2
--- /dev/null
+++ b/arch/arm/mach-imx/imx5.c
@@ -0,0 +1,58 @@
+#include <common.h>
+#include <io.h>
+#include <sizes.h>
+#include <mach/imx5.h>
+#include <mach/clock-imx51_53.h>
+
+void imx5_setup_pll(void __iomem *base, int freq, u32 op, u32 mfd, u32 mfn)
+{
+ u32 r;
+
+ /*
+ * If freq < 300MHz, we need to set dpdck0_2_en to 0
+ */
+ r = 0x00000232;
+ if (freq >= 300)
+ r |= 0x1000;
+
+ writel(r, base + MX5_PLL_DP_CTL);
+
+ writel(0x2, base + MX5_PLL_DP_CONFIG);
+
+ writel(op, base + MX5_PLL_DP_OP);
+ writel(op, base + MX5_PLL_DP_HFS_OP);
+
+ writel(mfd, base + MX5_PLL_DP_MFD);
+ writel(mfd, base + MX5_PLL_DP_HFS_MFD);
+
+ writel(mfn, base + MX5_PLL_DP_MFN);
+ writel(mfn, base + MX5_PLL_DP_HFS_MFN);
+
+ writel(0x00001232, base + MX5_PLL_DP_CTL);
+
+ while (!(readl(base + MX5_PLL_DP_CTL) & 1));
+}
+
+void imx5_init_lowlevel(void)
+{
+ u32 r;
+
+ /* ARM errata ID #468414 */
+ __asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r));
+ r |= (1 << 5); /* enable L1NEON bit */
+ r &= ~(1 << 1); /* explicitly disable L2 cache */
+ __asm__ __volatile__("mcr 15, 0, %0, c1, c0, 1" : : "r"(r));
+
+ /* reconfigure L2 cache aux control reg */
+ r = 0xc0 | /* tag RAM */
+ 0x4 | /* data RAM */
+ (1 << 24) | /* disable write allocate delay */
+ (1 << 23) | /* disable write allocate combine */
+ (1 << 22); /* disable write allocate */
+
+ __asm__ __volatile__("mcr 15, 1, %0, c9, c0, 2" : : "r"(r));
+
+ __asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r));
+ r |= 1 << 1; /* enable L2 cache */
+ __asm__ __volatile__("mcr 15, 0, %0, c1, c0, 1" : : "r"(r));
+}
diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c
index 64bec86..2fb18e7 100644
--- a/arch/arm/mach-imx/imx53.c
+++ b/arch/arm/mach-imx/imx53.c
@@ -19,6 +19,7 @@
#include <common.h>
#include <io.h>
#include <sizes.h>
+#include <mach/imx5.h>
#include <mach/imx53-regs.h>
#include <mach/clock-imx51_53.h>
@@ -45,63 +46,17 @@ static int imx53_init(void)
}
coredevice_initcall(imx53_init);
-static void setup_pll(void __iomem *base, int freq, u32 op, u32 mfd, u32 mfn)
-{
- u32 r;
-
- /*
- * If freq < 300MHz, we need to set dpdck0_2_en to 0
- */
- r = 0x00000232;
- if (freq >= 300)
- r |= 0x1000;
-
- writel(r, base + MX5_PLL_DP_CTL);
-
- writel(0x2, base + MX5_PLL_DP_CONFIG);
-
- writel(op, base + MX5_PLL_DP_OP);
- writel(op, base + MX5_PLL_DP_HFS_OP);
-
- writel(mfd, base + MX5_PLL_DP_MFD);
- writel(mfd, base + MX5_PLL_DP_HFS_MFD);
-
- writel(mfn, base + MX5_PLL_DP_MFN);
- writel(mfn, base + MX5_PLL_DP_HFS_MFN);
+#define setup_pll_1000(base) imx5_setup_pll((base), 1000, ((10 << 4) + ((1 - 1) << 0)), (12 - 1), 5)
+#define setup_pll_400(base) imx5_setup_pll((base), 400, ((8 << 4) + ((2 - 1) << 0)), (3 - 1), 1)
+#define setup_pll_455(base) imx5_setup_pll((base), 455, ((9 << 4) + ((2 - 1) << 0)), (48 - 1), 23)
+#define setup_pll_216(base) imx5_setup_pll((base), 216, ((8 << 4) + ((2 - 1) << 0)), (1 - 1), 1)
- writel(0x00001232, base + MX5_PLL_DP_CTL);
-
- while (!(readl(base + MX5_PLL_DP_CTL) & 1));
-}
-
-#define setup_pll_1000(base) setup_pll((base), 1000, ((10 << 4) + ((1 - 1) << 0)), (12 - 1), 5)
-#define setup_pll_400(base) setup_pll((base), 400, ((8 << 4) + ((2 - 1) << 0)), (3 - 1), 1)
-#define setup_pll_455(base) setup_pll((base), 455, ((9 << 4) + ((2 - 1) << 0)), (48 - 1), 23)
-#define setup_pll_216(base) setup_pll((base), 216, ((8 << 4) + ((2 - 1) << 0)), (1 - 1), 1)
-
-int mx53_init_lowlevel(void)
+void imx53_init_lowlevel(void)
{
void __iomem *ccm = (void __iomem *)MX53_CCM_BASE_ADDR;
u32 r;
- /* ARM errata ID #468414 */
- __asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r));
- r |= (1 << 5); /* enable L1NEON bit */
- r &= ~(1 << 1); /* explicitly disable L2 cache */
- __asm__ __volatile__("mcr 15, 0, %0, c1, c0, 1" : : "r"(r));
-
- /* reconfigure L2 cache aux control reg */
- r = 0xc0 | /* tag RAM */
- 0x4 | /* data RAM */
- (1 << 24) | /* disable write allocate delay */
- (1 << 23) | /* disable write allocate combine */
- (1 << 22); /* disable write allocate */
-
- __asm__ __volatile__("mcr 15, 1, %0, c9, c0, 2" : : "r"(r));
-
- __asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r));
- r |= 1 << 1; /* enable L2 cache */
- __asm__ __volatile__("mcr 15, 0, %0, c1, c0, 1" : : "r"(r));
+ imx5_init_lowlevel();
/*
* AIPS setup - Only setup MPROTx registers.
@@ -195,6 +150,4 @@ int mx53_init_lowlevel(void)
writel(0xffffffff, ccm + MX53_CCM_CCGR7);
writel(0, ccm + MX5_CCM_CCDR);
-
- return 0;
}
diff --git a/arch/arm/mach-imx/include/mach/imx5.h b/arch/arm/mach-imx/include/mach/imx5.h
new file mode 100644
index 0000000..d034082
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx5.h
@@ -0,0 +1,8 @@
+#ifndef __MACH_MX5_H
+#define __MACH_MX5_H
+
+void imx53_init_lowlevel(void);
+void imx5_setup_pll(void __iomem *base, int freq, u32 op, u32 mfd, u32 mfn);
+void imx5_init_lowlevel(void);
+
+#endif /* __MACH_MX53_H */
diff --git a/arch/arm/mach-imx/include/mach/imx53.h b/arch/arm/mach-imx/include/mach/imx53.h
deleted file mode 100644
index b1f30d3..0000000
--- a/arch/arm/mach-imx/include/mach/imx53.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __MACH_MX53_H
-#define __MACH_MX53_H
-
-int mx53_init_lowlevel(void);
-
-#endif /* __MACH_MX53_H */
--
1.7.7.3
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 7/9] ARM: move exception vectors away from start of binary
2011-12-17 14:52 ` [PATCH 7/9] ARM: move exception vectors away from start of binary Sascha Hauer
2011-12-18 23:43 ` Peter Korsgaard
@ 2011-12-20 14:07 ` Jean-Christophe PLAGNIOL-VILLARD
2011-12-21 10:09 ` Sascha Hauer
2012-01-01 4:37 ` Jean-Christophe PLAGNIOL-VILLARD
2 siblings, 1 reply; 20+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2011-12-20 14:07 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 15:52 Sat 17 Dec , Sascha Hauer wrote:
> Traditionally U-Boot and barebox have the exception vectors at
> the start of the binary. There is no real reason in doing so,
> because in the majority of cases this data will not be at 0x0
> where it could be used as vectors directly anyway.
> This patch puts the vectors into a separate linker section and
> defines an head function which is placed at the start of the
> image instead. Putting this in a separate function also has
> the advantage that it can be placed at the start of images
> which require an additional header like several Freescale i.MX
> images. As the head function contains the barebox arm magic
> those images can now also be detected aas barebox images.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c | 3 ++-
> arch/arm/boards/eukrea_cpuimx35/flash_header.c | 3 ++-
> arch/arm/boards/eukrea_cpuimx51/flash_header.c | 3 ++-
> arch/arm/boards/freescale-mx25-3-stack/3stack.c | 3 ++-
> .../boards/freescale-mx35-3-stack/flash_header.c | 3 ++-
> arch/arm/boards/freescale-mx51-pdk/flash_header.c | 3 ++-
> arch/arm/boards/freescale-mx53-loco/flash_header.c | 3 ++-
> arch/arm/boards/freescale-mx53-smd/flash_header.c | 3 ++-
> arch/arm/cpu/mmu.c | 4 ++--
> arch/arm/cpu/start.c | 14 +++++++-------
> arch/arm/include/asm/barebox-arm-head.h | 17 +++++++++++++++++
> arch/arm/include/asm/barebox-arm.h | 2 ++
> arch/arm/lib/barebox.lds.S | 5 ++++-
> 13 files changed, 48 insertions(+), 18 deletions(-)
> create mode 100644 arch/arm/include/asm/barebox-arm-head.h
you need to update the rm9200 too
Best Regards,
J.
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 7/9] ARM: move exception vectors away from start of binary
2011-12-20 14:07 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2011-12-21 10:09 ` Sascha Hauer
0 siblings, 0 replies; 20+ messages in thread
From: Sascha Hauer @ 2011-12-21 10:09 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
On Tue, Dec 20, 2011 at 03:07:45PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 15:52 Sat 17 Dec , Sascha Hauer wrote:
> > Traditionally U-Boot and barebox have the exception vectors at
> > the start of the binary. There is no real reason in doing so,
> > because in the majority of cases this data will not be at 0x0
> > where it could be used as vectors directly anyway.
> > This patch puts the vectors into a separate linker section and
> > defines an head function which is placed at the start of the
> > image instead. Putting this in a separate function also has
> > the advantage that it can be placed at the start of images
> > which require an additional header like several Freescale i.MX
> > images. As the head function contains the barebox arm magic
> > those images can now also be detected aas barebox images.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> > arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c | 3 ++-
> > arch/arm/boards/eukrea_cpuimx35/flash_header.c | 3 ++-
> > arch/arm/boards/eukrea_cpuimx51/flash_header.c | 3 ++-
> > arch/arm/boards/freescale-mx25-3-stack/3stack.c | 3 ++-
> > .../boards/freescale-mx35-3-stack/flash_header.c | 3 ++-
> > arch/arm/boards/freescale-mx51-pdk/flash_header.c | 3 ++-
> > arch/arm/boards/freescale-mx53-loco/flash_header.c | 3 ++-
> > arch/arm/boards/freescale-mx53-smd/flash_header.c | 3 ++-
> > arch/arm/cpu/mmu.c | 4 ++--
> > arch/arm/cpu/start.c | 14 +++++++-------
> > arch/arm/include/asm/barebox-arm-head.h | 17 +++++++++++++++++
> > arch/arm/include/asm/barebox-arm.h | 2 ++
> > arch/arm/lib/barebox.lds.S | 5 ++++-
> > 13 files changed, 48 insertions(+), 18 deletions(-)
> > create mode 100644 arch/arm/include/asm/barebox-arm-head.h
> you need to update the rm9200 too
Only the boards which define some non standard entry header need an
update. The rm9200 does not seem to be one of these boards, or am
I missing something?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 7/9] ARM: move exception vectors away from start of binary
2011-12-17 14:52 ` [PATCH 7/9] ARM: move exception vectors away from start of binary Sascha Hauer
2011-12-18 23:43 ` Peter Korsgaard
2011-12-20 14:07 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2012-01-01 4:37 ` Jean-Christophe PLAGNIOL-VILLARD
2012-01-02 14:13 ` Sascha Hauer
2 siblings, 1 reply; 20+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-01-01 4:37 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 15:52 Sat 17 Dec , Sascha Hauer wrote:
> Traditionally U-Boot and barebox have the exception vectors at
> the start of the binary. There is no real reason in doing so,
> because in the majority of cases this data will not be at 0x0
> where it could be used as vectors directly anyway.
> This patch puts the vectors into a separate linker section and
> defines an head function which is placed at the start of the
> image instead. Putting this in a separate function also has
> the advantage that it can be placed at the start of images
> which require an additional header like several Freescale i.MX
> images. As the head function contains the barebox arm magic
> those images can now also be detected aas barebox images.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
I've to make it optionnal as on AT91 for boot we must have it at the bigeniing
of the binary
Best Regards,
J.
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 7/9] ARM: move exception vectors away from start of binary
2012-01-01 4:37 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2012-01-02 14:13 ` Sascha Hauer
2012-01-02 15:09 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 20+ messages in thread
From: Sascha Hauer @ 2012-01-02 14:13 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
On Sun, Jan 01, 2012 at 05:37:17AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 15:52 Sat 17 Dec , Sascha Hauer wrote:
> > Traditionally U-Boot and barebox have the exception vectors at
> > the start of the binary. There is no real reason in doing so,
> > because in the majority of cases this data will not be at 0x0
> > where it could be used as vectors directly anyway.
> > This patch puts the vectors into a separate linker section and
> > defines an head function which is placed at the start of the
> > image instead. Putting this in a separate function also has
> > the advantage that it can be placed at the start of images
> > which require an additional header like several Freescale i.MX
> > images. As the head function contains the barebox arm magic
> > those images can now also be detected aas barebox images.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> I've to make it optionnal as on AT91 for boot we must have it at the bigeniing
> of the binary
Instead of this:
"b reset\n"
".rept 7\n"
".word 0x0\n"
".endr\n"
we could do this:
"b reset\n"
".rept 7\n"
"1: b 1b\n"
".endr\n"
This looks like a exception vector table for the at91 bootloader. BTW
I just looked at a at91 datasheet and at least on the at91sam9260 the
sixth vector should contain the image size to copy. So maybe this does
not work on at91 anyway?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 7/9] ARM: move exception vectors away from start of binary
2012-01-02 14:13 ` Sascha Hauer
@ 2012-01-02 15:09 ` Jean-Christophe PLAGNIOL-VILLARD
2012-01-23 12:07 ` Sascha Hauer
0 siblings, 1 reply; 20+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-01-02 15:09 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 15:13 Mon 02 Jan , Sascha Hauer wrote:
> On Sun, Jan 01, 2012 at 05:37:17AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 15:52 Sat 17 Dec , Sascha Hauer wrote:
> > > Traditionally U-Boot and barebox have the exception vectors at
> > > the start of the binary. There is no real reason in doing so,
> > > because in the majority of cases this data will not be at 0x0
> > > where it could be used as vectors directly anyway.
> > > This patch puts the vectors into a separate linker section and
> > > defines an head function which is placed at the start of the
> > > image instead. Putting this in a separate function also has
> > > the advantage that it can be placed at the start of images
> > > which require an additional header like several Freescale i.MX
> > > images. As the head function contains the barebox arm magic
> > > those images can now also be detected aas barebox images.
> > >
> > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > ---
> > I've to make it optionnal as on AT91 for boot we must have it at the bigeniing
> > of the binary
>
> Instead of this:
>
> "b reset\n"
> ".rept 7\n"
> ".word 0x0\n"
> ".endr\n"
>
> we could do this:
>
> "b reset\n"
> ".rept 7\n"
> "1: b 1b\n"
> ".endr\n"
>
> This looks like a exception vector table for the at91 bootloader. BTW
> I just looked at a at91 datasheet and at least on the at91sam9260 the
> sixth vector should contain the image size to copy. So maybe this does
> not work on at91 anyway?
I'm working on it so please hold on this
Best Regards,
J.
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barebox@lists.infradead.org
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 7/9] ARM: move exception vectors away from start of binary
2012-01-02 15:09 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2012-01-23 12:07 ` Sascha Hauer
2012-01-24 4:39 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 20+ messages in thread
From: Sascha Hauer @ 2012-01-23 12:07 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
On Mon, Jan 02, 2012 at 04:09:01PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 15:13 Mon 02 Jan , Sascha Hauer wrote:
> > On Sun, Jan 01, 2012 at 05:37:17AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > On 15:52 Sat 17 Dec , Sascha Hauer wrote:
> > > > Traditionally U-Boot and barebox have the exception vectors at
> > > > the start of the binary. There is no real reason in doing so,
> > > > because in the majority of cases this data will not be at 0x0
> > > > where it could be used as vectors directly anyway.
> > > > This patch puts the vectors into a separate linker section and
> > > > defines an head function which is placed at the start of the
> > > > image instead. Putting this in a separate function also has
> > > > the advantage that it can be placed at the start of images
> > > > which require an additional header like several Freescale i.MX
> > > > images. As the head function contains the barebox arm magic
> > > > those images can now also be detected aas barebox images.
> > > >
> > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > > ---
> > > I've to make it optionnal as on AT91 for boot we must have it at the bigeniing
> > > of the binary
> >
> > Instead of this:
> >
> > "b reset\n"
> > ".rept 7\n"
> > ".word 0x0\n"
> > ".endr\n"
> >
> > we could do this:
> >
> > "b reset\n"
> > ".rept 7\n"
> > "1: b 1b\n"
> > ".endr\n"
> >
> > This looks like a exception vector table for the at91 bootloader. BTW
> > I just looked at a at91 datasheet and at least on the at91sam9260 the
> > sixth vector should contain the image size to copy. So maybe this does
> > not work on at91 anyway?
> I'm working on it so please hold on this
ping. I'd really like to merge the remaining thumb2 support pieces.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 7/9] ARM: move exception vectors away from start of binary
2012-01-23 12:07 ` Sascha Hauer
@ 2012-01-24 4:39 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 20+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-01-24 4:39 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 13:07 Mon 23 Jan , Sascha Hauer wrote:
> On Mon, Jan 02, 2012 at 04:09:01PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 15:13 Mon 02 Jan , Sascha Hauer wrote:
> > > On Sun, Jan 01, 2012 at 05:37:17AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > > On 15:52 Sat 17 Dec , Sascha Hauer wrote:
> > > > > Traditionally U-Boot and barebox have the exception vectors at
> > > > > the start of the binary. There is no real reason in doing so,
> > > > > because in the majority of cases this data will not be at 0x0
> > > > > where it could be used as vectors directly anyway.
> > > > > This patch puts the vectors into a separate linker section and
> > > > > defines an head function which is placed at the start of the
> > > > > image instead. Putting this in a separate function also has
> > > > > the advantage that it can be placed at the start of images
> > > > > which require an additional header like several Freescale i.MX
> > > > > images. As the head function contains the barebox arm magic
> > > > > those images can now also be detected aas barebox images.
> > > > >
> > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > > > ---
> > > > I've to make it optionnal as on AT91 for boot we must have it at the bigeniing
> > > > of the binary
> > >
> > > Instead of this:
> > >
> > > "b reset\n"
> > > ".rept 7\n"
> > > ".word 0x0\n"
> > > ".endr\n"
> > >
> > > we could do this:
> > >
> > > "b reset\n"
> > > ".rept 7\n"
> > > "1: b 1b\n"
> > > ".endr\n"
> > >
> > > This looks like a exception vector table for the at91 bootloader. BTW
> > > I just looked at a at91 datasheet and at least on the at91sam9260 the
> > > sixth vector should contain the image size to copy. So maybe this does
> > > not work on at91 anyway?
> > I'm working on it so please hold on this
>
> ping. I'd really like to merge the remaining thumb2 support pieces.
I've issue on it
I try to send a version this week sorry but here its chinese new year
Best Regards,
J.
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^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2012-01-24 4:42 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-12-17 14:52 Thumb-2 support Sascha Hauer
2011-12-17 14:52 ` [PATCH 1/9] ARM i.MX5: prepare to add a imx51_lowlevel_init Sascha Hauer
2011-12-18 14:03 ` Eric Bénard
2011-12-19 10:18 ` Sascha Hauer
2011-12-17 14:52 ` [PATCH 2/9] ARM i.MX51: implement " Sascha Hauer
2011-12-17 14:52 ` [PATCH 3/9] ARM i.MX51 babbage: use generic lowlevel init function Sascha Hauer
2011-12-17 14:52 ` [PATCH 4/9] ARM eukrea i.MX51: use generic lowlevel init Sascha Hauer
2011-12-17 14:52 ` [PATCH 5/9] ARM: update string functions from Linux Kernel Sascha Hauer
2011-12-17 14:52 ` [PATCH 6/9] ARM cache-armv7: use thumb-2 instructions where necessary Sascha Hauer
2011-12-17 14:52 ` [PATCH 7/9] ARM: move exception vectors away from start of binary Sascha Hauer
2011-12-18 23:43 ` Peter Korsgaard
2011-12-20 14:07 ` Jean-Christophe PLAGNIOL-VILLARD
2011-12-21 10:09 ` Sascha Hauer
2012-01-01 4:37 ` Jean-Christophe PLAGNIOL-VILLARD
2012-01-02 14:13 ` Sascha Hauer
2012-01-02 15:09 ` Jean-Christophe PLAGNIOL-VILLARD
2012-01-23 12:07 ` Sascha Hauer
2012-01-24 4:39 ` Jean-Christophe PLAGNIOL-VILLARD
2011-12-17 14:52 ` [PATCH 8/9] ARM: get runtime offset of board_init_lowlevel_return by using separate section Sascha Hauer
2011-12-17 14:52 ` [PATCH 9/9] ARM: Allow to compile in thumb-2 mode Sascha Hauer
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