* [PATCH 1/4] ARM __mmu_cache_*: Do not clobber registers
2012-08-12 14:30 [PATCH] ARM: enable MMU in pbl Sascha Hauer
@ 2012-08-12 14:30 ` Sascha Hauer
2012-08-12 14:30 ` [PATCH 2/4] ARM MMU: call __mmu_cache_* as regular C functions Sascha Hauer
` (3 subsequent siblings)
4 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2012-08-12 14:30 UTC (permalink / raw)
To: barebox
Save/restore the registers used in __mmu_cache_* so that they can
be called as regular C functions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/cache-armv4.S | 3 ++-
arch/arm/cpu/cache-armv7.S | 6 ++++--
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S
index 2231eee..22fab14 100644
--- a/arch/arm/cpu/cache-armv4.S
+++ b/arch/arm/cpu/cache-armv4.S
@@ -46,6 +46,7 @@ ENDPROC(__mmu_cache_off)
.section .text.__mmu_cache_flush
ENTRY(__mmu_cache_flush)
+ stmfd sp!, {r6, r11, lr}
mrc p15, 0, r6, c0, c0 @ get processor ID
mov r2, #64*1024 @ default: 32K dcache size (*2)
mov r11, #32 @ default: 32 byte line size
@@ -74,7 +75,7 @@ no_cache_id:
mcr p15, 0, r1, c7, c5, 0 @ flush I cache
mcr p15, 0, r1, c7, c6, 0 @ flush D cache
mcr p15, 0, r1, c7, c10, 4 @ drain WB
- mov pc, lr
+ ldmfd sp!, {r6, r11, pc}
ENDPROC(__mmu_cache_flush)
/*
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index 9bd7425..2eba959 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -3,6 +3,7 @@
.section .text.__mmu_cache_on
ENTRY(__mmu_cache_on)
+ stmfd sp!, {r11, lr}
mov r12, lr
#ifdef CONFIG_MMU
mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
@@ -28,7 +29,7 @@ ENTRY(__mmu_cache_on)
mrc p15, 0, r0, c1, c0, 0 @ and read it back
mov r0, #0
mcr p15, 0, r0, c7, c5, 4 @ ISB
- mov pc, r12
+ ldmfd sp!, {r11, pc}
ENDPROC(__mmu_cache_on)
.section .text.__mmu_cache_off
@@ -54,6 +55,7 @@ ENDPROC(__mmu_cache_off)
.section .text.__mmu_cache_flush
ENTRY(__mmu_cache_flush)
+ stmfd sp!, {r10, lr}
mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
mov r10, #0
@@ -111,7 +113,7 @@ iflush:
mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
mcr p15, 0, r10, c7, c10, 4 @ DSB
mcr p15, 0, r10, c7, c5, 4 @ ISB
- mov pc, lr
+ ldmfd sp!, {r10, pc}
ENDPROC(__mmu_cache_flush)
/*
--
1.7.10.4
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 2/4] ARM MMU: call __mmu_cache_* as regular C functions
2012-08-12 14:30 [PATCH] ARM: enable MMU in pbl Sascha Hauer
2012-08-12 14:30 ` [PATCH 1/4] ARM __mmu_cache_*: Do not clobber registers Sascha Hauer
@ 2012-08-12 14:30 ` Sascha Hauer
2012-08-12 14:30 ` [PATCH 3/4] ARM pbl: enable MMU during decompression Sascha Hauer
` (2 subsequent siblings)
4 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2012-08-12 14:30 UTC (permalink / raw)
To: barebox
Now that __mmu_cache_* restore the registers they can be called
as regular C functions. Create a header file for them and use
C functions rather than inline assembly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/mmu.c | 25 ++++++-------------------
arch/arm/cpu/mmu.h | 8 ++++++++
2 files changed, 14 insertions(+), 19 deletions(-)
create mode 100644 arch/arm/cpu/mmu.h
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 607f357..dad8092 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -8,6 +8,8 @@
#include <asm/system.h>
#include <memory.h>
+#include "mmu.h"
+
static unsigned long *ttb;
static void create_sections(unsigned long virt, unsigned long phys, int size_m,
@@ -21,12 +23,7 @@ static void create_sections(unsigned long virt, unsigned long phys, int size_m,
for (i = size_m; i > 0; i--, virt++, phys++)
ttb[virt] = (phys << 20) | flags;
- asm volatile (
- "bl __mmu_cache_flush;"
- :
- :
- : "r0", "r1", "r2", "r3", "r6", "r10", "r12", "lr", "cc", "memory"
- );
+ __mmu_cache_flush();
}
/*
@@ -255,12 +252,7 @@ static int mmu_init(void)
create_sections(bank->start, bank->start, bank->size >> 20,
PMD_SECT_DEF_CACHED);
- asm volatile (
- "bl __mmu_cache_on;"
- :
- :
- : "r0", "r1", "r2", "r3", "r6", "r10", "r12", "lr", "cc", "memory"
- );
+ __mmu_cache_on();
/*
* Now that we have the MMU and caches on remap sdram again using
@@ -284,13 +276,8 @@ void mmu_disable(void)
if (outer_cache.disable)
outer_cache.disable();
- asm volatile (
- "bl __mmu_cache_flush;"
- "bl __mmu_cache_off;"
- :
- :
- : "r0", "r1", "r2", "r3", "r6", "r10", "r12", "lr", "cc", "memory"
- );
+ __mmu_cache_flush();
+ __mmu_cache_off();
}
#define PAGE_ALIGN(s) ((s) + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
diff --git a/arch/arm/cpu/mmu.h b/arch/arm/cpu/mmu.h
new file mode 100644
index 0000000..618968b
--- /dev/null
+++ b/arch/arm/cpu/mmu.h
@@ -0,0 +1,8 @@
+#ifndef __ARM_MMU_H
+#define __ARM_MMU_H
+
+void __mmu_cache_on(void);
+void __mmu_cache_off(void);
+void __mmu_cache_flush(void);
+
+#endif /* __ARM_MMU_H */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 3/4] ARM pbl: enable MMU during decompression
2012-08-12 14:30 [PATCH] ARM: enable MMU in pbl Sascha Hauer
2012-08-12 14:30 ` [PATCH 1/4] ARM __mmu_cache_*: Do not clobber registers Sascha Hauer
2012-08-12 14:30 ` [PATCH 2/4] ARM MMU: call __mmu_cache_* as regular C functions Sascha Hauer
@ 2012-08-12 14:30 ` Sascha Hauer
2012-08-12 18:09 ` Jean-Christophe PLAGNIOL-VILLARD
2012-08-12 14:30 ` [PATCH 4/4] create a common ARM flush_icache function Sascha Hauer
2012-09-20 18:52 ` [PATCH] ARM: enable MMU in pbl Jean-Christophe PLAGNIOL-VILLARD
4 siblings, 1 reply; 14+ messages in thread
From: Sascha Hauer @ 2012-08-12 14:30 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/Makefile | 4 ++++
arch/arm/cpu/start-pbl.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 49 insertions(+)
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index 78d300d..0ecc72e 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -10,9 +10,13 @@ obj-$(CONFIG_CMD_ARM_CPUINFO) += cpuinfo.o
obj-$(CONFIG_CMD_ARM_MMUINFO) += mmuinfo.o
obj-$(CONFIG_MMU) += mmu.o
obj-$(CONFIG_CPU_32v4T) += cache-armv4.o
+pbl-$(CONFIG_CPU_32v4T) += cache-armv4.o
obj-$(CONFIG_CPU_32v5) += cache-armv5.o
+pbl-$(CONFIG_CPU_32v5) += cache-armv5.o
obj-$(CONFIG_CPU_32v6) += cache-armv6.o
+pbl-$(CONFIG_CPU_32v6) += cache-armv6.o
obj-$(CONFIG_CPU_32v7) += cache-armv7.o
+pbl-$(CONFIG_CPU_32v7) += cache-armv7.o
obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
pbl-y += start-pbl.o start-reset.o
diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c
index 004ba6a..1b67e2a 100644
--- a/arch/arm/cpu/start-pbl.c
+++ b/arch/arm/cpu/start-pbl.c
@@ -28,6 +28,9 @@
#include <asm/barebox-arm-head.h>
#include <asm-generic/memory_layout.h>
#include <asm/sections.h>
+#include <asm/pgtable.h>
+
+#include "mmu.h"
unsigned long free_mem_ptr;
unsigned long free_mem_end_ptr;
@@ -50,14 +53,53 @@ extern void *input_data_end;
#include "../../../../lib/decompress_inflate.c"
#endif
+static void mmu_enable(unsigned long *ttb)
+{
+ int i;
+
+ /* Set the ttb register */
+ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb) /*:*/);
+
+ /* Set the Domain Access Control Register */
+ i = 0x3;
+ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+ /* create a flat mapping using 1MiB sections */
+ for (i = 0; i < 4096; i++)
+ ttb[i] = (i << 20) | PMD_SECT_AP_WRITE |
+ PMD_SECT_AP_READ | PMD_TYPE_SECT |
+ PMD_SECT_WB;
+
+ __mmu_cache_on();
+}
+
+static void mmu_disable(void)
+{
+ __mmu_cache_flush();
+ __mmu_cache_off();
+}
+
static void barebox_uncompress(void *compressed_start, unsigned int len)
{
void (*barebox)(void);
+ unsigned long *ttb;
+ /*
+ * We create a flat mapping for the whole address space
+ * and enable the MMU here. This means that you cannot use
+ * any hardware like UARTs while the MMU is on. If you want
+ * to debug this code disable MMU support below.
+ */
+ int use_mmu = IS_ENABLED(CONFIG_MMU);
/* set 128 KiB at the end of the MALLOC_BASE for early malloc */
free_mem_ptr = MALLOC_BASE + MALLOC_SIZE - SZ_128K;
free_mem_end_ptr = free_mem_ptr + SZ_128K;
+ ttb = (void *)((free_mem_ptr - 0x4000) & ~0x3fff);
+
+ if (use_mmu)
+ mmu_enable(ttb);
+
if (IS_ENABLED(CONFIG_THUMB2_BAREBOX))
barebox = (void *)(TEXT_BASE + 1);
else
@@ -68,6 +110,9 @@ static void barebox_uncompress(void *compressed_start, unsigned int len)
NULL, NULL,
(void *)TEXT_BASE, NULL, NULL);
+ if (use_mmu)
+ mmu_disable();
+
/* flush I-cache before jumping to the uncompressed binary */
__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
--
1.7.10.4
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 3/4] ARM pbl: enable MMU during decompression
2012-08-12 14:30 ` [PATCH 3/4] ARM pbl: enable MMU during decompression Sascha Hauer
@ 2012-08-12 18:09 ` Jean-Christophe PLAGNIOL-VILLARD
2012-08-13 18:29 ` Sascha Hauer
0 siblings, 1 reply; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-08-12 18:09 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 16:30 Sun 12 Aug , Sascha Hauer wrote:
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/cpu/Makefile | 4 ++++
> arch/arm/cpu/start-pbl.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 49 insertions(+)
>
> diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
> index 78d300d..0ecc72e 100644
> --- a/arch/arm/cpu/Makefile
> +++ b/arch/arm/cpu/Makefile
> @@ -10,9 +10,13 @@ obj-$(CONFIG_CMD_ARM_CPUINFO) += cpuinfo.o
> obj-$(CONFIG_CMD_ARM_MMUINFO) += mmuinfo.o
> obj-$(CONFIG_MMU) += mmu.o
> obj-$(CONFIG_CPU_32v4T) += cache-armv4.o
> +pbl-$(CONFIG_CPU_32v4T) += cache-armv4.o
> obj-$(CONFIG_CPU_32v5) += cache-armv5.o
> +pbl-$(CONFIG_CPU_32v5) += cache-armv5.o
> obj-$(CONFIG_CPU_32v6) += cache-armv6.o
> +pbl-$(CONFIG_CPU_32v6) += cache-armv6.o
> obj-$(CONFIG_CPU_32v7) += cache-armv7.o
> +pbl-$(CONFIG_CPU_32v7) += cache-armv7.o
> obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
>
> pbl-y += start-pbl.o start-reset.o
> diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c
> index 004ba6a..1b67e2a 100644
> --- a/arch/arm/cpu/start-pbl.c
> +++ b/arch/arm/cpu/start-pbl.c
> @@ -28,6 +28,9 @@
> #include <asm/barebox-arm-head.h>
> #include <asm-generic/memory_layout.h>
> #include <asm/sections.h>
> +#include <asm/pgtable.h>
> +
> +#include "mmu.h"
>
> unsigned long free_mem_ptr;
> unsigned long free_mem_end_ptr;
> @@ -50,14 +53,53 @@ extern void *input_data_end;
> #include "../../../../lib/decompress_inflate.c"
> #endif
>
> +static void mmu_enable(unsigned long *ttb)
> +{
> + int i;
> +
> + /* Set the ttb register */
> + asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb) /*:*/);
> +
> + /* Set the Domain Access Control Register */
> + i = 0x3;
> + asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
> +
> + /* create a flat mapping using 1MiB sections */
> + for (i = 0; i < 4096; i++)
> + ttb[i] = (i << 20) | PMD_SECT_AP_WRITE |
> + PMD_SECT_AP_READ | PMD_TYPE_SECT |
> + PMD_SECT_WB;
> +
> + __mmu_cache_on();
> +}
> +
> +static void mmu_disable(void)
> +{
> + __mmu_cache_flush();
> + __mmu_cache_off();
> +}
> +
> static void barebox_uncompress(void *compressed_start, unsigned int len)
> {
> void (*barebox)(void);
> + unsigned long *ttb;
> + /*
> + * We create a flat mapping for the whole address space
> + * and enable the MMU here. This means that you cannot use
> + * any hardware like UARTs while the MMU is on. If you want
> + * to debug this code disable MMU support below.
> + */
> + int use_mmu = IS_ENABLED(CONFIG_MMU);
I really do not like it as I do want to be able to use nand flash as the same
time or other controller so we need a better to handle it
Best Regards,
J.
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 3/4] ARM pbl: enable MMU during decompression
2012-08-12 18:09 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2012-08-13 18:29 ` Sascha Hauer
2012-09-21 13:18 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 14+ messages in thread
From: Sascha Hauer @ 2012-08-13 18:29 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
On Sun, Aug 12, 2012 at 08:09:47PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> I really do not like it as I do want to be able to use nand flash as the same
> time or other controller so we need a better to handle it
>
8<---------------------------------------------------
[PATCH] ARM pbl: enable MMU during decompression
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/Makefile | 4 +++
arch/arm/cpu/start-pbl.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 75 insertions(+)
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index 78d300d..0ecc72e 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -10,9 +10,13 @@ obj-$(CONFIG_CMD_ARM_CPUINFO) += cpuinfo.o
obj-$(CONFIG_CMD_ARM_MMUINFO) += mmuinfo.o
obj-$(CONFIG_MMU) += mmu.o
obj-$(CONFIG_CPU_32v4T) += cache-armv4.o
+pbl-$(CONFIG_CPU_32v4T) += cache-armv4.o
obj-$(CONFIG_CPU_32v5) += cache-armv5.o
+pbl-$(CONFIG_CPU_32v5) += cache-armv5.o
obj-$(CONFIG_CPU_32v6) += cache-armv6.o
+pbl-$(CONFIG_CPU_32v6) += cache-armv6.o
obj-$(CONFIG_CPU_32v7) += cache-armv7.o
+pbl-$(CONFIG_CPU_32v7) += cache-armv7.o
obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
pbl-y += start-pbl.o start-reset.o
diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c
index 004ba6a..8eb465c 100644
--- a/arch/arm/cpu/start-pbl.c
+++ b/arch/arm/cpu/start-pbl.c
@@ -28,6 +28,9 @@
#include <asm/barebox-arm-head.h>
#include <asm-generic/memory_layout.h>
#include <asm/sections.h>
+#include <asm/pgtable.h>
+
+#include "mmu.h"
unsigned long free_mem_ptr;
unsigned long free_mem_end_ptr;
@@ -50,14 +53,79 @@ extern void *input_data_end;
#include "../../../../lib/decompress_inflate.c"
#endif
+static unsigned long *ttb;
+
+static void create_sections(unsigned long addr, int size, unsigned int flags)
+{
+ int i;
+
+ addr >>= 20;
+ size >>= 20;
+
+ for (i = size; i > 0; i--, addr++)
+ ttb[addr] = (addr << 20) | flags;
+}
+
+static void map_cachable(unsigned long start, unsigned long size)
+{
+ start &= ~(SZ_1M - 1);
+ size = (size + (SZ_1M - 1)) & ~(SZ_1M - 1);
+
+ create_sections(start, size, PMD_SECT_AP_WRITE |
+ PMD_SECT_AP_READ | PMD_TYPE_SECT | PMD_SECT_WB);
+}
+
+static void mmu_enable(unsigned long compressed_start, unsigned int len)
+{
+ int i;
+
+ /* Set the ttb register */
+ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb) /*:*/);
+
+ /* Set the Domain Access Control Register */
+ i = 0x3;
+ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+ create_sections(0, 4096, PMD_SECT_AP_WRITE |
+ PMD_SECT_AP_READ | PMD_TYPE_SECT);
+ /*
+ * Setup all regions we need cacheable, namely:
+ * - the stack
+ * - the decompressor code
+ * - the compressed image
+ * - the uncompressed image
+ * - the early malloc space
+ */
+ map_cachable(STACK_BASE, STACK_SIZE);
+ map_cachable((unsigned long)&_text,
+ (unsigned long)&_end - (unsigned long)&_text);
+ map_cachable((unsigned long)compressed_start, len);
+ map_cachable(TEXT_BASE, len * 4);
+ map_cachable(free_mem_ptr, free_mem_end_ptr - free_mem_ptr);
+
+ __mmu_cache_on();
+}
+
+static void mmu_disable(void)
+{
+ __mmu_cache_flush();
+ __mmu_cache_off();
+}
+
static void barebox_uncompress(void *compressed_start, unsigned int len)
{
void (*barebox)(void);
+ int use_mmu = IS_ENABLED(CONFIG_MMU);
/* set 128 KiB at the end of the MALLOC_BASE for early malloc */
free_mem_ptr = MALLOC_BASE + MALLOC_SIZE - SZ_128K;
free_mem_end_ptr = free_mem_ptr + SZ_128K;
+ ttb = (void *)((free_mem_ptr - 0x4000) & ~0x3fff);
+
+ if (use_mmu)
+ mmu_enable((unsigned long)compressed_start, len);
+
if (IS_ENABLED(CONFIG_THUMB2_BAREBOX))
barebox = (void *)(TEXT_BASE + 1);
else
@@ -68,6 +136,9 @@ static void barebox_uncompress(void *compressed_start, unsigned int len)
NULL, NULL,
(void *)TEXT_BASE, NULL, NULL);
+ if (use_mmu)
+ mmu_disable();
+
/* flush I-cache before jumping to the uncompressed binary */
__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
--
1.7.10.4
--
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 3/4] ARM pbl: enable MMU during decompression
2012-08-13 18:29 ` Sascha Hauer
@ 2012-09-21 13:18 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-21 13:18 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 20:29 Mon 13 Aug , Sascha Hauer wrote:
> On Sun, Aug 12, 2012 at 08:09:47PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > I really do not like it as I do want to be able to use nand flash as the same
> > time or other controller so we need a better to handle it
> >
>
> 8<---------------------------------------------------
>
> [PATCH] ARM pbl: enable MMU during decompression
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/cpu/Makefile | 4 +++
> arch/arm/cpu/start-pbl.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 75 insertions(+)
>
this does not work on at91
dhcp && nfs
/opt/work/barebox/build/sam9m10g45ek-compressed/arch/arm/pbl/zbarebox.bin &&
bootm zbarebox.bin
fail
btu the previous version forbiddenme to use uart or nand in the decompressor
which I need on at91
Best Regards,
J.
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 4/4] create a common ARM flush_icache function
2012-08-12 14:30 [PATCH] ARM: enable MMU in pbl Sascha Hauer
` (2 preceding siblings ...)
2012-08-12 14:30 ` [PATCH 3/4] ARM pbl: enable MMU during decompression Sascha Hauer
@ 2012-08-12 14:30 ` Sascha Hauer
2012-09-20 18:52 ` [PATCH] ARM: enable MMU in pbl Jean-Christophe PLAGNIOL-VILLARD
4 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2012-08-12 14:30 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/start-pbl.c | 7 +++----
arch/arm/cpu/start.c | 4 ++--
arch/arm/include/asm/cache.h | 9 +++++++++
3 files changed, 14 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/include/asm/cache.h
diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c
index 1b67e2a..3f2eb07 100644
--- a/arch/arm/cpu/start-pbl.c
+++ b/arch/arm/cpu/start-pbl.c
@@ -29,6 +29,7 @@
#include <asm-generic/memory_layout.h>
#include <asm/sections.h>
#include <asm/pgtable.h>
+#include <asm/cache.h>
#include "mmu.h"
@@ -113,8 +114,7 @@ static void barebox_uncompress(void *compressed_start, unsigned int len)
if (use_mmu)
mmu_disable();
- /* flush I-cache before jumping to the uncompressed binary */
- __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
+ flush_icache();
barebox();
}
@@ -173,8 +173,7 @@ copy_link:
/* clear bss */
memset(__bss_start, 0, __bss_stop - __bss_start);
- /* flush I-cache before jumping to the copied binary */
- __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
+ flush_icache();
r = (unsigned int)&barebox_uncompress;
/* call barebox_uncompress with its absolute address */
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index 8365a75..07e7dfe 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -26,6 +26,7 @@
#include <asm/barebox-arm-head.h>
#include <asm-generic/memory_layout.h>
#include <asm/sections.h>
+#include <asm/cache.h>
#ifdef CONFIG_PBL_IMAGE
/*
@@ -80,8 +81,7 @@ void __naked __section(.text_ll_return) board_init_lowlevel_return(void)
/* clear bss */
memset(__bss_start, 0, __bss_stop - __bss_start);
- /* flush I-cache before jumping to the copied binary */
- __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
+ flush_icache();
/* call start_barebox with its absolute address */
r = (unsigned int)&start_barebox;
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
new file mode 100644
index 0000000..ff79749
--- /dev/null
+++ b/arch/arm/include/asm/cache.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_CACHE_H
+#define __ASM_CACHE_H
+
+static inline void flush_icache(void)
+{
+ asm volatile("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
+}
+
+#endif
--
1.7.10.4
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH] ARM: enable MMU in pbl
2012-08-12 14:30 [PATCH] ARM: enable MMU in pbl Sascha Hauer
` (3 preceding siblings ...)
2012-08-12 14:30 ` [PATCH 4/4] create a common ARM flush_icache function Sascha Hauer
@ 2012-09-20 18:52 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-20 19:56 ` Sascha Hauer
4 siblings, 1 reply; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-20 18:52 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 16:30 Sun 12 Aug , Sascha Hauer wrote:
> The following enables the MMU during decompression which speeds up
> things significantly.
Atmel board does not boot
barebox@Atmel at91sam9m10g45-ek:/ dhcp && nfs
/opt/work/barebox/build/sam9m10g45ek-compressed/arch/arm/pbl/zbarebox.bin &&
bootm zbarebox.bin
phy0: Link is up - 100/Full
DHCP client bound to address 192.168.200.43
Filename
'/opt/work/barebox/build/sam9m10g45ek-compressed/arch/arm/pbl/zbarebox.bin'.
[#################################################################]
without MMU boot fine
Best Regards,
J.
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH] ARM: enable MMU in pbl
2012-09-20 18:52 ` [PATCH] ARM: enable MMU in pbl Jean-Christophe PLAGNIOL-VILLARD
@ 2012-09-20 19:56 ` Sascha Hauer
2012-09-21 13:23 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 14+ messages in thread
From: Sascha Hauer @ 2012-09-20 19:56 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
On Thu, Sep 20, 2012 at 08:52:43PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 16:30 Sun 12 Aug , Sascha Hauer wrote:
> > The following enables the MMU during decompression which speeds up
> > things significantly.
>
> Atmel board does not boot
>
> barebox@Atmel at91sam9m10g45-ek:/ dhcp && nfs
> /opt/work/barebox/build/sam9m10g45ek-compressed/arch/arm/pbl/zbarebox.bin &&
> bootm zbarebox.bin
> phy0: Link is up - 100/Full
> DHCP client bound to address 192.168.200.43
>
> Filename
> '/opt/work/barebox/build/sam9m10g45ek-compressed/arch/arm/pbl/zbarebox.bin'.
> [#################################################################]
>
> without MMU boot fine
does it work with the v1 version of this patch?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] ARM: enable MMU in pbl
2012-09-20 19:56 ` Sascha Hauer
@ 2012-09-21 13:23 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-21 14:46 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-21 13:23 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 21:56 Thu 20 Sep , Sascha Hauer wrote:
> On Thu, Sep 20, 2012 at 08:52:43PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 16:30 Sun 12 Aug , Sascha Hauer wrote:
> > > The following enables the MMU during decompression which speeds up
> > > things significantly.
> >
> > Atmel board does not boot
> >
> > barebox@Atmel at91sam9m10g45-ek:/ dhcp && nfs
> > /opt/work/barebox/build/sam9m10g45ek-compressed/arch/arm/pbl/zbarebox.bin &&
> > bootm zbarebox.bin
> > phy0: Link is up - 100/Full
> > DHCP client bound to address 192.168.200.43
> >
> > Filename
> > '/opt/work/barebox/build/sam9m10g45ek-compressed/arch/arm/pbl/zbarebox.bin'.
> > [#################################################################]
> >
> > without MMU boot fine
>
> does it work with the v1 version of this patch?
work but can use nand :(
Best Regards,
J.
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barebox@lists.infradead.org
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] ARM: enable MMU in pbl
2012-09-21 13:23 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2012-09-21 14:46 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-22 10:21 ` Sascha Hauer
0 siblings, 1 reply; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-21 14:46 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 15:23 Fri 21 Sep , Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 21:56 Thu 20 Sep , Sascha Hauer wrote:
> > On Thu, Sep 20, 2012 at 08:52:43PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > On 16:30 Sun 12 Aug , Sascha Hauer wrote:
> > > > The following enables the MMU during decompression which speeds up
> > > > things significantly.
> > >
> > > Atmel board does not boot
> > >
> > > barebox@Atmel at91sam9m10g45-ek:/ dhcp && nfs
> > > /opt/work/barebox/build/sam9m10g45ek-compressed/arch/arm/pbl/zbarebox.bin &&
> > > bootm zbarebox.bin
> > > phy0: Link is up - 100/Full
> > > DHCP client bound to address 192.168.200.43
> > >
> > > Filename
> > > '/opt/work/barebox/build/sam9m10g45ek-compressed/arch/arm/pbl/zbarebox.bin'.
> > > [#################################################################]
> > >
> > > without MMU boot fine
> >
> > does it work with the v1 version of this patch?
> work but can use nand :(
work but can *not* use nand :(
Best Regards,
J.
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] ARM: enable MMU in pbl
2012-09-21 14:46 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2012-09-22 10:21 ` Sascha Hauer
2012-09-22 11:41 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 14+ messages in thread
From: Sascha Hauer @ 2012-09-22 10:21 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
On Fri, Sep 21, 2012 at 04:46:31PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 15:23 Fri 21 Sep , Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 21:56 Thu 20 Sep , Sascha Hauer wrote:
> > > On Thu, Sep 20, 2012 at 08:52:43PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > > On 16:30 Sun 12 Aug , Sascha Hauer wrote:
> > > > > The following enables the MMU during decompression which speeds up
> > > > > things significantly.
> > > >
> > > > Atmel board does not boot
> > > >
> > > > barebox@Atmel at91sam9m10g45-ek:/ dhcp && nfs
> > > > /opt/work/barebox/build/sam9m10g45ek-compressed/arch/arm/pbl/zbarebox.bin &&
> > > > bootm zbarebox.bin
> > > > phy0: Link is up - 100/Full
> > > > DHCP client bound to address 192.168.200.43
> > > >
> > > > Filename
> > > > '/opt/work/barebox/build/sam9m10g45ek-compressed/arch/arm/pbl/zbarebox.bin'.
> > > > [#################################################################]
> > > >
> > > > without MMU boot fine
> > >
> > > does it work with the v1 version of this patch?
> > work but can use nand :(
> work but can *not* use nand :(
The at91 port depends on at91bootstrap as first stage loader, right? So
booting from NAND seems to need out of tree code. I can't help you then.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] ARM: enable MMU in pbl
2012-09-22 10:21 ` Sascha Hauer
@ 2012-09-22 11:41 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-22 11:41 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 12:21 Sat 22 Sep , Sascha Hauer wrote:
> On Fri, Sep 21, 2012 at 04:46:31PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 15:23 Fri 21 Sep , Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > On 21:56 Thu 20 Sep , Sascha Hauer wrote:
> > > > On Thu, Sep 20, 2012 at 08:52:43PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > > > On 16:30 Sun 12 Aug , Sascha Hauer wrote:
> > > > > > The following enables the MMU during decompression which speeds up
> > > > > > things significantly.
> > > > >
> > > > > Atmel board does not boot
> > > > >
> > > > > barebox@Atmel at91sam9m10g45-ek:/ dhcp && nfs
> > > > > /opt/work/barebox/build/sam9m10g45ek-compressed/arch/arm/pbl/zbarebox.bin &&
> > > > > bootm zbarebox.bin
> > > > > phy0: Link is up - 100/Full
> > > > > DHCP client bound to address 192.168.200.43
> > > > >
> > > > > Filename
> > > > > '/opt/work/barebox/build/sam9m10g45ek-compressed/arch/arm/pbl/zbarebox.bin'.
> > > > > [#################################################################]
> > > > >
> > > > > without MMU boot fine
> > > >
> > > > does it work with the v1 version of this patch?
> > > work but can use nand :(
> > work but can *not* use nand :(
>
> The at91 port depends on at91bootstrap as first stage loader, right? So
> booting from NAND seems to need out of tree code. I can't help you then.
no I'm working to add it and drop the at91boostrap so it's mandatory for me
to have the MMU and nand access in the PBL
Best Regards,
J.
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^ permalink raw reply [flat|nested] 14+ messages in thread