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From: Sascha Hauer <s.hauer@pengutronix.de>
To: Franck Jullien <franck.jullien@gmail.com>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH 1/3] [OpenRISC] Add __ashrdi3 and remove link to libgcc
Date: Fri, 14 Sep 2012 08:40:48 +0200	[thread overview]
Message-ID: <20120914064048.GP6180@pengutronix.de> (raw)
In-Reply-To: <1347488914-7460-1-git-send-email-franck.jullien@gmail.com>

Hi Franck,

On Thu, Sep 13, 2012 at 12:28:32AM +0200, Franck Jullien wrote:
> In a previous patch, Sascha needed to add __ashrdi3 and then linked
> to libgcc. This patch add the ashrdi3 function in the arch/openrisc/lib
> directory and remove the libgcc dependency.
> 
> Signed-off-by: Franck Jullien <franck.jullien@gmail.com>


Applied this series.

Thanks
 Sascha

> ---
>  arch/openrisc/Makefile      |    4 ---
>  arch/openrisc/lib/Makefile  |    1 +
>  arch/openrisc/lib/ashrdi3.S |   59 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 60 insertions(+), 4 deletions(-)
>  create mode 100644 arch/openrisc/lib/ashrdi3.S
> 
> diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile
> index 1f4b175..fd8bbbf 100644
> --- a/arch/openrisc/Makefile
> +++ b/arch/openrisc/Makefile
> @@ -1,7 +1,5 @@
>  CPPFLAGS += -D__OR1K__ -ffixed-r10 -mhard-mul -mhard-div
>  
> -LIBGCC          := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
> -
>  board-$(CONFIG_GENERIC) := generic
>  
>  KALLSYMS += --symbol-prefix=_
> @@ -20,6 +18,4 @@ common-y += $(BOARD)
>  common-y += arch/openrisc/lib/
>  common-y += arch/openrisc/cpu/
>  
> -common-y          += $(LIBGCC)
> -
>  lds-y += arch/openrisc/cpu/barebox.lds
> diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile
> index aaf93cb..0b3cc50 100644
> --- a/arch/openrisc/lib/Makefile
> +++ b/arch/openrisc/lib/Makefile
> @@ -4,3 +4,4 @@ obj-y                 += cpuinfo.o
>  obj-y                 += muldi3.o
>  obj-y                 += lshrdi3.o
>  obj-y                 += ashldi3.o
> +obj-y                 += ashrdi3.o
> diff --git a/arch/openrisc/lib/ashrdi3.S b/arch/openrisc/lib/ashrdi3.S
> new file mode 100644
> index 0000000..c656d9f
> --- /dev/null
> +++ b/arch/openrisc/lib/ashrdi3.S
> @@ -0,0 +1,59 @@
> +/*
> + * (C) Copyright 2012 - Franck JULLIEN <elec4fun@gmail.com>
> + *
> + * Extracted from gcc generated assembly.
> + *
> + * Extended precision shifts.
> + *
> + * R3/R4 (MSW, LSW) has 64 bit value
> + * R5    has shift count
> + * result in R11/R12
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +
> +.globl __ashrdi3
> +
> +__ashrdi3:
> +	l.sfeqi r5,0x0			/* if count = 0, go out                   */
> +	l.bf out
> +
> +	l.addi r6,r0,0x20		/* r6 = 32                                */
> +	l.sub r6,r6,r5			/* r6 = 32 - count                        */
> +	l.sfgtsi r6,0x0			/* if count >= 32                         */
> +	l.bnf more_than_32		/* branch to more_than_32                 */
> +	l.nop 0x0
> +
> +
> + less_than_32:
> +	l.sll r6,r3,r6			/* r6 gets the bits moved from MSW to LSW */
> +	l.srl r4,r4,r5			/* shift LSW                              */
> +	l.sra r5,r3,r5			/* shift MSW to r5                        */
> +	l.or r4,r6,r4			/* LSW gets bits shifted from MSW         */
> +	l.ori r3,r5,0x0			/* r3 = MSW                               */
> +
> + out:
> +	l.ori r11,r3,0x0
> +	l.jr r9
> +	l.ori r12,r4,0x0
> +
> + more_than_32:
> +	l.srai r5,r3,0x1f		/* r5 = MSW sign extended                 */
> +	l.sub r4,r0,r6			/* r4 = -r6, the number of bits above 32  */
> +	l.sra r4,r3,r4			/* LSW gets bits shifted from MSB         */
> +	l.j out				/* go out                                 */
> +	l.ori r3,r5,0x0			/* r3 = MSW                               */
> -- 
> 1.7.1
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

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      parent reply	other threads:[~2012-09-14  6:41 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-09-12 22:28 Franck Jullien
2012-09-12 22:28 ` [PATCH 2/3] Add OpenRISC Image type Franck Jullien
2012-09-12 22:28 ` [PATCH 3/3] [MCI_SPI] Fix endianness error on be target Franck Jullien
2012-09-14  6:40 ` Sascha Hauer [this message]

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