* [PATCH 1/5] phylib: bus reset function
2012-09-20 16:31 [PATCH 0/5] gianfar: mdio bus support Renaud Barbier
@ 2012-09-20 16:31 ` Renaud Barbier
2012-09-20 18:23 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-20 16:31 ` [PATCH 2/5] FSL mdio bus support Renaud Barbier
` (3 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Renaud Barbier @ 2012-09-20 16:31 UTC (permalink / raw)
To: barebox
Added an entry point for a bus reset function.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
---
drivers/net/phy/phy.c | 3 +++
include/miidev.h | 1 +
2 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 5406ea3..d9f5409 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -129,6 +129,9 @@ int phy_device_connect(struct eth_device *edev, struct mii_device *bus, int addr
unsigned int i;
int ret = -EINVAL;
+ if (bus->reset)
+ bus->reset(bus);
+
if (!edev->phydev) {
if (addr >= 0) {
dev = get_phy_device(bus, addr);
diff --git a/include/miidev.h b/include/miidev.h
index dc344ca..6e4ae92 100644
--- a/include/miidev.h
+++ b/include/miidev.h
@@ -36,6 +36,7 @@ struct mii_device {
int (*read) (struct mii_device *dev, int addr, int reg);
int (*write) (struct mii_device *dev, int addr, int reg, int value);
+ int (*reset) (struct mii_device *dev);
};
int mii_register(struct mii_device *dev);
--
1.7.1
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 1/5] phylib: bus reset function
2012-09-20 16:31 ` [PATCH 1/5] phylib: bus reset function Renaud Barbier
@ 2012-09-20 18:23 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-21 6:34 ` Sascha Hauer
0 siblings, 1 reply; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-20 18:23 UTC (permalink / raw)
To: Renaud Barbier; +Cc: barebox
On 17:31 Thu 20 Sep , Renaud Barbier wrote:
> Added an entry point for a bus reset function.
>
> Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
> ---
> drivers/net/phy/phy.c | 3 +++
> include/miidev.h | 1 +
> 2 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> index 5406ea3..d9f5409 100644
> --- a/drivers/net/phy/phy.c
> +++ b/drivers/net/phy/phy.c
> @@ -129,6 +129,9 @@ int phy_device_connect(struct eth_device *edev, struct mii_device *bus, int addr
> unsigned int i;
> int ret = -EINVAL;
>
> + if (bus->reset)
> + bus->reset(bus);
> +
I do not like this we should not touch the bus at phy connect
Best Regards,
J.
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/5] phylib: bus reset function
2012-09-20 18:23 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2012-09-21 6:34 ` Sascha Hauer
2012-09-21 8:06 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 14+ messages in thread
From: Sascha Hauer @ 2012-09-21 6:34 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
On Thu, Sep 20, 2012 at 08:23:32PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 17:31 Thu 20 Sep , Renaud Barbier wrote:
> > Added an entry point for a bus reset function.
> >
> > Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
> > ---
> > drivers/net/phy/phy.c | 3 +++
> > include/miidev.h | 1 +
> > 2 files changed, 4 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> > index 5406ea3..d9f5409 100644
> > --- a/drivers/net/phy/phy.c
> > +++ b/drivers/net/phy/phy.c
> > @@ -129,6 +129,9 @@ int phy_device_connect(struct eth_device *edev, struct mii_device *bus, int addr
> > unsigned int i;
> > int ret = -EINVAL;
> >
> > + if (bus->reset)
> > + bus->reset(bus);
> > +
> I do not like this we should not touch the bus at phy connect
Then please make a suggestion where it should be then. I also have some
drivers where this function could be used.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/5] phylib: bus reset function
2012-09-21 6:34 ` Sascha Hauer
@ 2012-09-21 8:06 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-21 8:30 ` Sascha Hauer
0 siblings, 1 reply; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-21 8:06 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 08:34 Fri 21 Sep , Sascha Hauer wrote:
> On Thu, Sep 20, 2012 at 08:23:32PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 17:31 Thu 20 Sep , Renaud Barbier wrote:
> > > Added an entry point for a bus reset function.
> > >
> > > Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
> > > ---
> > > drivers/net/phy/phy.c | 3 +++
> > > include/miidev.h | 1 +
> > > 2 files changed, 4 insertions(+), 0 deletions(-)
> > >
> > > diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> > > index 5406ea3..d9f5409 100644
> > > --- a/drivers/net/phy/phy.c
> > > +++ b/drivers/net/phy/phy.c
> > > @@ -129,6 +129,9 @@ int phy_device_connect(struct eth_device *edev, struct mii_device *bus, int addr
> > > unsigned int i;
> > > int ret = -EINVAL;
> > >
> > > + if (bus->reset)
> > > + bus->reset(bus);
> > > +
> > I do not like this we should not touch the bus at phy connect
>
> Then please make a suggestion where it should be then. I also have some
> drivers where this function could be used.
I have too the need of a reset
I get a big issue on reset the mii bus at eth open
my only idea was to move the phy detect awqy from the eth_open to the mii bus
probe
but this will increase the boot time as we do not need to probe the phy if we
do not use the network
Best Regards,
J.
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/5] phylib: bus reset function
2012-09-21 8:06 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2012-09-21 8:30 ` Sascha Hauer
2012-09-21 17:04 ` Renaud Barbier
0 siblings, 1 reply; 14+ messages in thread
From: Sascha Hauer @ 2012-09-21 8:30 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
On Fri, Sep 21, 2012 at 10:06:58AM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 08:34 Fri 21 Sep , Sascha Hauer wrote:
> > On Thu, Sep 20, 2012 at 08:23:32PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > On 17:31 Thu 20 Sep , Renaud Barbier wrote:
> > > > Added an entry point for a bus reset function.
> > > >
> > > > Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
> > > > ---
> > > > drivers/net/phy/phy.c | 3 +++
> > > > include/miidev.h | 1 +
> > > > 2 files changed, 4 insertions(+), 0 deletions(-)
> > > >
> > > > diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> > > > index 5406ea3..d9f5409 100644
> > > > --- a/drivers/net/phy/phy.c
> > > > +++ b/drivers/net/phy/phy.c
> > > > @@ -129,6 +129,9 @@ int phy_device_connect(struct eth_device *edev, struct mii_device *bus, int addr
> > > > unsigned int i;
> > > > int ret = -EINVAL;
> > > >
> > > > + if (bus->reset)
> > > > + bus->reset(bus);
> > > > +
> > > I do not like this we should not touch the bus at phy connect
> >
> > Then please make a suggestion where it should be then. I also have some
> > drivers where this function could be used.
> I have too the need of a reset
>
> I get a big issue on reset the mii bus at eth open
>
> my only idea was to move the phy detect awqy from the eth_open to the mii bus
> probe
>
> but this will increase the boot time as we do not need to probe the phy if we
> do not use the network
Before we start adding quirks for do-the-reset-only-when necessary,
access-the-phy-pnly-when necessary can we have a statement on which
timescales we talk about here? A quick test on a i.MX board shows that
detecting the phy takes 186us when its address is specified and 1.7ms
when the whole bus is scanned for phys. This is really not worth adding
quirks for.
BTW the reset function for the mii *bus* really should be done when the
bus is registered. Doing it when a new phy is registered will break phys
already present.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/5] phylib: bus reset function
2012-09-21 8:30 ` Sascha Hauer
@ 2012-09-21 17:04 ` Renaud Barbier
2012-09-21 17:20 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 14+ messages in thread
From: Renaud Barbier @ 2012-09-21 17:04 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 21/09/12 09:30, Sascha Hauer wrote:
> On Fri, Sep 21, 2012 at 10:06:58AM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
>> On 08:34 Fri 21 Sep , Sascha Hauer wrote:
>>> On Thu, Sep 20, 2012 at 08:23:32PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>>> On 17:31 Thu 20 Sep , Renaud Barbier wrote:
>>>>> Added an entry point for a bus reset function.
>>>>>
>>>>> Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
>>>>> ---
>>>>> drivers/net/phy/phy.c | 3 +++
>>>>> include/miidev.h | 1 +
>>>>> 2 files changed, 4 insertions(+), 0 deletions(-)
>>>>>
>>>>> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
>>>>> index 5406ea3..d9f5409 100644
>>>>> --- a/drivers/net/phy/phy.c
>>>>> +++ b/drivers/net/phy/phy.c
>>>>> @@ -129,6 +129,9 @@ int phy_device_connect(struct eth_device *edev, struct mii_device *bus, int addr
>>>>> unsigned int i;
>>>>> int ret = -EINVAL;
>>>>>
>>>>> + if (bus->reset)
>>>>> + bus->reset(bus);
>>>>> +
>>>> I do not like this we should not touch the bus at phy connect
>>>
>>> Then please make a suggestion where it should be then. I also have some
>>> drivers where this function could be used.
>> I have too the need of a reset
>>
>> I get a big issue on reset the mii bus at eth open
>>
>> my only idea was to move the phy detect awqy from the eth_open to the mii bus
>> probe
>>
>> but this will increase the boot time as we do not need to probe the phy if we
>> do not use the network
>
> Before we start adding quirks for do-the-reset-only-when necessary,
> access-the-phy-pnly-when necessary can we have a statement on which
> timescales we talk about here? A quick test on a i.MX board shows that
> detecting the phy takes 186us when its address is specified and 1.7ms
> when the whole bus is scanned for phys. This is really not worth adding
> quirks for.
>
> BTW the reset function for the mii *bus* really should be done when the
> bus is registered. Doing it when a new phy is registered will break phys
> already present.
In summary, we agree that we need a bus reset function and that it
should be called at present by the function mii_register.
>
> Sascha
>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/5] phylib: bus reset function
2012-09-21 17:04 ` Renaud Barbier
@ 2012-09-21 17:20 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-21 17:20 UTC (permalink / raw)
To: Renaud Barbier; +Cc: barebox
On 18:04 Fri 21 Sep , Renaud Barbier wrote:
> On 21/09/12 09:30, Sascha Hauer wrote:
> > On Fri, Sep 21, 2012 at 10:06:58AM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >> On 08:34 Fri 21 Sep , Sascha Hauer wrote:
> >>> On Thu, Sep 20, 2012 at 08:23:32PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >>>> On 17:31 Thu 20 Sep , Renaud Barbier wrote:
> >>>>> Added an entry point for a bus reset function.
> >>>>>
> >>>>> Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
> >>>>> ---
> >>>>> drivers/net/phy/phy.c | 3 +++
> >>>>> include/miidev.h | 1 +
> >>>>> 2 files changed, 4 insertions(+), 0 deletions(-)
> >>>>>
> >>>>> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> >>>>> index 5406ea3..d9f5409 100644
> >>>>> --- a/drivers/net/phy/phy.c
> >>>>> +++ b/drivers/net/phy/phy.c
> >>>>> @@ -129,6 +129,9 @@ int phy_device_connect(struct eth_device *edev, struct mii_device *bus, int addr
> >>>>> unsigned int i;
> >>>>> int ret = -EINVAL;
> >>>>>
> >>>>> + if (bus->reset)
> >>>>> + bus->reset(bus);
> >>>>> +
> >>>> I do not like this we should not touch the bus at phy connect
> >>>
> >>> Then please make a suggestion where it should be then. I also have some
> >>> drivers where this function could be used.
> >> I have too the need of a reset
> >>
> >> I get a big issue on reset the mii bus at eth open
> >>
> >> my only idea was to move the phy detect awqy from the eth_open to the mii bus
> >> probe
> >>
> >> but this will increase the boot time as we do not need to probe the phy if we
> >> do not use the network
> >
> > Before we start adding quirks for do-the-reset-only-when necessary,
> > access-the-phy-pnly-when necessary can we have a statement on which
> > timescales we talk about here? A quick test on a i.MX board shows that
> > detecting the phy takes 186us when its address is specified and 1.7ms
> > when the whole bus is scanned for phys. This is really not worth adding
> > quirks for.
> >
> > BTW the reset function for the mii *bus* really should be done when the
> > bus is registered. Doing it when a new phy is registered will break phys
> > already present.
> In summary, we agree that we need a bus reset function and that it
> should be called at present by the function mii_register.
wait a few we agree on more than this, I will take a look how to update the
phylib correctly
Best Regards,
J.
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/5] FSL mdio bus support
2012-09-20 16:31 [PATCH 0/5] gianfar: mdio bus support Renaud Barbier
2012-09-20 16:31 ` [PATCH 1/5] phylib: bus reset function Renaud Barbier
@ 2012-09-20 16:31 ` Renaud Barbier
2012-09-20 18:27 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-20 16:31 ` [PATCH 3/5] gianfar update Renaud Barbier
` (2 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Renaud Barbier @ 2012-09-20 16:31 UTC (permalink / raw)
To: barebox
An new file is added to handle the Freescale mdio bus. PHY access functions
have been pulled out of the gianfar driver and a bus reset function defined
in this new file.
Also an initialization function is added to register the mii device
with the read/write/reset function and bus base address.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
---
arch/ppc/include/asm/fsl_mdio.h | 11 +++
drivers/net/fsl_mdio.c | 134 +++++++++++++++++++++++++++++++++++++++
2 files changed, 145 insertions(+), 0 deletions(-)
create mode 100644 arch/ppc/include/asm/fsl_mdio.h
create mode 100644 drivers/net/fsl_mdio.c
diff --git a/arch/ppc/include/asm/fsl_mdio.h b/arch/ppc/include/asm/fsl_mdio.h
new file mode 100644
index 0000000..816d8e0
--- /dev/null
+++ b/arch/ppc/include/asm/fsl_mdio.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ */
+int fsl_local_mdio_write(void __iomem *phyregs, uint addr, uint reg, uint val);
+uint fsl_local_mdio_read(void __iomem *phyregs, uint phyid, uint reg);
+int fsl_pq_mdio_init(void *busaddr);
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
new file mode 100644
index 0000000..174a8e0
--- /dev/null
+++ b/drivers/net/fsl_mdio.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * Copyright 2012 GE Intelligent Platforms, Inc.
+ * based on work by Jun-jie Zhang and Mingkai Hu
+ */
+
+#include <common.h>
+#include <linux/phy.h>
+#include <init.h>
+#include <miidev.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include "gianfar.h"
+
+/* Writes the given phy's reg with value, using the specified MDIO regs */
+int fsl_local_mdio_write(void __iomem *phyregs, uint addr, uint reg, uint val)
+{
+ uint64_t start;
+
+ out_be32(phyregs + GFAR_MIIMADD_OFFSET, (addr << 8) | (reg & 0x1f));
+ out_be32(phyregs + GFAR_MIIMCON_OFFSET, val);
+
+ start = get_time_ns();
+ while (!is_timeout(start, 10 * MSECOND)) {
+ if (!(in_be32(phyregs + GFAR_MIIMMIND_OFFSET) &
+ GFAR_MIIMIND_BUSY))
+ return 0;
+ }
+
+ return -EIO;
+}
+
+/*
+ * Reads register regnum on the device's PHY through the
+ * specified registers. It lowers and raises the read
+ * command, and waits for the data to become valid (miimind
+ * notvalid bit cleared), and the bus to cease activity (miimind
+ * busy bit cleared), and then returns the value
+ */
+uint fsl_local_mdio_read(void __iomem *phyregs, uint phyid, uint reg)
+{
+ uint64_t start;
+
+ /* Put the address of the phy, and the register number into MIIMADD */
+ out_be32(phyregs + GFAR_MIIMADD_OFFSET, (phyid << 8) | (reg & 0x1f));
+
+ /* Clear the command register, and wait */
+ out_be32(phyregs + GFAR_MIIMCOM_OFFSET, 0);
+
+ /* Initiate a read command, and wait */
+ out_be32(phyregs + GFAR_MIIMCOM_OFFSET, GFAR_MIIM_READ_COMMAND);
+
+ start = get_time_ns();
+ while (!is_timeout(start, 10 * MSECOND)) {
+ if (!(in_be32(phyregs + GFAR_MIIMMIND_OFFSET) &
+ (GFAR_MIIMIND_NOTVALID | GFAR_MIIMIND_BUSY)))
+ return in_be32(phyregs + GFAR_MIIMSTAT_OFFSET);
+ }
+
+ return -EIO;
+}
+
+/* Read a MII PHY register. */
+static int fsl_miiphy_read(struct mii_device *bus, int addr, int reg)
+{
+ struct device_d *dev = bus->parent;
+ void __iomem *phyregs = bus->priv;
+ int ret;
+
+ ret = fsl_local_mdio_read(phyregs, addr, reg);
+ if (ret == -EIO)
+ dev_err(dev, "Can't read PHY at address %d\n", addr);
+
+ return ret;
+}
+
+/* Write a MII PHY register. */
+static int fsl_miiphy_write(struct mii_device *bus, int addr, int reg,
+ int value)
+{
+ struct device_d *dev = bus->parent;
+ void __iomem *phyregs = bus->priv;
+ unsigned short val = value;
+ int ret;
+
+ ret = fsl_local_mdio_write(phyregs, addr, reg, val);
+
+ if (ret)
+ dev_err(dev, "Can't write PHY at address %d\n", addr);
+
+ return 0;
+}
+
+static int fsl_pq_mdio_reset(struct mii_device *bus)
+{
+ void __iomem *phyregs = bus->priv;
+ uint64_t start;
+
+ /* Reset MII (due to new addresses) */
+ out_be32(phyregs + GFAR_MIIMCFG_OFFSET, GFAR_MIIMCFG_RESET);
+ out_be32(phyregs + GFAR_MIIMCFG_OFFSET, GFAR_MIIMCFG_INIT_VALUE);
+
+ start = get_time_ns();
+ while (!is_timeout(start, 10 * MSECOND)) {
+ if (!(in_be32(phyregs + GFAR_MIIMMIND_OFFSET) &
+ GFAR_MIIMIND_BUSY))
+ break;
+ }
+
+ return 0;
+}
+
+int fsl_pq_mdio_init(void *busaddr)
+{
+ struct mii_device *bus;
+
+ bus = xzalloc(sizeof(struct mii_device));
+ if (bus == NULL)
+ return -ENOMEM;
+
+ bus->read = fsl_miiphy_read;
+ bus->write = fsl_miiphy_write;
+ bus->reset = fsl_pq_mdio_reset;
+ bus->parent = NULL;
+ bus->priv = busaddr;
+
+ return mii_register(bus);
+}
--
1.7.1
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 2/5] FSL mdio bus support
2012-09-20 16:31 ` [PATCH 2/5] FSL mdio bus support Renaud Barbier
@ 2012-09-20 18:27 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-20 18:27 UTC (permalink / raw)
To: Renaud Barbier; +Cc: barebox
On 17:31 Thu 20 Sep , Renaud Barbier wrote:
> An new file is added to handle the Freescale mdio bus. PHY access functions
> have been pulled out of the gianfar driver and a bus reset function defined
> in this new file.
> Also an initialization function is added to register the mii device
> with the read/write/reset function and bus base address.
>
> Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
> ---
> arch/ppc/include/asm/fsl_mdio.h | 11 +++
> drivers/net/fsl_mdio.c | 134 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 145 insertions(+), 0 deletions(-)
> create mode 100644 arch/ppc/include/asm/fsl_mdio.h
> create mode 100644 drivers/net/fsl_mdio.c
>
> diff --git a/arch/ppc/include/asm/fsl_mdio.h b/arch/ppc/include/asm/fsl_mdio.h
> new file mode 100644
> index 0000000..816d8e0
> --- /dev/null
> +++ b/arch/ppc/include/asm/fsl_mdio.h
> @@ -0,0 +1,11 @@
> +/*
> + * Copyright 2012 GE Intelligent Platforms, Inc.
> + *
> + * This software may be used and distributed according to the
> + * terms of the GNU Public License, Version 2, incorporated
> + * herein by reference.
> + *
> + */
> +int fsl_local_mdio_write(void __iomem *phyregs, uint addr, uint reg, uint val);
> +uint fsl_local_mdio_read(void __iomem *phyregs, uint phyid, uint reg);
> +int fsl_pq_mdio_init(void *busaddr);
> diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
> new file mode 100644
> index 0000000..174a8e0
> --- /dev/null
> +++ b/drivers/net/fsl_mdio.c
> @@ -0,0 +1,134 @@
> +/*
> + * Copyright 2009-2010 Freescale Semiconductor, Inc.
> + *
> + * This software may be used and distributed according to the
> + * terms of the GNU Public License, Version 2, incorporated
> + * herein by reference.
> + *
> + * Copyright 2012 GE Intelligent Platforms, Inc.
> + * based on work by Jun-jie Zhang and Mingkai Hu
> + */
> +
> +#include <common.h>
> +#include <linux/phy.h>
> +#include <init.h>
> +#include <miidev.h>
> +#include <malloc.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +#include "gianfar.h"
> +
> +/* Writes the given phy's reg with value, using the specified MDIO regs */
> +int fsl_local_mdio_write(void __iomem *phyregs, uint addr, uint reg, uint val)
> +{
> + uint64_t start;
> +
> + out_be32(phyregs + GFAR_MIIMADD_OFFSET, (addr << 8) | (reg & 0x1f));
> + out_be32(phyregs + GFAR_MIIMCON_OFFSET, val);
> +
> + start = get_time_ns();
> + while (!is_timeout(start, 10 * MSECOND)) {
> + if (!(in_be32(phyregs + GFAR_MIIMMIND_OFFSET) &
> + GFAR_MIIMIND_BUSY))
> + return 0;
> + }
> +
> + return -EIO;
> +}
> +
> +/*
> + * Reads register regnum on the device's PHY through the
> + * specified registers. It lowers and raises the read
> + * command, and waits for the data to become valid (miimind
> + * notvalid bit cleared), and the bus to cease activity (miimind
> + * busy bit cleared), and then returns the value
> + */
> +uint fsl_local_mdio_read(void __iomem *phyregs, uint phyid, uint reg)
> +{
> + uint64_t start;
> +
> + /* Put the address of the phy, and the register number into MIIMADD */
> + out_be32(phyregs + GFAR_MIIMADD_OFFSET, (phyid << 8) | (reg & 0x1f));
> +
> + /* Clear the command register, and wait */
> + out_be32(phyregs + GFAR_MIIMCOM_OFFSET, 0);
> +
> + /* Initiate a read command, and wait */
> + out_be32(phyregs + GFAR_MIIMCOM_OFFSET, GFAR_MIIM_READ_COMMAND);
> +
> + start = get_time_ns();
> + while (!is_timeout(start, 10 * MSECOND)) {
> + if (!(in_be32(phyregs + GFAR_MIIMMIND_OFFSET) &
> + (GFAR_MIIMIND_NOTVALID | GFAR_MIIMIND_BUSY)))
> + return in_be32(phyregs + GFAR_MIIMSTAT_OFFSET);
> + }
> +
> + return -EIO;
> +}
> +
> +/* Read a MII PHY register. */
> +static int fsl_miiphy_read(struct mii_device *bus, int addr, int reg)
> +{
> + struct device_d *dev = bus->parent;
> + void __iomem *phyregs = bus->priv;
> + int ret;
> +
> + ret = fsl_local_mdio_read(phyregs, addr, reg);
> + if (ret == -EIO)
> + dev_err(dev, "Can't read PHY at address %d\n", addr);
> +
> + return ret;
> +}
> +
> +/* Write a MII PHY register. */
> +static int fsl_miiphy_write(struct mii_device *bus, int addr, int reg,
> + int value)
> +{
> + struct device_d *dev = bus->parent;
> + void __iomem *phyregs = bus->priv;
> + unsigned short val = value;
> + int ret;
> +
> + ret = fsl_local_mdio_write(phyregs, addr, reg, val);
> +
> + if (ret)
> + dev_err(dev, "Can't write PHY at address %d\n", addr);
> +
> + return 0;
> +}
> +
> +static int fsl_pq_mdio_reset(struct mii_device *bus)
> +{
> + void __iomem *phyregs = bus->priv;
> + uint64_t start;
> +
> + /* Reset MII (due to new addresses) */
> + out_be32(phyregs + GFAR_MIIMCFG_OFFSET, GFAR_MIIMCFG_RESET);
> + out_be32(phyregs + GFAR_MIIMCFG_OFFSET, GFAR_MIIMCFG_INIT_VALUE);
> +
> + start = get_time_ns();
> + while (!is_timeout(start, 10 * MSECOND)) {
we have a timeout function for this wait_xxx
> + if (!(in_be32(phyregs + GFAR_MIIMMIND_OFFSET) &
> + GFAR_MIIMIND_BUSY))
> + break;
> + }
> +
> + return 0;
> +}
> +
> +int fsl_pq_mdio_init(void *busaddr)
> +{
> + struct mii_device *bus;
> +
> + bus = xzalloc(sizeof(struct mii_device));
> + if (bus == NULL)
> + return -ENOMEM;
no need xzalloc does not retrun if no mem
> +
> + bus->read = fsl_miiphy_read;
> + bus->write = fsl_miiphy_write;
> + bus->reset = fsl_pq_mdio_reset;
> + bus->parent = NULL;
no need you use zalloc
> + bus->priv = busaddr;
> +
> + return mii_register(bus);
> +}
Best Regards,
J.
> --
> 1.7.1
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 3/5] gianfar update
2012-09-20 16:31 [PATCH 0/5] gianfar: mdio bus support Renaud Barbier
2012-09-20 16:31 ` [PATCH 1/5] phylib: bus reset function Renaud Barbier
2012-09-20 16:31 ` [PATCH 2/5] FSL mdio bus support Renaud Barbier
@ 2012-09-20 16:31 ` Renaud Barbier
2012-09-20 18:30 ` Jean-Christophe PLAGNIOL-VILLARD
2012-09-20 16:31 ` [PATCH 4/5] FSL mdio: configuration and build file Renaud Barbier
2012-09-20 16:31 ` [PATCH 5/5] P2020rdb: eTSEC2 support Renaud Barbier
4 siblings, 1 reply; 14+ messages in thread
From: Renaud Barbier @ 2012-09-20 16:31 UTC (permalink / raw)
To: barebox
The gianfar is updated following the addition of the FSL mdio bus support.
PHY access functions have been removed as well as the reset of the mdio
bus.
Also the resource for the External PHY registers has been removed
from the Ethernet port initialization function.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
---
arch/ppc/mach-mpc85xx/eth-devices.c | 14 +--
arch/ppc/mach-mpc85xx/include/mach/gianfar.h | 2 +
drivers/net/gianfar.c | 127 ++++----------------------
drivers/net/gianfar.h | 3 +-
4 files changed, 26 insertions(+), 120 deletions(-)
diff --git a/arch/ppc/mach-mpc85xx/eth-devices.c b/arch/ppc/mach-mpc85xx/eth-devices.c
index c6e8f36..8399f21 100644
--- a/arch/ppc/mach-mpc85xx/eth-devices.c
+++ b/arch/ppc/mach-mpc85xx/eth-devices.c
@@ -29,21 +29,17 @@ int fsl_eth_init(int num, struct gfar_info_struct *gf)
{
struct resource *res;
- res = xzalloc(3 * sizeof(struct resource));
+ res = xzalloc(2 * sizeof(struct resource));
/* TSEC interface registers */
res[0].start = GFAR_BASE_ADDR + ((num - 1) * 0x1000);
res[0].end = res[0].start + 0x1000 - 1;
res[0].flags = IORESOURCE_MEM;
- /* External PHY access always through eTSEC1 */
- res[1].start = MDIO_BASE_ADDR;
- res[1].end = res[1].start + 0x1000 - 1;
- res[1].flags = IORESOURCE_MEM;
/* Access to TBI/RTBI interface. */
- res[2].start = MDIO_BASE_ADDR + ((num - 1) * 0x1000);
- res[2].end = res[2].start + 0x1000 - 1;
- res[2].flags = IORESOURCE_MEM;
+ res[1].start = MDIO_BASE_ADDR + ((num - 1) * 0x1000);
+ res[1].end = res[2].start + 0x1000 - 1;
+ res[1].flags = IORESOURCE_MEM;
- add_generic_device_res("gfar", DEVICE_ID_DYNAMIC, res, 3, gf);
+ add_generic_device_res("gfar", DEVICE_ID_DYNAMIC, res, 2, gf);
return 0;
}
diff --git a/arch/ppc/mach-mpc85xx/include/mach/gianfar.h b/arch/ppc/mach-mpc85xx/include/mach/gianfar.h
index ae31638..2c6d58c 100644
--- a/arch/ppc/mach-mpc85xx/include/mach/gianfar.h
+++ b/arch/ppc/mach-mpc85xx/include/mach/gianfar.h
@@ -22,6 +22,8 @@
* Platform data for the Motorola Triple Speed Ethernet Controller
*/
+#include <asm/fsl_mdio.h>
+
struct gfar_info_struct {
unsigned int phyaddr;
unsigned int tbiana;
diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c
index f8a7cd7..a8033b4 100644
--- a/drivers/net/gianfar.c
+++ b/drivers/net/gianfar.c
@@ -83,7 +83,6 @@ static void gfar_adjust_link(struct eth_device *edev)
struct gfar_private *priv = edev->priv;
void __iomem *regs = priv->regs;
u32 ecntrl, maccfg2;
- uint32_t status;
priv->link = edev->phydev->link;
priv->duplexity =edev->phydev->duplex;
@@ -189,7 +188,7 @@ static int gfar_open(struct eth_device *edev)
void __iomem *regs = priv->regs;
int ret;
- ret = phy_device_connect(edev, &priv->miidev, priv->phyaddr,
+ ret = phy_device_connect(edev, priv->miidev, priv->phyaddr,
gfar_adjust_link, 0, PHY_INTERFACE_MODE_NA);
if (ret)
return ret;
@@ -256,64 +255,15 @@ static int gfar_set_ethaddr(struct eth_device *edev, unsigned char *mac)
return 0;
}
-/* Writes the given phy's reg with value, using the specified MDIO regs */
-static int gfar_local_mdio_write(void __iomem *phyregs, uint addr, uint reg,
- uint value)
-{
- uint64_t start;
-
- out_be32(phyregs + GFAR_MIIMADD_OFFSET, (addr << 8) | (reg & 0x1f));
- out_be32(phyregs + GFAR_MIIMCON_OFFSET, value);
-
- start = get_time_ns();
- while (!is_timeout(start, 10 * MSECOND)) {
- if (!(in_be32(phyregs + GFAR_MIIMMIND_OFFSET) &
- GFAR_MIIMIND_BUSY))
- return 0;
- }
-
- return -EIO;
-}
-
-/*
- * Reads register regnum on the device's PHY through the
- * specified registers. It lowers and raises the read
- * command, and waits for the data to become valid (miimind
- * notvalid bit cleared), and the bus to cease activity (miimind
- * busy bit cleared), and then returns the value
- */
-static uint gfar_local_mdio_read(void __iomem *phyregs, uint phyid, uint regnum)
-{
- uint64_t start;
-
- /* Put the address of the phy, and the register number into MIIMADD */
- out_be32(phyregs + GFAR_MIIMADD_OFFSET, (phyid << 8) | (regnum & 0x1f));
-
- /* Clear the command register, and wait */
- out_be32(phyregs + GFAR_MIIMCOM_OFFSET, 0);
-
- /* Initiate a read command, and wait */
- out_be32(phyregs + GFAR_MIIMCOM_OFFSET, GFAR_MIIM_READ_COMMAND);
-
- start = get_time_ns();
- while (!is_timeout(start, 10 * MSECOND)) {
- if (!(in_be32(phyregs + GFAR_MIIMMIND_OFFSET) &
- (GFAR_MIIMIND_NOTVALID | GFAR_MIIMIND_BUSY)))
- return in_be32(phyregs + GFAR_MIIMSTAT_OFFSET);
- }
-
- return -EIO;
-}
-
static void gfar_configure_serdes(struct gfar_private *priv)
{
- gfar_local_mdio_write(priv->phyregs_sgmii,
+ fsl_local_mdio_write(priv->phyregs_sgmii,
in_be32(priv->regs + GFAR_TBIPA_OFFSET), GFAR_TBI_ANA,
priv->tbiana);
- gfar_local_mdio_write(priv->phyregs_sgmii,
+ fsl_local_mdio_write(priv->phyregs_sgmii,
in_be32(priv->regs + GFAR_TBIPA_OFFSET),
GFAR_TBI_TBICON, GFAR_TBICON_CLK_SELECT);
- gfar_local_mdio_write(priv->phyregs_sgmii,
+ fsl_local_mdio_write(priv->phyregs_sgmii,
in_be32(priv->regs + GFAR_TBIPA_OFFSET), GFAR_TBI_CR,
priv->tbicr);
}
@@ -322,34 +272,22 @@ static void gfar_configure_serdes(struct gfar_private *priv)
static void gfar_init_phy(struct eth_device *dev)
{
struct gfar_private *priv = dev->priv;
- void __iomem *regs = priv->regs;
uint64_t start;
/* Assign a Physical address to the TBI */
- out_be32(regs + GFAR_TBIPA_OFFSET, GFAR_TBIPA_VALUE);
-
- /* Reset MII (due to new addresses) */
- out_be32(priv->phyregs + GFAR_MIIMCFG_OFFSET, GFAR_MIIMCFG_RESET);
- out_be32(priv->phyregs + GFAR_MIIMCFG_OFFSET, GFAR_MIIMCFG_INIT_VALUE);
-
- start = get_time_ns();
- while (!is_timeout(start, 10 * MSECOND)) {
- if (!(in_be32(priv->phyregs + GFAR_MIIMMIND_OFFSET) &
- GFAR_MIIMIND_BUSY))
- break;
- }
+ out_be32(priv->regs + GFAR_TBIPA_OFFSET, GFAR_TBIPA_VALUE);
- gfar_local_mdio_write(priv->phyregs, priv->phyaddr, GFAR_MIIM_CR,
+ fsl_local_mdio_write(priv->phyregs, priv->phyaddr, GFAR_MIIM_CR,
GFAR_MIIM_CR_RST);
start = get_time_ns();
while (!is_timeout(start, 10 * MSECOND)) {
- if (!(gfar_local_mdio_read(priv->phyregs, priv->phyaddr,
+ if (!(fsl_local_mdio_read(priv->phyregs, priv->phyaddr,
GFAR_MIIM_CR) & GFAR_MIIM_CR_RST))
break;
}
- if (in_be32(regs + GFAR_ECNTRL_OFFSET) & GFAR_ECNTRL_SGMII_MODE)
+ if (in_be32(priv->regs + GFAR_ECNTRL_OFFSET) & GFAR_ECNTRL_SGMII_MODE)
gfar_configure_serdes(priv);
}
@@ -432,43 +370,13 @@ static int gfar_recv(struct eth_device *edev)
return 0;
}
-/* Read a MII PHY register. */
-static int gfar_miiphy_read(struct mii_device *mdev, int addr, int reg)
-{
- struct device_d *dev = mdev->parent;
- struct gfar_private *priv = mdev->priv;
- int ret;
-
- ret = gfar_local_mdio_read(priv->phyregs, addr, reg);
- if (ret == -EIO)
- dev_err(dev, "Can't read PHY at address %d\n", addr);
-
- return ret;
-}
-
-/* Write a MII PHY register. */
-static int gfar_miiphy_write(struct mii_device *mdev, int addr, int reg,
- int value)
-{
- struct device_d *dev = mdev->parent;
- struct gfar_private *priv = mdev->priv;
- unsigned short val = value;
- int ret;
-
- ret = gfar_local_mdio_write(priv->phyregs, addr, reg, val);
-
- if (ret)
- dev_err(dev, "Can't write PHY at address %d\n", addr);
-
- return 0;
-}
-
/*
* Initialize device structure. Returns success if
* initialization succeeded.
*/
static int gfar_probe(struct device_d *dev)
{
+ struct device_d *mdiodev;
struct gfar_info_struct *gfar_info = dev->platform_data;
struct eth_device *edev;
struct gfar_private *priv;
@@ -483,8 +391,12 @@ static int gfar_probe(struct device_d *dev)
edev = &priv->edev;
priv->regs = dev_request_mem_region(dev, 0);
- priv->phyregs = dev_request_mem_region(dev, 1);
- priv->phyregs_sgmii = dev_request_mem_region(dev, 2);
+
+#ifdef CONFIG_TSECV2
+ priv->phyregs_sgmii = dev_request_mem_region(dev, 1);
+#else
+ priv->phyregs_sgmii = priv->regs;
+#endif
priv->phyaddr = gfar_info->phyaddr;
priv->tbicr = gfar_info->tbicr;
@@ -514,15 +426,12 @@ static int gfar_probe(struct device_d *dev)
udelay(2);
clrbits_be32(priv->regs + GFAR_MACCFG1_OFFSET, GFAR_MACCFG1_SOFT_RESET);
- priv->miidev.read = gfar_miiphy_read;
- priv->miidev.write = gfar_miiphy_write;
- priv->miidev.priv = priv;
- priv->miidev.parent = dev;
+ mdiodev = get_device_by_name("miidev0");
+ priv->miidev = mdiodev->priv;
+ priv->phyregs = priv->miidev->priv;
gfar_init_phy(edev);
- mii_register(&priv->miidev);
-
return eth_register(edev);
}
diff --git a/drivers/net/gianfar.h b/drivers/net/gianfar.h
index a4ad99e..13c49c4 100644
--- a/drivers/net/gianfar.h
+++ b/drivers/net/gianfar.h
@@ -268,8 +268,7 @@ struct gfar_private {
void __iomem *regs;
void __iomem *phyregs;
void __iomem *phyregs_sgmii;
- struct phy_info *phyinfo;
- struct mii_device miidev;
+ struct mii_device *miidev;
volatile struct txbd8 *txbd;
volatile struct rxbd8 *rxbd;
uint txidx;
--
1.7.1
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 3/5] gianfar update
2012-09-20 16:31 ` [PATCH 3/5] gianfar update Renaud Barbier
@ 2012-09-20 18:30 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-09-20 18:30 UTC (permalink / raw)
To: Renaud Barbier; +Cc: barebox
On 17:31 Thu 20 Sep , Renaud Barbier wrote:
> The gianfar is updated following the addition of the FSL mdio bus support.
> PHY access functions have been removed as well as the reset of the mdio
> bus.
> Also the resource for the External PHY registers has been removed
> from the Ethernet port initialization function.
>
> Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
> ---
> arch/ppc/mach-mpc85xx/eth-devices.c | 14 +--
> arch/ppc/mach-mpc85xx/include/mach/gianfar.h | 2 +
> drivers/net/gianfar.c | 127 ++++----------------------
> drivers/net/gianfar.h | 3 +-
> 4 files changed, 26 insertions(+), 120 deletions(-)
>
> diff --git a/arch/ppc/mach-mpc85xx/eth-devices.c b/arch/ppc/mach-mpc85xx/eth-devices.c
> index c6e8f36..8399f21 100644
> --- a/arch/ppc/mach-mpc85xx/eth-devices.c
> +++ b/arch/ppc/mach-mpc85xx/eth-devices.c
> @@ -29,21 +29,17 @@ int fsl_eth_init(int num, struct gfar_info_struct *gf)
> {
> struct resource *res;
>
> - res = xzalloc(3 * sizeof(struct resource));
> + res = xzalloc(2 * sizeof(struct resource));
> /* TSEC interface registers */
> res[0].start = GFAR_BASE_ADDR + ((num - 1) * 0x1000);
> res[0].end = res[0].start + 0x1000 - 1;
> res[0].flags = IORESOURCE_MEM;
> - /* External PHY access always through eTSEC1 */
> - res[1].start = MDIO_BASE_ADDR;
> - res[1].end = res[1].start + 0x1000 - 1;
> - res[1].flags = IORESOURCE_MEM;
> /* Access to TBI/RTBI interface. */
> - res[2].start = MDIO_BASE_ADDR + ((num - 1) * 0x1000);
> - res[2].end = res[2].start + 0x1000 - 1;
> - res[2].flags = IORESOURCE_MEM;
> + res[1].start = MDIO_BASE_ADDR + ((num - 1) * 0x1000);
> + res[1].end = res[2].start + 0x1000 - 1;
> + res[1].flags = IORESOURCE_MEM;
>
> - add_generic_device_res("gfar", DEVICE_ID_DYNAMIC, res, 3, gf);
> + add_generic_device_res("gfar", DEVICE_ID_DYNAMIC, res, 2, gf);
>
> return 0;
> }
> diff --git a/arch/ppc/mach-mpc85xx/include/mach/gianfar.h b/arch/ppc/mach-mpc85xx/include/mach/gianfar.h
> index ae31638..2c6d58c 100644
> --- a/arch/ppc/mach-mpc85xx/include/mach/gianfar.h
> +++ b/arch/ppc/mach-mpc85xx/include/mach/gianfar.h
> @@ -22,6 +22,8 @@
> * Platform data for the Motorola Triple Speed Ethernet Controller
> */
>
> +#include <asm/fsl_mdio.h>
> +
> struct gfar_info_struct {
> unsigned int phyaddr;
> unsigned int tbiana;
> diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c
> index f8a7cd7..a8033b4 100644
> --- a/drivers/net/gianfar.c
> +++ b/drivers/net/gianfar.c
> @@ -83,7 +83,6 @@ static void gfar_adjust_link(struct eth_device *edev)
> struct gfar_private *priv = edev->priv;
> void __iomem *regs = priv->regs;
> u32 ecntrl, maccfg2;
> - uint32_t status;
>
> priv->link = edev->phydev->link;
> priv->duplexity =edev->phydev->duplex;
> @@ -189,7 +188,7 @@ static int gfar_open(struct eth_device *edev)
> void __iomem *regs = priv->regs;
> int ret;
>
> - ret = phy_device_connect(edev, &priv->miidev, priv->phyaddr,
> + ret = phy_device_connect(edev, priv->miidev, priv->phyaddr,
> gfar_adjust_link, 0, PHY_INTERFACE_MODE_NA);
> if (ret)
> return ret;
> @@ -256,64 +255,15 @@ static int gfar_set_ethaddr(struct eth_device *edev, unsigned char *mac)
> return 0;
> }
>
> -/* Writes the given phy's reg with value, using the specified MDIO regs */
> -static int gfar_local_mdio_write(void __iomem *phyregs, uint addr, uint reg,
> - uint value)
> -{
> - uint64_t start;
> -
> - out_be32(phyregs + GFAR_MIIMADD_OFFSET, (addr << 8) | (reg & 0x1f));
> - out_be32(phyregs + GFAR_MIIMCON_OFFSET, value);
> -
> - start = get_time_ns();
> - while (!is_timeout(start, 10 * MSECOND)) {
> - if (!(in_be32(phyregs + GFAR_MIIMMIND_OFFSET) &
> - GFAR_MIIMIND_BUSY))
> - return 0;
> - }
> -
> - return -EIO;
> -}
> -
> -/*
> - * Reads register regnum on the device's PHY through the
> - * specified registers. It lowers and raises the read
> - * command, and waits for the data to become valid (miimind
> - * notvalid bit cleared), and the bus to cease activity (miimind
> - * busy bit cleared), and then returns the value
> - */
> -static uint gfar_local_mdio_read(void __iomem *phyregs, uint phyid, uint regnum)
> -{
> - uint64_t start;
> -
> - /* Put the address of the phy, and the register number into MIIMADD */
> - out_be32(phyregs + GFAR_MIIMADD_OFFSET, (phyid << 8) | (regnum & 0x1f));
> -
> - /* Clear the command register, and wait */
> - out_be32(phyregs + GFAR_MIIMCOM_OFFSET, 0);
> -
> - /* Initiate a read command, and wait */
> - out_be32(phyregs + GFAR_MIIMCOM_OFFSET, GFAR_MIIM_READ_COMMAND);
> -
> - start = get_time_ns();
> - while (!is_timeout(start, 10 * MSECOND)) {
> - if (!(in_be32(phyregs + GFAR_MIIMMIND_OFFSET) &
> - (GFAR_MIIMIND_NOTVALID | GFAR_MIIMIND_BUSY)))
> - return in_be32(phyregs + GFAR_MIIMSTAT_OFFSET);
> - }
> -
> - return -EIO;
> -}
> -
> static void gfar_configure_serdes(struct gfar_private *priv)
> {
> - gfar_local_mdio_write(priv->phyregs_sgmii,
> + fsl_local_mdio_write(priv->phyregs_sgmii,
> in_be32(priv->regs + GFAR_TBIPA_OFFSET), GFAR_TBI_ANA,
> priv->tbiana);
> - gfar_local_mdio_write(priv->phyregs_sgmii,
> + fsl_local_mdio_write(priv->phyregs_sgmii,
> in_be32(priv->regs + GFAR_TBIPA_OFFSET),
> GFAR_TBI_TBICON, GFAR_TBICON_CLK_SELECT);
> - gfar_local_mdio_write(priv->phyregs_sgmii,
> + fsl_local_mdio_write(priv->phyregs_sgmii,
> in_be32(priv->regs + GFAR_TBIPA_OFFSET), GFAR_TBI_CR,
> priv->tbicr);
> }
> @@ -322,34 +272,22 @@ static void gfar_configure_serdes(struct gfar_private *priv)
> static void gfar_init_phy(struct eth_device *dev)
> {
> struct gfar_private *priv = dev->priv;
> - void __iomem *regs = priv->regs;
> uint64_t start;
>
> /* Assign a Physical address to the TBI */
> - out_be32(regs + GFAR_TBIPA_OFFSET, GFAR_TBIPA_VALUE);
> -
> - /* Reset MII (due to new addresses) */
> - out_be32(priv->phyregs + GFAR_MIIMCFG_OFFSET, GFAR_MIIMCFG_RESET);
> - out_be32(priv->phyregs + GFAR_MIIMCFG_OFFSET, GFAR_MIIMCFG_INIT_VALUE);
> -
> - start = get_time_ns();
> - while (!is_timeout(start, 10 * MSECOND)) {
> - if (!(in_be32(priv->phyregs + GFAR_MIIMMIND_OFFSET) &
> - GFAR_MIIMIND_BUSY))
> - break;
> - }
> + out_be32(priv->regs + GFAR_TBIPA_OFFSET, GFAR_TBIPA_VALUE);
>
> - gfar_local_mdio_write(priv->phyregs, priv->phyaddr, GFAR_MIIM_CR,
> + fsl_local_mdio_write(priv->phyregs, priv->phyaddr, GFAR_MIIM_CR,
> GFAR_MIIM_CR_RST);
>
> start = get_time_ns();
> while (!is_timeout(start, 10 * MSECOND)) {
> - if (!(gfar_local_mdio_read(priv->phyregs, priv->phyaddr,
> + if (!(fsl_local_mdio_read(priv->phyregs, priv->phyaddr,
> GFAR_MIIM_CR) & GFAR_MIIM_CR_RST))
> break;
> }
>
> - if (in_be32(regs + GFAR_ECNTRL_OFFSET) & GFAR_ECNTRL_SGMII_MODE)
> + if (in_be32(priv->regs + GFAR_ECNTRL_OFFSET) & GFAR_ECNTRL_SGMII_MODE)
> gfar_configure_serdes(priv);
> }
>
> @@ -432,43 +370,13 @@ static int gfar_recv(struct eth_device *edev)
> return 0;
> }
>
> -/* Read a MII PHY register. */
> -static int gfar_miiphy_read(struct mii_device *mdev, int addr, int reg)
> -{
> - struct device_d *dev = mdev->parent;
> - struct gfar_private *priv = mdev->priv;
> - int ret;
> -
> - ret = gfar_local_mdio_read(priv->phyregs, addr, reg);
> - if (ret == -EIO)
> - dev_err(dev, "Can't read PHY at address %d\n", addr);
> -
> - return ret;
> -}
> -
> -/* Write a MII PHY register. */
> -static int gfar_miiphy_write(struct mii_device *mdev, int addr, int reg,
> - int value)
> -{
> - struct device_d *dev = mdev->parent;
> - struct gfar_private *priv = mdev->priv;
> - unsigned short val = value;
> - int ret;
> -
> - ret = gfar_local_mdio_write(priv->phyregs, addr, reg, val);
> -
> - if (ret)
> - dev_err(dev, "Can't write PHY at address %d\n", addr);
> -
> - return 0;
> -}
> -
> /*
> * Initialize device structure. Returns success if
> * initialization succeeded.
> */
> static int gfar_probe(struct device_d *dev)
> {
> + struct device_d *mdiodev;
> struct gfar_info_struct *gfar_info = dev->platform_data;
> struct eth_device *edev;
> struct gfar_private *priv;
> @@ -483,8 +391,12 @@ static int gfar_probe(struct device_d *dev)
> edev = &priv->edev;
>
> priv->regs = dev_request_mem_region(dev, 0);
> - priv->phyregs = dev_request_mem_region(dev, 1);
> - priv->phyregs_sgmii = dev_request_mem_region(dev, 2);
> +
> +#ifdef CONFIG_TSECV2
> + priv->phyregs_sgmii = dev_request_mem_region(dev, 1);
> +#else
> + priv->phyregs_sgmii = priv->regs;
> +#endif
>
> priv->phyaddr = gfar_info->phyaddr;
> priv->tbicr = gfar_info->tbicr;
> @@ -514,15 +426,12 @@ static int gfar_probe(struct device_d *dev)
> udelay(2);
> clrbits_be32(priv->regs + GFAR_MACCFG1_OFFSET, GFAR_MACCFG1_SOFT_RESET);
>
> - priv->miidev.read = gfar_miiphy_read;
> - priv->miidev.write = gfar_miiphy_write;
> - priv->miidev.priv = priv;
> - priv->miidev.parent = dev;
> + mdiodev = get_device_by_name("miidev0");
too much fagile register the miidev and pass the device_d* via pdata
Best Regards,
J.
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 4/5] FSL mdio: configuration and build file
2012-09-20 16:31 [PATCH 0/5] gianfar: mdio bus support Renaud Barbier
` (2 preceding siblings ...)
2012-09-20 16:31 ` [PATCH 3/5] gianfar update Renaud Barbier
@ 2012-09-20 16:31 ` Renaud Barbier
2012-09-20 16:31 ` [PATCH 5/5] P2020rdb: eTSEC2 support Renaud Barbier
4 siblings, 0 replies; 14+ messages in thread
From: Renaud Barbier @ 2012-09-20 16:31 UTC (permalink / raw)
To: barebox
The configuration and build files are updated to compile the FSL mdio
support.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
---
drivers/net/Kconfig | 5 +++++
drivers/net/Makefile | 1 +
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 7db2837..c780340 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -128,8 +128,13 @@ config DRIVER_NET_DESIGNWARE_ALTDESCRIPTOR
config DRIVER_NET_GIANFAR
bool "Gianfar Ethernet"
depends on ARCH_MPC85XX
+ select FSL_MDIO
select MIIDEV
+config FSL_MDIO
+ bool
+ default n
+
source "drivers/net/usb/Kconfig"
config DRIVER_NET_MICREL
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 2057963..af19d20 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -15,5 +15,6 @@ obj-$(CONFIG_NET_USB) += usb/
obj-$(CONFIG_DRIVER_NET_TSE) += altera_tse.o
obj-$(CONFIG_DRIVER_NET_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_DRIVER_NET_DESIGNWARE) += designware.o
+obj-$(CONFIG_FSL_MDIO) += fsl_mdio.o
obj-$(CONFIG_DRIVER_NET_GIANFAR) += gianfar.o
obj-$(CONFIG_DRIVER_NET_MICREL) += ksz8864rmn.o
--
1.7.1
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 5/5] P2020rdb: eTSEC2 support
2012-09-20 16:31 [PATCH 0/5] gianfar: mdio bus support Renaud Barbier
` (3 preceding siblings ...)
2012-09-20 16:31 ` [PATCH 4/5] FSL mdio: configuration and build file Renaud Barbier
@ 2012-09-20 16:31 ` Renaud Barbier
4 siblings, 0 replies; 14+ messages in thread
From: Renaud Barbier @ 2012-09-20 16:31 UTC (permalink / raw)
To: barebox
The mdio bus is registered before adding the gianfar interface.
Also the eTSEC2 is configured. Either eTSEC2 or eTSEC3 can now be
used.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
---
arch/ppc/boards/freescale-p2020rdb/p2020rdb.c | 25 +++++++++++++++++++++++--
1 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
index edb9bcd..9d83133 100644
--- a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
+++ b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
@@ -59,9 +59,14 @@
#define SYSCLK_50 50000000
#define SYSCLK_100 100000000
-/* Ethernet. Use eTSEC3 */
+/* eTSEC2 and eTSEC 3 Ethernet port parameters */
static struct gfar_info_struct gfar_info[] = {
{
+ .phyaddr = 0,
+ .tbiana = 0x1a0,
+ .tbicr = 0x9140,
+ },
+ {
.phyaddr = 1,
.tbiana = 0,
.tbicr = 0,
@@ -75,6 +80,9 @@ struct i2c_platform_data i2cplat = {
static int devices_init(void)
{
+ void __iomem *tsecregs;
+ int ix;
+
add_cfi_flash_device(DEVICE_ID_DYNAMIC, CFG_FLASH_BASE, 16 << 20, 0);
add_generic_device("i2c-fsl", 0, NULL, I2C1_BASE_ADDR,
@@ -82,8 +90,21 @@ static int devices_init(void)
add_generic_device("i2c-fsl", 1, NULL, I2C2_BASE_ADDR,
0x100, IORESOURCE_MEM, &i2cplat);
+ /*
+ * Assign TBI physical address early because eTSEC2 has a PHY address
+ * of 0. Otherwise, the PHY on eTSEC2 goes into a bad state.
+ */
+ for (ix = 0; ix < 3; ix++) {
+ tsecregs = (void __iomem *)(GFAR_BASE_ADDR + (ix * 0x1000));
+ out_be32(tsecregs + 0x30, 0x1f);
+ }
+
+ fsl_pq_mdio_init((void *)MDIO_BASE_ADDR);
+
+ /* eTSEC2 */
+ fsl_eth_init(2, &gfar_info[0]);
/* eTSEC3 */
- fsl_eth_init(3, &gfar_info[0]);
+ fsl_eth_init(3, &gfar_info[1]);
devfs_add_partition("nor0", 0xf80000, 0x80000, DEVFS_PARTITION_FIXED,
"self0");
--
1.7.1
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^ permalink raw reply [flat|nested] 14+ messages in thread