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* [PATCH v2 1/3] ARM: Add CLPS711X architecture
@ 2012-10-15 16:26 Alexander Shiyan
  2012-10-15 16:26 ` [PATCH v2 2/3] ARM: clps711x: Add serial driver Alexander Shiyan
                   ` (2 more replies)
  0 siblings, 3 replies; 16+ messages in thread
From: Alexander Shiyan @ 2012-10-15 16:26 UTC (permalink / raw)
  To: barebox

This patch adds new architecture (CLPS711X) into barebox.
The core-logic functionality of the device is built around an ARM720T
processor running at clock speeds up to 90 MHz.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/Kconfig                               |    6 +
 arch/arm/Makefile                              |    1 +
 arch/arm/mach-clps711x/Kconfig                 |   16 ++
 arch/arm/mach-clps711x/Makefile                |    1 +
 arch/arm/mach-clps711x/clock.c                 |  113 ++++++++++
 arch/arm/mach-clps711x/devices.c               |   42 ++++
 arch/arm/mach-clps711x/include/mach/clkdev.h   |    7 +
 arch/arm/mach-clps711x/include/mach/clps711x.h |  283 ++++++++++++++++++++++++
 arch/arm/mach-clps711x/include/mach/devices.h  |    7 +
 arch/arm/mach-clps711x/reset.c                 |   20 ++
 10 files changed, 496 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-clps711x/Kconfig
 create mode 100644 arch/arm/mach-clps711x/Makefile
 create mode 100644 arch/arm/mach-clps711x/clock.c
 create mode 100644 arch/arm/mach-clps711x/devices.c
 create mode 100644 arch/arm/mach-clps711x/include/mach/clkdev.h
 create mode 100644 arch/arm/mach-clps711x/include/mach/clps711x.h
 create mode 100644 arch/arm/mach-clps711x/include/mach/devices.h
 create mode 100644 arch/arm/mach-clps711x/reset.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8278c82..2cf9a57 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -31,6 +31,11 @@ config ARCH_AT91
 	select HAS_DEBUG_LL
 	select HAVE_MACH_ARM_HEAD
 
+config ARCH_CLPS711X
+	bool "Cirrus Logic EP711x/EP721x/EP731x"
+	select CLKDEV_LOOKUP
+	select CPU_32v4T
+
 config ARCH_EP93XX
 	bool "Cirrus Logic EP93xx"
 	select CPU_ARM920T
@@ -99,6 +104,7 @@ endchoice
 
 source arch/arm/cpu/Kconfig
 source arch/arm/mach-at91/Kconfig
+source arch/arm/mach-clps711x/Kconfig
 source arch/arm/mach-ep93xx/Kconfig
 source arch/arm/mach-imx/Kconfig
 source arch/arm/mach-mxs/Kconfig
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 855043a..da80e00 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -52,6 +52,7 @@ AFLAGS   += -include asm/unified.h -msoft-float $(AFLAGS_THUMB2)
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
 machine-$(CONFIG_ARCH_AT91)		:= at91
+machine-$(CONFIG_ARCH_CLPS711X)		:= clps711x
 machine-$(CONFIG_ARCH_EP93XX)		:= ep93xx
 machine-$(CONFIG_ARCH_IMX)		:= imx
 machine-$(CONFIG_ARCH_MXS)		:= mxs
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
new file mode 100644
index 0000000..c5e97ed
--- /dev/null
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -0,0 +1,16 @@
+if ARCH_CLPS711X
+
+choice
+	prompt "Cirrus Logic EP711x/EP721x/EP731x Board Type"
+
+endchoice
+
+config ARCH_TEXT_BASE
+	hex
+	default 0xc0780000
+
+config BAREBOX_MAX_IMAGE_SIZE
+	hex
+	default 0x00080000
+
+endif
diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
new file mode 100644
index 0000000..41012bc
--- /dev/null
+++ b/arch/arm/mach-clps711x/Makefile
@@ -0,0 +1 @@
+obj-y += clock.o devices.o reset.o
diff --git a/arch/arm/mach-clps711x/clock.c b/arch/arm/mach-clps711x/clock.c
new file mode 100644
index 0000000..5cafba9
--- /dev/null
+++ b/arch/arm/mach-clps711x/clock.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <clock.h>
+#include <asm/io.h>
+#include <linux/clkdev.h>
+
+#include <mach/clps711x.h>
+
+struct clk {
+	unsigned long	rate;
+};
+
+static struct clk uart_clk, bus_clk;
+
+uint64_t clocksource_read(void)
+{
+	return ~readw(TC2D);
+}
+
+static struct clocksource cs = {
+	.read	= clocksource_read,
+	.mask	= CLOCKSOURCE_MASK(16),
+};
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+int clk_enable(struct clk *clk)
+{
+	/* Do nothing */
+	return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+	/* Do nothing */
+}
+EXPORT_SYMBOL(clk_disable);
+
+static int clocks_init(void)
+{
+	int osc, ext, pll, cpu, timer;
+	u32 tmp;
+
+	osc = 3686400;
+	ext = 13000000;
+
+	tmp = readl(PLLR) >> 24;
+	if (tmp)
+		pll = (osc * tmp) / 2;
+	else
+		pll = 73728000; /* Default value for old CPUs */
+
+	tmp = readl(SYSFLG2);
+	if (tmp & SYSFLG2_CKMODE) {
+		cpu = ext;
+		bus_clk.rate = cpu;
+	} else {
+		cpu = pll;
+		if (cpu >= 36864000)
+			bus_clk.rate = cpu / 2;
+		else
+			bus_clk.rate = 36864000 / 2;
+	}
+
+	uart_clk.rate = bus_clk.rate / 10;
+
+	if (tmp & SYSFLG2_CKMODE) {
+		tmp = readw(SYSCON2);
+		if (tmp & SYSCON2_OSTB)
+			timer = ext / 26;
+		else
+			timer = 541440;
+	} else
+		timer = cpu / 144;
+
+	tmp = readl(SYSCON1);
+	tmp &= ~SYSCON1_TC2M;	/* Free running mode */
+	tmp |= SYSCON1_TC2S;	/* High frequency source */
+	writel(tmp, SYSCON1);
+
+	clocks_calc_mult_shift(&cs.mult, &cs.shift, timer, NSEC_PER_SEC, 10);
+
+	return init_clock(&cs);
+}
+core_initcall(clocks_init);
+
+static struct clk_lookup clocks_lookups[] = {
+	CLKDEV_CON_ID("bus", &bus_clk),
+	CLKDEV_DEV_ID("clps711x_serial0", &uart_clk),
+	CLKDEV_DEV_ID("clps711x_serial1", &uart_clk),
+};
+
+static int clkdev_init(void)
+{
+	clkdev_add_table(clocks_lookups, ARRAY_SIZE(clocks_lookups));
+
+	return 0;
+}
+postcore_initcall(clkdev_init);
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
new file mode 100644
index 0000000..8433a55
--- /dev/null
+++ b/arch/arm/mach-clps711x/devices.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/io.h>
+
+#include <mach/clps711x.h>
+
+inline void _clps711x_setup_memcfg(int bank, u32 addr, u32 val)
+{
+	u32 tmp = readl(addr);
+
+	tmp &= ~(0xff << (bank * 8));
+	tmp |= val << (bank * 8);
+
+	writel(tmp, addr);
+}
+
+void clps711x_setup_memcfg(int bank, u32 val)
+{
+	switch (bank) {
+	case 0 ... 3:
+		_clps711x_setup_memcfg(bank, MEMCFG1, val);
+		break;
+	case 4 ... 7:
+		_clps711x_setup_memcfg(bank - 4, MEMCFG2, val);
+		break;
+	}
+}
+
+void clps711x_add_uart(unsigned int id)
+{
+	add_generic_device_res("clps711x_serial", id, NULL, 0, NULL);
+}
diff --git a/arch/arm/mach-clps711x/include/mach/clkdev.h b/arch/arm/mach-clps711x/include/mach/clkdev.h
new file mode 100644
index 0000000..9278209
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_CLKDEV_H
+#define __MACH_CLKDEV_H
+
+#define __clk_get(clk)	({ 1; })
+#define __clk_put(clk)	do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
new file mode 100644
index 0000000..ac6edfb
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -0,0 +1,283 @@
+/*
+ *  Hardware definitions for Cirrus Logic CLPS711X
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *  Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __MACH_CLPS711X_H
+#define __MACH_CLPS711X_H
+
+#define CS0_BASE		(0x00000000)
+#define CS1_BASE		(0x10000000)
+#define CS2_BASE		(0x20000000)
+#define CS3_BASE		(0x30000000)
+#define CS4_BASE		(0x40000000)
+#define CS5_BASE		(0x50000000)
+#define CS6_BASE		(0x60000000)
+#define CS7_BASE		(0x70000000)
+#define REGS_BASE		(0x80000000)
+#define SDRAM_BASE		(0xc0000000)
+
+#define PADR			(REGS_BASE + 0x0000)
+#define PBDR			(REGS_BASE + 0x0001)
+#define PCDR			(REGS_BASE + 0x0002)
+#define PDDR			(REGS_BASE + 0x0003)
+#define PADDR			(REGS_BASE + 0x0040)
+#define PBDDR			(REGS_BASE + 0x0041)
+#define PCDDR			(REGS_BASE + 0x0042)
+#define PDDDR			(REGS_BASE + 0x0043)
+#define PEDR			(REGS_BASE + 0x0083)
+#define PEDDR			(REGS_BASE + 0x00c3)
+#define SYSCON1			(REGS_BASE + 0x0100)
+#define SYSFLG1			(REGS_BASE + 0x0140)
+#define MEMCFG1			(REGS_BASE + 0x0180)
+#define MEMCFG2			(REGS_BASE + 0x01c0)
+#define DRFPR			(REGS_BASE + 0x0200)
+#define INTSR1			(REGS_BASE + 0x0240)
+#define INTMR1			(REGS_BASE + 0x0280)
+#define LCDCON			(REGS_BASE + 0x02c0)
+#define TC1D			(REGS_BASE + 0x0300)
+#define TC2D			(REGS_BASE + 0x0340)
+#define RTCDR			(REGS_BASE + 0x0380)
+#define RTCMR			(REGS_BASE + 0x03c0)
+#define PMPCON			(REGS_BASE + 0x0400)
+#define CODR			(REGS_BASE + 0x0440)
+#define UARTDR1			(REGS_BASE + 0x0480)
+#define UBRLCR1			(REGS_BASE + 0x04c0)
+#define SYNCIO			(REGS_BASE + 0x0500)
+#define PALLSW			(REGS_BASE + 0x0540)
+#define PALMSW			(REGS_BASE + 0x0580)
+#define STFCLR			(REGS_BASE + 0x05c0)
+#define BLEOI			(REGS_BASE + 0x0600)
+#define MCEOI			(REGS_BASE + 0x0640)
+#define TEOI			(REGS_BASE + 0x0680)
+#define TC1EOI			(REGS_BASE + 0x06c0)
+#define TC2EOI			(REGS_BASE + 0x0700)
+#define RTCEOI			(REGS_BASE + 0x0740)
+#define UMSEOI			(REGS_BASE + 0x0780)
+#define COEOI			(REGS_BASE + 0x07c0)
+#define HALT			(REGS_BASE + 0x0800)
+#define STDBY			(REGS_BASE + 0x0840)
+
+#define FBADDR			(REGS_BASE + 0x1000)
+#define SYSCON2			(REGS_BASE + 0x1100)
+#define SYSFLG2			(REGS_BASE + 0x1140)
+#define INTSR2			(REGS_BASE + 0x1240)
+#define INTMR2			(REGS_BASE + 0x1280)
+#define UARTDR2			(REGS_BASE + 0x1480)
+#define UBRLCR2			(REGS_BASE + 0x14c0)
+#define SS2DR			(REGS_BASE + 0x1500)
+#define SRXEOF			(REGS_BASE + 0x1600)
+#define SS2POP			(REGS_BASE + 0x16c0)
+#define KBDEOI			(REGS_BASE + 0x1700)
+
+#define DAIR			(REGS_BASE + 0x2000)
+#define DAIDR0			(REGS_BASE + 0x2040)
+#define DAIDR1			(REGS_BASE + 0x2080)
+#define DAIDR2			(REGS_BASE + 0x20c0)
+#define DAISR			(REGS_BASE + 0x2100)
+#define SYSCON3			(REGS_BASE + 0x2200)
+#define INTSR3			(REGS_BASE + 0x2240)
+#define INTMR3			(REGS_BASE + 0x2280)
+#define LEDFLSH			(REGS_BASE + 0x22c0)
+#define SDCONF			(REGS_BASE + 0x2300)
+#define SDRFPR			(REGS_BASE + 0x2340)
+#define UNIQID			(REGS_BASE + 0x2440)
+#define DAI64FS			(REGS_BASE + 0x2600)
+#define PLLW			(REGS_BASE + 0x2610)
+#define PLLR			(REGS_BASE + 0xa5a8)
+#define RANDID0			(REGS_BASE + 0x2700)
+#define RANDID1			(REGS_BASE + 0x2704)
+#define RANDID2			(REGS_BASE + 0x2708)
+#define RANDID3			(REGS_BASE + 0x270c)
+
+/* common bits: SYSCON1 / SYSCON2 */
+#define SYSCON_UARTEN		(1 << 8)
+
+#define SYSCON1_KBDSCAN(x)	((x) & 15)
+#define SYSCON1_KBDSCANMASK	(15)
+#define SYSCON1_TC1M		(1 << 4)
+#define SYSCON1_TC1S		(1 << 5)
+#define SYSCON1_TC2M		(1 << 6)
+#define SYSCON1_TC2S		(1 << 7)
+#define SYSCON1_UART1EN		SYSCON_UARTEN
+#define SYSCON1_BZTOG		(1 << 9)
+#define SYSCON1_BZMOD		(1 << 10)
+#define SYSCON1_DBGEN		(1 << 11)
+#define SYSCON1_LCDEN		(1 << 12)
+#define SYSCON1_CDENTX		(1 << 13)
+#define SYSCON1_CDENRX		(1 << 14)
+#define SYSCON1_SIREN		(1 << 15)
+#define SYSCON1_ADCKSEL(x)	(((x) & 3) << 16)
+#define SYSCON1_ADCKSEL_MASK	(3 << 16)
+#define SYSCON1_EXCKEN		(1 << 18)
+#define SYSCON1_WAKEDIS		(1 << 19)
+#define SYSCON1_IRTXM		(1 << 20)
+
+/* common bits: SYSFLG1 / SYSFLG2 */
+#define SYSFLG_UBUSY		(1 << 11)
+#define SYSFLG_URXFE		(1 << 22)
+#define SYSFLG_UTXFF		(1 << 23)
+
+#define SYSFLG1_MCDR		(1 << 0)
+#define SYSFLG1_DCDET		(1 << 1)
+#define SYSFLG1_WUDR		(1 << 2)
+#define SYSFLG1_WUON		(1 << 3)
+#define SYSFLG1_CTS		(1 << 8)
+#define SYSFLG1_DSR		(1 << 9)
+#define SYSFLG1_DCD		(1 << 10)
+#define SYSFLG1_UBUSY		SYSFLG_UBUSY
+#define SYSFLG1_NBFLG		(1 << 12)
+#define SYSFLG1_RSTFLG		(1 << 13)
+#define SYSFLG1_PFFLG		(1 << 14)
+#define SYSFLG1_CLDFLG		(1 << 15)
+#define SYSFLG1_URXFE		SYSFLG_URXFE
+#define SYSFLG1_UTXFF		SYSFLG_UTXFF
+#define SYSFLG1_CRXFE		(1 << 24)
+#define SYSFLG1_CTXFF		(1 << 25)
+#define SYSFLG1_SSIBUSY		(1 << 26)
+#define SYSFLG1_ID		(1 << 29)
+#define SYSFLG1_VERID(x)	(((x) >> 30) & 3)
+#define SYSFLG1_VERID_MASK	(3 << 30)
+
+#define SYSFLG2_SSRXOF		(1 << 0)
+#define SYSFLG2_RESVAL		(1 << 1)
+#define SYSFLG2_RESFRM		(1 << 2)
+#define SYSFLG2_SS2RXFE		(1 << 3)
+#define SYSFLG2_SS2TXFF		(1 << 4)
+#define SYSFLG2_SS2TXUF		(1 << 5)
+#define SYSFLG2_CKMODE		(1 << 6)
+#define SYSFLG2_UBUSY		SYSFLG_UBUSY
+#define SYSFLG2_URXFE		SYSFLG_URXFE
+#define SYSFLG2_UTXFF		SYSFLG_UTXFF
+
+#define LCDCON_GSEN		(1 << 30)
+#define LCDCON_GSMD		(1 << 31)
+
+#define SYSCON2_SERSEL		(1 << 0)
+#define SYSCON2_KBD6		(1 << 1)
+#define SYSCON2_DRAMZ		(1 << 2)
+#define SYSCON2_KBWEN		(1 << 3)
+#define SYSCON2_SS2TXEN		(1 << 4)
+#define SYSCON2_PCCARD1		(1 << 5)
+#define SYSCON2_PCCARD2		(1 << 6)
+#define SYSCON2_SS2RXEN		(1 << 7)
+#define SYSCON2_UART2EN		SYSCON_UARTEN
+#define SYSCON2_SS2MAEN		(1 << 9)
+#define SYSCON2_OSTB		(1 << 12)
+#define SYSCON2_CLKENSL		(1 << 13)
+#define SYSCON2_BUZFREQ		(1 << 14)
+
+/* common bits: UARTDR1 / UARTDR2 */
+#define UARTDR_FRMERR		(1 << 8)
+#define UARTDR_PARERR		(1 << 9)
+#define UARTDR_OVERR		(1 << 10)
+
+/* common bits: UBRLCR1 / UBRLCR2 */
+#define UBRLCR_BAUD_MASK	((1 << 12) - 1)
+#define UBRLCR_BREAK		(1 << 12)
+#define UBRLCR_PRTEN		(1 << 13)
+#define UBRLCR_EVENPRT		(1 << 14)
+#define UBRLCR_XSTOP		(1 << 15)
+#define UBRLCR_FIFOEN		(1 << 16)
+#define UBRLCR_WRDLEN5		(0 << 17)
+#define UBRLCR_WRDLEN6		(1 << 17)
+#define UBRLCR_WRDLEN7		(2 << 17)
+#define UBRLCR_WRDLEN8		(3 << 17)
+#define UBRLCR_WRDLEN_MASK	(3 << 17)
+
+#define SYNCIO_FRMLEN(x)	(((x) & 0x1f) << 8)
+#define SYNCIO_SMCKEN		(1 << 13)
+#define SYNCIO_TXFRMEN		(1 << 14)
+
+#define DAIR_RESERVED		(0x0404)
+#define DAIR_DAIEN		(1 << 16)
+#define DAIR_ECS		(1 << 17)
+#define DAIR_LCTM		(1 << 19)
+#define DAIR_LCRM		(1 << 20)
+#define DAIR_RCTM		(1 << 21)
+#define DAIR_RCRM		(1 << 22)
+#define DAIR_LBM		(1 << 23)
+
+#define DAIDR2_FIFOEN		(1 << 15)
+#define DAIDR2_FIFOLEFT		(0x0d << 16)
+#define DAIDR2_FIFORIGHT	(0x11 << 16)
+
+#define DAISR_RCTS		(1 << 0)
+#define DAISR_RCRS		(1 << 1)
+#define DAISR_LCTS		(1 << 2)
+#define DAISR_LCRS		(1 << 3)
+#define DAISR_RCTU		(1 << 4)
+#define DAISR_RCRO		(1 << 5)
+#define DAISR_LCTU		(1 << 6)
+#define DAISR_LCRO		(1 << 7)
+#define DAISR_RCNF		(1 << 8)
+#define DAISR_RCNE		(1 << 9)
+#define DAISR_LCNF		(1 << 10)
+#define DAISR_LCNE		(1 << 11)
+#define DAISR_FIFO		(1 << 12)
+
+#define DAI64FS_I2SF64		(1 << 0)
+#define DAI64FS_AUDIOCLKEN	(1 << 1)
+#define DAI64FS_AUDIOCLKSRC	(1 << 2)
+#define DAI64FS_MCLK256EN	(1 << 3)
+#define DAI64FS_LOOPBACK	(1 << 5)
+#define DAI64FS_AUDIV_MASK	(0x7f)
+#define DAI64FS_AUDIV(x)	(((x) & DAI64FS_AUDIV_MASK) << 8)
+
+#define SYSCON3_ADCCON		(1 << 0)
+#define SYSCON3_CLKCTL0		(1 << 1)
+#define SYSCON3_CLKCTL1		(1 << 2)
+#define SYSCON3_DAISEL		(1 << 3)
+#define SYSCON3_ADCCKNSEN	(1 << 4)
+#define SYSCON3_VERSN(x)	(((x) >> 5) & 7)
+#define SYSCON3_VERSN_MASK	(7 << 5)
+#define SYSCON3_FASTWAKE	(1 << 8)
+#define SYSCON3_DAIEN		(1 << 9)
+#define SYSCON3_128FS		SYSCON3_DAIEN
+#define SYSCON3_ENPD67		(1 << 10)
+
+#define SDCONF_ACTIVE		(1 << 10)
+#define SDCONF_CLKCTL		(1 << 9)
+#define SDCONF_WIDTH_4		(0 << 7)
+#define SDCONF_WIDTH_8		(1 << 7)
+#define SDCONF_WIDTH_16		(2 << 7)
+#define SDCONF_WIDTH_32		(3 << 7)
+#define SDCONF_SIZE_16		(0 << 5)
+#define SDCONF_SIZE_64		(1 << 5)
+#define SDCONF_SIZE_128		(2 << 5)
+#define SDCONF_SIZE_256		(3 << 5)
+#define SDCONF_CASLAT_2		(2)
+#define SDCONF_CASLAT_3		(3)
+
+#define MEMCFG_BUS_WIDTH_32	(1)
+#define MEMCFG_BUS_WIDTH_16	(0)
+#define MEMCFG_BUS_WIDTH_8	(3)
+
+#define MEMCFG_SQAEN		(1 << 6)
+#define MEMCFG_CLKENB		(1 << 7)
+
+#define MEMCFG_WAITSTATE_8_3	(0 << 2)
+#define MEMCFG_WAITSTATE_7_3	(1 << 2)
+#define MEMCFG_WAITSTATE_6_3	(2 << 2)
+#define MEMCFG_WAITSTATE_5_3	(3 << 2)
+#define MEMCFG_WAITSTATE_4_2	(4 << 2)
+#define MEMCFG_WAITSTATE_3_2	(5 << 2)
+#define MEMCFG_WAITSTATE_2_2	(6 << 2)
+#define MEMCFG_WAITSTATE_1_2	(7 << 2)
+#define MEMCFG_WAITSTATE_8_1	(8 << 2)
+#define MEMCFG_WAITSTATE_7_1	(9 << 2)
+#define MEMCFG_WAITSTATE_6_1	(10 << 2)
+#define MEMCFG_WAITSTATE_5_1	(11 << 2)
+#define MEMCFG_WAITSTATE_4_0	(12 << 2)
+#define MEMCFG_WAITSTATE_3_0	(13 << 2)
+#define MEMCFG_WAITSTATE_2_0	(14 << 2)
+#define MEMCFG_WAITSTATE_1_0	(15 << 2)
+
+#endif
diff --git a/arch/arm/mach-clps711x/include/mach/devices.h b/arch/arm/mach-clps711x/include/mach/devices.h
new file mode 100644
index 0000000..18a251a
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/devices.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_DEVICES_H
+#define __MACH_DEVICES_H
+
+void clps711x_setup_memcfg(int bank, u32 val);
+void clps711x_add_uart(unsigned int id);
+
+#endif
diff --git a/arch/arm/mach-clps711x/reset.c b/arch/arm/mach-clps711x/reset.c
new file mode 100644
index 0000000..312fc9e
--- /dev/null
+++ b/arch/arm/mach-clps711x/reset.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/barebox-arm-head.h>
+
+void __noreturn reset_cpu(unsigned long addr)
+{
+	common_reset();
+
+	asm("mov pc, #0");
+
+	hang();
+}
-- 
1.7.8.6


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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [PATCH v2 2/3] ARM: clps711x: Add serial driver
  2012-10-15 16:26 [PATCH v2 1/3] ARM: Add CLPS711X architecture Alexander Shiyan
@ 2012-10-15 16:26 ` Alexander Shiyan
  2012-10-15 17:58   ` Jean-Christophe PLAGNIOL-VILLARD
  2012-10-15 16:26 ` [PATCH v2 3/3] ARM: clps711x: Add generic board support (CLEP7212) Alexander Shiyan
  2012-10-15 17:54 ` [PATCH v2 1/3] ARM: Add CLPS711X architecture Jean-Christophe PLAGNIOL-VILLARD
  2 siblings, 1 reply; 16+ messages in thread
From: Alexander Shiyan @ 2012-10-15 16:26 UTC (permalink / raw)
  To: barebox


Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 drivers/serial/Kconfig           |    5 ++
 drivers/serial/Makefile          |    1 +
 drivers/serial/serial_clps711x.c |  118 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 124 insertions(+), 0 deletions(-)
 create mode 100644 drivers/serial/serial_clps711x.c

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 7eb96ed..02bc8bf 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -43,6 +43,11 @@ config DRIVER_SERIAL_BLACKFIN
 	default y
 	bool "Blackfin serial driver"
 
+config DRIVER_SERIAL_CLPS711X
+	depends on ARCH_CLPS711X
+	default y
+	bool "CLPS711X serial driver"
+
 config DRIVER_SERIAL_ALTERA
 	depends on NIOS2
 	default y
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index e2d56b9..e6f1e22 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_DRIVER_SERIAL_NETX)		+= serial_netx.o
 obj-$(CONFIG_DRIVER_SERIAL_LINUX_CONSOLE)	+= linux_console.o
 obj-$(CONFIG_DRIVER_SERIAL_MPC5XXX)		+= serial_mpc5xxx.o
 obj-$(CONFIG_DRIVER_SERIAL_BLACKFIN)		+= serial_blackfin.o
+obj-$(CONFIG_DRIVER_SERIAL_CLPS711X)		+= serial_clps711x.o
 obj-$(CONFIG_DRIVER_SERIAL_NS16550)		+= serial_ns16550.o
 obj-$(CONFIG_DRIVER_SERIAL_PL010)		+= serial_pl010.o
 obj-$(CONFIG_DRIVER_SERIAL_S3C)			+= serial_s3c.o
diff --git a/drivers/serial/serial_clps711x.c b/drivers/serial/serial_clps711x.c
new file mode 100644
index 0000000..462ba9f
--- /dev/null
+++ b/drivers/serial/serial_clps711x.c
@@ -0,0 +1,118 @@
+/*
+ * Simple CLPS711X serial driver
+ *
+ * (C) Copyright 2012 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <linux/clk.h>
+
+#include <mach/clps711x.h>
+
+#define UBRLCR(x)	(UBRLCR1 + (x) * 0x1000)
+#define SYSCON(x)	(SYSCON1 + (x) * 0x1000)
+#define SYSFLG(x)	(SYSFLG1 + (x) * 0x1000)
+#define UARTDR(x)	(UARTDR1 + (x) * 0x1000)
+
+static int clps711x_setbaudrate(struct console_device *cdev, int baudrate)
+{
+	int divisor;
+	u32 tmp;
+
+	divisor = (clk_get_rate(cdev->dev->priv) / 16) / baudrate;
+
+	tmp = readl(UBRLCR(cdev->dev->id)) & ~UBRLCR_BAUD_MASK;
+	tmp |= divisor - 1;
+	writel(tmp, UBRLCR(cdev->dev->id));
+
+	return 0;
+}
+
+static void clps711x_init_port(struct console_device *cdev)
+{
+	u32 tmp;
+
+	/* Disable the UART */
+	writel(readl(SYSCON(cdev->dev->id)) & ~SYSCON_UARTEN,
+	       SYSCON(cdev->dev->id));
+
+	/* Setup Line Control Register */
+	tmp = readl(UBRLCR(cdev->dev->id)) & UBRLCR_BAUD_MASK;
+	tmp |= UBRLCR_FIFOEN | UBRLCR_WRDLEN8; /* FIFO on, 8N1 mode */
+	writel(tmp, UBRLCR(cdev->dev->id));
+
+	/* Set default baudrate on initialization */
+	clps711x_setbaudrate(cdev, CONFIG_BAUDRATE);
+
+	/* Enable the UART */
+	writel(readl(SYSCON(cdev->dev->id)) | SYSCON_UARTEN,
+	       SYSCON(cdev->dev->id));
+}
+
+static void clps711x_putc(struct console_device *cdev, char c)
+{
+	/* Wait until there is space in the FIFO */
+	while (readl(SYSFLG(cdev->dev->id)) & SYSFLG_UTXFF) {
+	}
+
+	/* Send the character */
+	writew(c, UARTDR(cdev->dev->id));
+}
+
+static int clps711x_getc(struct console_device *cdev)
+{
+	u16 data;
+
+	/* Wait until there is data in the FIFO */
+	while (readl(SYSFLG(cdev->dev->id)) & SYSFLG_URXFE) {
+	}
+
+	data = readw(UARTDR(cdev->dev->id));
+
+	/* Check for an error flag */
+	if (data & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR))
+		return -1;
+
+	return (int)data;
+}
+
+static int clps711x_tstc(struct console_device *cdev)
+{
+	return !(readl(SYSFLG(cdev->dev->id)) & SYSFLG_URXFE);
+}
+
+static int clps711x_probe(struct device_d *dev)
+{
+	struct console_device *cdev = xzalloc(sizeof(struct console_device));
+
+	dev->priv = clk_get(dev, NULL);
+	BUG_ON(!dev->priv);
+
+	cdev->dev	= dev;
+	cdev->f_caps	= CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
+	cdev->tstc	= clps711x_tstc;
+	cdev->putc	= clps711x_putc;
+	cdev->getc	= clps711x_getc;
+	cdev->setbrg	= clps711x_setbaudrate;
+	clps711x_init_port(cdev);
+
+	return console_register(cdev);
+}
+
+static struct driver_d clps711x_driver = {
+	.name	= "clps711x_serial",
+	.probe	= clps711x_probe,
+};
+
+static int clps711x_init(void)
+{
+	return platform_driver_register(&clps711x_driver);
+}
+console_initcall(clps711x_init);
-- 
1.7.8.6


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [PATCH v2 3/3] ARM: clps711x: Add generic board support (CLEP7212)
  2012-10-15 16:26 [PATCH v2 1/3] ARM: Add CLPS711X architecture Alexander Shiyan
  2012-10-15 16:26 ` [PATCH v2 2/3] ARM: clps711x: Add serial driver Alexander Shiyan
@ 2012-10-15 16:26 ` Alexander Shiyan
  2012-10-15 18:03   ` Jean-Christophe PLAGNIOL-VILLARD
  2012-10-15 17:54 ` [PATCH v2 1/3] ARM: Add CLPS711X architecture Jean-Christophe PLAGNIOL-VILLARD
  2 siblings, 1 reply; 16+ messages in thread
From: Alexander Shiyan @ 2012-10-15 16:26 UTC (permalink / raw)
  To: barebox

This patch adds generic board support (CLEP7212, Linux ARM ID=91)
for CLPS711X-target.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/Makefile                               |    1 +
 arch/arm/boards/clep7212/Makefile               |    1 +
 arch/arm/boards/clep7212/clep7212.c             |   64 +++++++++++++++++++++++
 arch/arm/boards/clep7212/config.h               |    4 ++
 arch/arm/boards/clep7212/env/bin/mtdparts-add   |   21 +++++++
 arch/arm/boards/clep7212/env/boot/nor           |    9 +++
 arch/arm/boards/clep7212/env/init/automount     |   12 ++++
 arch/arm/boards/clep7212/env/init/bootargs-base |    8 +++
 arch/arm/boards/clep7212/env/init/general       |   12 ++++
 arch/arm/boards/clep7212/env/init/hostname      |    8 +++
 arch/arm/boards/clep7212/lowlevel.c             |   56 ++++++++++++++++++++
 arch/arm/configs/clps711x_defconfig             |   42 +++++++++++++++
 arch/arm/mach-clps711x/Kconfig                  |    9 +++
 13 files changed, 247 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boards/clep7212/Makefile
 create mode 100644 arch/arm/boards/clep7212/clep7212.c
 create mode 100644 arch/arm/boards/clep7212/config.h
 create mode 100644 arch/arm/boards/clep7212/env/bin/mtdparts-add
 create mode 100644 arch/arm/boards/clep7212/env/boot/nor
 create mode 100644 arch/arm/boards/clep7212/env/init/automount
 create mode 100644 arch/arm/boards/clep7212/env/init/bootargs-base
 create mode 100644 arch/arm/boards/clep7212/env/init/general
 create mode 100644 arch/arm/boards/clep7212/env/init/hostname
 create mode 100644 arch/arm/boards/clep7212/lowlevel.c
 create mode 100644 arch/arm/configs/clps711x_defconfig

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index da80e00..05f9943 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -76,6 +76,7 @@ board-$(CONFIG_MACH_AT91SAM9G10EK)		:= at91sam9261ek
 board-$(CONFIG_MACH_AT91SAM9G20EK)		:= at91sam9260ek
 board-$(CONFIG_MACH_AT91SAM9X5EK)		:= at91sam9x5ek
 board-$(CONFIG_MACH_AT91SAM9M10G45EK)		:= at91sam9m10g45ek
+board-$(CONFIG_MACH_CLEP7212)			:= clep7212
 board-$(CONFIG_MACH_DSS11)			:= dss11
 board-$(CONFIG_MACH_EDB9301)			:= edb93xx
 board-$(CONFIG_MACH_EDB9302)			:= edb93xx
diff --git a/arch/arm/boards/clep7212/Makefile b/arch/arm/boards/clep7212/Makefile
new file mode 100644
index 0000000..7e58f10
--- /dev/null
+++ b/arch/arm/boards/clep7212/Makefile
@@ -0,0 +1 @@
+obj-y += clep7212.o lowlevel.o
diff --git a/arch/arm/boards/clep7212/clep7212.c b/arch/arm/boards/clep7212/clep7212.c
new file mode 100644
index 0000000..1d5828d
--- /dev/null
+++ b/arch/arm/boards/clep7212/clep7212.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <init.h>
+#include <partition.h>
+#include <io.h>
+#include <sizes.h>
+#include <asm/armlinux.h>
+#include <generated/mach-types.h>
+
+#include <mach/clps711x.h>
+#include <mach/devices.h>
+
+static int clps711x_mem_init(void)
+{
+	ulong memsize = get_ram_size((ulong *)SDRAM_BASE, SZ_32M);
+
+	arm_add_mem_device("ram0", SDRAM_BASE, memsize);
+
+	return 0;
+}
+mem_initcall(clps711x_mem_init);
+
+static int clps711x_devices_init(void)
+{
+	u32 serial_h = 0, serial_l = readl(UNIQID);
+
+	/* Setup Chipselects */
+	clps711x_setup_memcfg(0, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_16);
+	clps711x_setup_memcfg(1, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_8);
+	clps711x_setup_memcfg(2, MEMCFG_WAITSTATE_8_3 | MEMCFG_BUS_WIDTH_16 |
+			      MEMCFG_CLKENB);
+	clps711x_setup_memcfg(3, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_32);
+
+	add_cfi_flash_device(0, CS0_BASE, SZ_32M, 0);
+
+	devfs_add_partition("nor0", 0x00000, SZ_256K, DEVFS_PARTITION_FIXED,
+			    "self0");
+	devfs_add_partition("nor0", SZ_256K, SZ_256K, DEVFS_PARTITION_FIXED,
+			    "env0");
+
+	armlinux_set_bootparams((void *)SDRAM_BASE + 0x100);
+	armlinux_set_architecture(MACH_TYPE_CLEP7212);
+	armlinux_set_serial(((u64)serial_h << 32) | serial_l);
+
+	return 0;
+}
+device_initcall(clps711x_devices_init);
+
+static int clps711x_console_init(void)
+{
+	clps711x_add_uart(0);
+
+	return 0;
+}
+console_initcall(clps711x_console_init);
diff --git a/arch/arm/boards/clep7212/config.h b/arch/arm/boards/clep7212/config.h
new file mode 100644
index 0000000..6ae9a40
--- /dev/null
+++ b/arch/arm/boards/clep7212/config.h
@@ -0,0 +1,4 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#endif  /* __CONFIG_H */
diff --git a/arch/arm/boards/clep7212/env/bin/mtdparts-add b/arch/arm/boards/clep7212/env/bin/mtdparts-add
new file mode 100644
index 0000000..ef1bc02
--- /dev/null
+++ b/arch/arm/boards/clep7212/env/bin/mtdparts-add
@@ -0,0 +1,21 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+	init-menu-add-entry "$0" "Partitions"
+	exit
+fi
+
+norparts="256k(barebox),256k(bareboxenv),3584k(kernel),-(root)"
+ramparts="-(ramdisk)"
+
+if [ -e /dev/nor0 ]; then
+	addpart -n /dev/nor0 "${norparts}"
+
+	global linux.mtdparts.nor
+	global.linux.mtdparts.nor="physmap-flash.0:${norparts}"
+else
+	echo "NOR Flash not found."
+fi
+
+global linux.mtdparts.ram
+global.linux.mtdparts.ram="mtd-ram.0:${ramparts}"
diff --git a/arch/arm/boards/clep7212/env/boot/nor b/arch/arm/boards/clep7212/env/boot/nor
new file mode 100644
index 0000000..5cf1e15
--- /dev/null
+++ b/arch/arm/boards/clep7212/env/boot/nor
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+	boot-menu-add-entry "$0" "NOR Flash"
+	exit
+fi
+
+global.bootm.image="/dev/kernel"
+global.linux.bootargs.dyn.root="root=/dev/mtdblock4 ro"
diff --git a/arch/arm/boards/clep7212/env/init/automount b/arch/arm/boards/clep7212/env/init/automount
new file mode 100644
index 0000000..2ceefc3
--- /dev/null
+++ b/arch/arm/boards/clep7212/env/init/automount
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+	init-menu-add-entry "$0" "Automountpoints"
+	exit
+fi
+
+mkdir -p /mnt/disk0
+automount -d /mnt/disk0 '[ -e /dev/disk0.0 ] && mount /dev/disk0.0 /mnt/disk0'
+
+mkdir -p /mnt/disk1
+automount -d /mnt/disk1 '[ -e /dev/disk1.0 ] && mount /dev/disk1.0 /mnt/disk1'
diff --git a/arch/arm/boards/clep7212/env/init/bootargs-base b/arch/arm/boards/clep7212/env/init/bootargs-base
new file mode 100644
index 0000000..ec08e39
--- /dev/null
+++ b/arch/arm/boards/clep7212/env/init/bootargs-base
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+	init-menu-add-entry "$0" "Base bootargs"
+	exit
+fi
+
+global.linux.bootargs.base="earlyprintk console=ttyCL0,57600n8"
diff --git a/arch/arm/boards/clep7212/env/init/general b/arch/arm/boards/clep7212/env/init/general
new file mode 100644
index 0000000..77e6a59
--- /dev/null
+++ b/arch/arm/boards/clep7212/env/init/general
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+	init-menu-add-entry "$0" "general config settings"
+	exit
+fi
+
+global.user=barebox
+global.autoboot_timeout=2
+global.boot.default=nor
+
+/env/bin/mtdparts-add
diff --git a/arch/arm/boards/clep7212/env/init/hostname b/arch/arm/boards/clep7212/env/init/hostname
new file mode 100644
index 0000000..684ee63
--- /dev/null
+++ b/arch/arm/boards/clep7212/env/init/hostname
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+	init-menu-add-entry "$0" "hostname"
+	exit
+fi
+
+global.hostname=clep7212
diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
new file mode 100644
index 0000000..9b7e241
--- /dev/null
+++ b/arch/arm/boards/clep7212/lowlevel.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <init.h>
+
+#include <asm/io.h>
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+
+#include <mach/clps711x.h>
+
+#define MAIN_CLOCK		3686400
+#define CPU_SPEED		92160000
+#define BUS_SPEED		(CPU_SPEED / 2)
+
+#define PLL_VALUE		(((CPU_SPEED * 2) / MAIN_CLOCK) << 24)
+#define SDRAM_REFRESH_RATE	(64 * (BUS_SPEED / (8192 * 1000)))
+
+void __naked __bare_init reset(void)
+{
+	u32 tmp;
+
+	common_reset();
+
+	/* Setup base clock */
+	writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3);
+	asm("nop");
+
+	/* Setup PLL */
+	writel(PLL_VALUE, PLLW);
+	asm("nop");
+
+	/* CLKEN select, SDRAM width=32 */
+	writel(SYSCON2_CLKENSL, SYSCON2);
+
+	/* Enable SDQM pins */
+	tmp = readl(SYSCON3);
+	tmp &= ~SYSCON3_ENPD67;
+	writel(tmp, SYSCON3);
+
+	/* Setup Refresh Rate (64ms 8K Blocks) */
+	writel(SDRAM_REFRESH_RATE, SDRFPR);
+
+	/* Setup SDRAM (32MB, 16Bit*2, CAS=3) */
+	writel(SDCONF_CASLAT_3 | SDCONF_SIZE_256 | SDCONF_WIDTH_16 |
+	       SDCONF_CLKCTL | SDCONF_ACTIVE, SDCONF);
+
+	board_init_lowlevel_return();
+}
diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
new file mode 100644
index 0000000..cf2b3b6
--- /dev/null
+++ b/arch/arm/configs/clps711x_defconfig
@@ -0,0 +1,42 @@
+CONFIG_ARCH_CLPS711X=y
+CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+# CONFIG_MEMINFO is not set
+CONFIG_TEXT_BASE=0xc0780000
+CONFIG_EXPERIMENTAL=y
+CONFIG_BAUDRATE=57600
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_DEFAULT_ENVIRONMENT_COMPRESSED_LZO=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/clep7212/env"
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_BOOTU is not set
+CONFIG_CMD_RESET=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+# CONFIG_SPI is not set
+CONFIG_DRIVER_CFI=y
+# CONFIG_DRIVER_CFI_BANK_WIDTH_1 is not set
+# CONFIG_DRIVER_CFI_BANK_WIDTH_4 is not set
+CONFIG_MTD=y
+CONFIG_DISK=y
+CONFIG_DISK_WRITE=y
+CONFIG_DISK_INTF_PLATFORM_IDE=y
+CONFIG_FS_CRAMFS=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index c5e97ed..f531587 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -3,8 +3,17 @@ if ARCH_CLPS711X
 choice
 	prompt "Cirrus Logic EP711x/EP721x/EP731x Board Type"
 
+config MACH_CLEP7212
+	bool "Cirrus Logic CLEP7212"
+	select MACH_HAS_LOWLEVEL_INIT
+	help
+	  Boards based on the Cirrus Logic 7212/7312 CPU
+
 endchoice
 
+config BOARDINFO
+	default "Cirrus Logic CLEP7212"
+
 config ARCH_TEXT_BASE
 	hex
 	default 0xc0780000
-- 
1.7.8.6


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^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH v2 1/3] ARM: Add CLPS711X architecture
  2012-10-15 16:26 [PATCH v2 1/3] ARM: Add CLPS711X architecture Alexander Shiyan
  2012-10-15 16:26 ` [PATCH v2 2/3] ARM: clps711x: Add serial driver Alexander Shiyan
  2012-10-15 16:26 ` [PATCH v2 3/3] ARM: clps711x: Add generic board support (CLEP7212) Alexander Shiyan
@ 2012-10-15 17:54 ` Jean-Christophe PLAGNIOL-VILLARD
  2012-10-15 18:56   ` Alexander Shiyan
  2 siblings, 1 reply; 16+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-10-15 17:54 UTC (permalink / raw)
  To: Alexander Shiyan; +Cc: barebox

On 20:26 Mon 15 Oct     , Alexander Shiyan wrote:
> This patch adds new architecture (CLPS711X) into barebox.
> The core-logic functionality of the device is built around an ARM720T
> processor running at clock speeds up to 90 MHz.
> 
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> ---
>  arch/arm/Kconfig                               |    6 +
>  arch/arm/Makefile                              |    1 +
>  arch/arm/mach-clps711x/Kconfig                 |   16 ++
>  arch/arm/mach-clps711x/Makefile                |    1 +
>  arch/arm/mach-clps711x/clock.c                 |  113 ++++++++++
>  arch/arm/mach-clps711x/devices.c               |   42 ++++
>  arch/arm/mach-clps711x/include/mach/clkdev.h   |    7 +
>  arch/arm/mach-clps711x/include/mach/clps711x.h |  283 ++++++++++++++++++++++++
>  arch/arm/mach-clps711x/include/mach/devices.h  |    7 +
>  arch/arm/mach-clps711x/reset.c                 |   20 ++
>  10 files changed, 496 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-clps711x/Kconfig
>  create mode 100644 arch/arm/mach-clps711x/Makefile
>  create mode 100644 arch/arm/mach-clps711x/clock.c
>  create mode 100644 arch/arm/mach-clps711x/devices.c
>  create mode 100644 arch/arm/mach-clps711x/include/mach/clkdev.h
>  create mode 100644 arch/arm/mach-clps711x/include/mach/clps711x.h
>  create mode 100644 arch/arm/mach-clps711x/include/mach/devices.h
>  create mode 100644 arch/arm/mach-clps711x/reset.c
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 8278c82..2cf9a57 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -31,6 +31,11 @@ config ARCH_AT91
>  	select HAS_DEBUG_LL
>  	select HAVE_MACH_ARM_HEAD
>  
> +config ARCH_CLPS711X
> +	bool "Cirrus Logic EP711x/EP721x/EP731x"
> +	select CLKDEV_LOOKUP
> +	select CPU_32v4T
> +
>  config ARCH_EP93XX
>  	bool "Cirrus Logic EP93xx"
>  	select CPU_ARM920T
> @@ -99,6 +104,7 @@ endchoice
>  
>  source arch/arm/cpu/Kconfig
>  source arch/arm/mach-at91/Kconfig
> +source arch/arm/mach-clps711x/Kconfig
>  source arch/arm/mach-ep93xx/Kconfig
>  source arch/arm/mach-imx/Kconfig
>  source arch/arm/mach-mxs/Kconfig
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 855043a..da80e00 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -52,6 +52,7 @@ AFLAGS   += -include asm/unified.h -msoft-float $(AFLAGS_THUMB2)
>  # Machine directory name.  This list is sorted alphanumerically
>  # by CONFIG_* macro name.
>  machine-$(CONFIG_ARCH_AT91)		:= at91
> +machine-$(CONFIG_ARCH_CLPS711X)		:= clps711x
>  machine-$(CONFIG_ARCH_EP93XX)		:= ep93xx
>  machine-$(CONFIG_ARCH_IMX)		:= imx
>  machine-$(CONFIG_ARCH_MXS)		:= mxs
> diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
> new file mode 100644
> index 0000000..c5e97ed
> --- /dev/null
> +++ b/arch/arm/mach-clps711x/Kconfig
> @@ -0,0 +1,16 @@
> +if ARCH_CLPS711X
> +
> +choice
> +	prompt "Cirrus Logic EP711x/EP721x/EP731x Board Type"
> +
> +endchoice
> +
> +config ARCH_TEXT_BASE
> +	hex
> +	default 0xc0780000
> +
> +config BAREBOX_MAX_IMAGE_SIZE
> +	hex
> +	default 0x00080000
> +
> +endif
> diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
> new file mode 100644
> index 0000000..41012bc
> --- /dev/null
> +++ b/arch/arm/mach-clps711x/Makefile
> @@ -0,0 +1 @@
> +obj-y += clock.o devices.o reset.o
> diff --git a/arch/arm/mach-clps711x/clock.c b/arch/arm/mach-clps711x/clock.c
> new file mode 100644
> index 0000000..5cafba9
> --- /dev/null
> +++ b/arch/arm/mach-clps711x/clock.c
> @@ -0,0 +1,113 @@
> +/*
> + * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +#include <clock.h>
> +#include <asm/io.h>
> +#include <linux/clkdev.h>
split the code in 2
 - clock
 - clocksource in drivers/clocksource
 and cs as a driver
> +
> +#include <mach/clps711x.h>
> +
> +struct clk {
> +	unsigned long	rate;
> +};
> +
> +static struct clk uart_clk, bus_clk;
> +
> +uint64_t clocksource_read(void)
> +{
> +	return ~readw(TC2D);
> +}
> +
> +static struct clocksource cs = {
> +	.read	= clocksource_read,
> +	.mask	= CLOCKSOURCE_MASK(16),
> +};
> +
> +unsigned long clk_get_rate(struct clk *clk)
> +{
> +	return clk->rate;
> +}
> +EXPORT_SYMBOL(clk_get_rate);
> +
> +int clk_enable(struct clk *clk)
> +{
> +	/* Do nothing */
> +	return 0;
> +}
> +EXPORT_SYMBOL(clk_enable);
> +
> +void clk_disable(struct clk *clk)
> +{
> +	/* Do nothing */
> +}
> +EXPORT_SYMBOL(clk_disable);
> +
> +static int clocks_init(void)
> +{
> +	int osc, ext, pll, cpu, timer;
> +	u32 tmp;
> +
> +	osc = 3686400;
> +	ext = 13000000;
creaet a clock for this
> +
> +	tmp = readl(PLLR) >> 24;
> +	if (tmp)
> +		pll = (osc * tmp) / 2;
> +	else
> +		pll = 73728000; /* Default value for old CPUs */
ditto etc...
> +
> +	tmp = readl(SYSFLG2);
> +	if (tmp & SYSFLG2_CKMODE) {
> +		cpu = ext;
> +		bus_clk.rate = cpu;
> +	} else {
> +		cpu = pll;
> +		if (cpu >= 36864000)
> +			bus_clk.rate = cpu / 2;
> +		else
> +			bus_clk.rate = 36864000 / 2;
> +	}
> +
> +	uart_clk.rate = bus_clk.rate / 10;
> +
> +	if (tmp & SYSFLG2_CKMODE) {
> +		tmp = readw(SYSCON2);
> +		if (tmp & SYSCON2_OSTB)
> +			timer = ext / 26;
> +		else
> +			timer = 541440;
> +	} else
> +		timer = cpu / 144;
> +
> +	tmp = readl(SYSCON1);
> +	tmp &= ~SYSCON1_TC2M;	/* Free running mode */
> +	tmp |= SYSCON1_TC2S;	/* High frequency source */
> +	writel(tmp, SYSCON1);
> +
> +	clocks_calc_mult_shift(&cs.mult, &cs.shift, timer, NSEC_PER_SEC, 10);
> +
> +	return init_clock(&cs);
> +}
> +core_initcall(clocks_init);
> +
> +static struct clk_lookup clocks_lookups[] = {
> +	CLKDEV_CON_ID("bus", &bus_clk),
> +	CLKDEV_DEV_ID("clps711x_serial0", &uart_clk),
> +	CLKDEV_DEV_ID("clps711x_serial1", &uart_clk),
> +};
> +
> +static int clkdev_init(void)
> +{
> +	clkdev_add_table(clocks_lookups, ARRAY_SIZE(clocks_lookups));
> +
> +	return 0;
> +}
> +postcore_initcall(clkdev_init);
> diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
> new file mode 100644
> index 0000000..8433a55
> --- /dev/null
> +++ b/arch/arm/mach-clps711x/devices.c
> @@ -0,0 +1,42 @@
> +/*
> + * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +
> +#include <asm/io.h>
> +
> +#include <mach/clps711x.h>
> +
> +inline void _clps711x_setup_memcfg(int bank, u32 addr, u32 val)
> +{
> +	u32 tmp = readl(addr);
> +
> +	tmp &= ~(0xff << (bank * 8));
> +	tmp |= val << (bank * 8);
> +
> +	writel(tmp, addr);
> +}
> +
> +void clps711x_setup_memcfg(int bank, u32 val)
> +{
> +	switch (bank) {
> +	case 0 ... 3:
> +		_clps711x_setup_memcfg(bank, MEMCFG1, val);
> +		break;
> +	case 4 ... 7:
> +		_clps711x_setup_memcfg(bank - 4, MEMCFG2, val);
> +		break;
> +	}
> +}
> +
> +void clps711x_add_uart(unsigned int id)
> +{
> +	add_generic_device_res("clps711x_serial", id, NULL, 0, NULL);
where is the base address address?
where is the check on the id?

Best Regards,
J.

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^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/3] ARM: clps711x: Add serial driver
  2012-10-15 16:26 ` [PATCH v2 2/3] ARM: clps711x: Add serial driver Alexander Shiyan
@ 2012-10-15 17:58   ` Jean-Christophe PLAGNIOL-VILLARD
  2012-10-15 19:00     ` Alexander Shiyan
  2012-10-15 21:58     ` Sascha Hauer
  0 siblings, 2 replies; 16+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-10-15 17:58 UTC (permalink / raw)
  To: Alexander Shiyan; +Cc: barebox

On 20:26 Mon 15 Oct     , Alexander Shiyan wrote:
> 
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> ---
>  drivers/serial/Kconfig           |    5 ++
>  drivers/serial/Makefile          |    1 +
>  drivers/serial/serial_clps711x.c |  118 ++++++++++++++++++++++++++++++++++++++
>  3 files changed, 124 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/serial/serial_clps711x.c
> 
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index 7eb96ed..02bc8bf 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -43,6 +43,11 @@ config DRIVER_SERIAL_BLACKFIN
>  	default y
>  	bool "Blackfin serial driver"
>  
> +config DRIVER_SERIAL_CLPS711X
> +	depends on ARCH_CLPS711X
> +	default y
> +	bool "CLPS711X serial driver"
> +
>  config DRIVER_SERIAL_ALTERA
>  	depends on NIOS2
>  	default y
> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
> index e2d56b9..e6f1e22 100644
> --- a/drivers/serial/Makefile
> +++ b/drivers/serial/Makefile
> @@ -13,6 +13,7 @@ obj-$(CONFIG_DRIVER_SERIAL_NETX)		+= serial_netx.o
>  obj-$(CONFIG_DRIVER_SERIAL_LINUX_CONSOLE)	+= linux_console.o
>  obj-$(CONFIG_DRIVER_SERIAL_MPC5XXX)		+= serial_mpc5xxx.o
>  obj-$(CONFIG_DRIVER_SERIAL_BLACKFIN)		+= serial_blackfin.o
> +obj-$(CONFIG_DRIVER_SERIAL_CLPS711X)		+= serial_clps711x.o
>  obj-$(CONFIG_DRIVER_SERIAL_NS16550)		+= serial_ns16550.o
>  obj-$(CONFIG_DRIVER_SERIAL_PL010)		+= serial_pl010.o
>  obj-$(CONFIG_DRIVER_SERIAL_S3C)			+= serial_s3c.o
> diff --git a/drivers/serial/serial_clps711x.c b/drivers/serial/serial_clps711x.c
> new file mode 100644
> index 0000000..462ba9f
> --- /dev/null
> +++ b/drivers/serial/serial_clps711x.c
> @@ -0,0 +1,118 @@
> +/*
> + * Simple CLPS711X serial driver
> + *
> + * (C) Copyright 2012 Alexander Shiyan <shc_work@mail.ru>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +#include <io.h>
> +#include <linux/clk.h>
> +
> +#include <mach/clps711x.h>
> +
> +#define UBRLCR(x)	(UBRLCR1 + (x) * 0x1000)
> +#define SYSCON(x)	(SYSCON1 + (x) * 0x1000)
> +#define SYSFLG(x)	(SYSFLG1 + (x) * 0x1000)
> +#define UARTDR(x)	(UARTDR1 + (x) * 0x1000)
provide this via resoure

here 4 resources
> +
> +static int clps711x_setbaudrate(struct console_device *cdev, int baudrate)
> +{
> +	int divisor;
> +	u32 tmp;
> +
> +	divisor = (clk_get_rate(cdev->dev->priv) / 16) / baudrate;
> +
> +	tmp = readl(UBRLCR(cdev->dev->id)) & ~UBRLCR_BAUD_MASK;
> +	tmp |= divisor - 1;
> +	writel(tmp, UBRLCR(cdev->dev->id));
> +
> +	return 0;
> +}
> +
> +static void clps711x_init_port(struct console_device *cdev)
> +{
> +	u32 tmp;
> +
> +	/* Disable the UART */
> +	writel(readl(SYSCON(cdev->dev->id)) & ~SYSCON_UARTEN,
> +	       SYSCON(cdev->dev->id));
> +
> +	/* Setup Line Control Register */
> +	tmp = readl(UBRLCR(cdev->dev->id)) & UBRLCR_BAUD_MASK;
> +	tmp |= UBRLCR_FIFOEN | UBRLCR_WRDLEN8; /* FIFO on, 8N1 mode */
> +	writel(tmp, UBRLCR(cdev->dev->id));
> +
> +	/* Set default baudrate on initialization */
> +	clps711x_setbaudrate(cdev, CONFIG_BAUDRATE);
> +
> +	/* Enable the UART */
> +	writel(readl(SYSCON(cdev->dev->id)) | SYSCON_UARTEN,
> +	       SYSCON(cdev->dev->id));
> +}
> +
> +static void clps711x_putc(struct console_device *cdev, char c)
> +{
> +	/* Wait until there is space in the FIFO */
> +	while (readl(SYSFLG(cdev->dev->id)) & SYSFLG_UTXFF) {
> +	}
drop the {}
> +
> +	/* Send the character */
> +	writew(c, UARTDR(cdev->dev->id));
> +}
> +
> +static int clps711x_getc(struct console_device *cdev)
> +{
> +	u16 data;
> +
> +	/* Wait until there is data in the FIFO */
> +	while (readl(SYSFLG(cdev->dev->id)) & SYSFLG_URXFE) {
> +	}
> +
> +	data = readw(UARTDR(cdev->dev->id));
> +
> +	/* Check for an error flag */
> +	if (data & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR))
> +		return -1;
> +
> +	return (int)data;
> +}
> +
> +static int clps711x_tstc(struct console_device *cdev)
> +{
> +	return !(readl(SYSFLG(cdev->dev->id)) & SYSFLG_URXFE);
factorise those pull status as

status int xxx(data, mask) {}

Best Regards,
J.

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^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH v2 3/3] ARM: clps711x: Add generic board support (CLEP7212)
  2012-10-15 16:26 ` [PATCH v2 3/3] ARM: clps711x: Add generic board support (CLEP7212) Alexander Shiyan
@ 2012-10-15 18:03   ` Jean-Christophe PLAGNIOL-VILLARD
  2012-10-15 19:05     ` Alexander Shiyan
  0 siblings, 1 reply; 16+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-10-15 18:03 UTC (permalink / raw)
  To: Alexander Shiyan; +Cc: barebox

On 20:26 Mon 15 Oct     , Alexander Shiyan wrote:
> This patch adds generic board support (CLEP7212, Linux ARM ID=91)
> for CLPS711X-target.
> 
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> ---
>  arch/arm/Makefile                               |    1 +
>  arch/arm/boards/clep7212/Makefile               |    1 +
>  arch/arm/boards/clep7212/clep7212.c             |   64 +++++++++++++++++++++++
>  arch/arm/boards/clep7212/config.h               |    4 ++
>  arch/arm/boards/clep7212/env/bin/mtdparts-add   |   21 +++++++
>  arch/arm/boards/clep7212/env/boot/nor           |    9 +++
>  arch/arm/boards/clep7212/env/init/automount     |   12 ++++
>  arch/arm/boards/clep7212/env/init/bootargs-base |    8 +++
>  arch/arm/boards/clep7212/env/init/general       |   12 ++++
>  arch/arm/boards/clep7212/env/init/hostname      |    8 +++
>  arch/arm/boards/clep7212/lowlevel.c             |   56 ++++++++++++++++++++
>  arch/arm/configs/clps711x_defconfig             |   42 +++++++++++++++
>  arch/arm/mach-clps711x/Kconfig                  |    9 +++
>  13 files changed, 247 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/boards/clep7212/Makefile
>  create mode 100644 arch/arm/boards/clep7212/clep7212.c
>  create mode 100644 arch/arm/boards/clep7212/config.h
>  create mode 100644 arch/arm/boards/clep7212/env/bin/mtdparts-add
>  create mode 100644 arch/arm/boards/clep7212/env/boot/nor
>  create mode 100644 arch/arm/boards/clep7212/env/init/automount
>  create mode 100644 arch/arm/boards/clep7212/env/init/bootargs-base
>  create mode 100644 arch/arm/boards/clep7212/env/init/general
>  create mode 100644 arch/arm/boards/clep7212/env/init/hostname
>  create mode 100644 arch/arm/boards/clep7212/lowlevel.c
>  create mode 100644 arch/arm/configs/clps711x_defconfig
> 
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index da80e00..05f9943 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -76,6 +76,7 @@ board-$(CONFIG_MACH_AT91SAM9G10EK)		:= at91sam9261ek
>  board-$(CONFIG_MACH_AT91SAM9G20EK)		:= at91sam9260ek
>  board-$(CONFIG_MACH_AT91SAM9X5EK)		:= at91sam9x5ek
>  board-$(CONFIG_MACH_AT91SAM9M10G45EK)		:= at91sam9m10g45ek
> +board-$(CONFIG_MACH_CLEP7212)			:= clep7212
>  board-$(CONFIG_MACH_DSS11)			:= dss11
>  board-$(CONFIG_MACH_EDB9301)			:= edb93xx
>  board-$(CONFIG_MACH_EDB9302)			:= edb93xx
> diff --git a/arch/arm/boards/clep7212/Makefile b/arch/arm/boards/clep7212/Makefile
> new file mode 100644
> index 0000000..7e58f10
> --- /dev/null
> +++ b/arch/arm/boards/clep7212/Makefile
> @@ -0,0 +1 @@
> +obj-y += clep7212.o lowlevel.o
> diff --git a/arch/arm/boards/clep7212/clep7212.c b/arch/arm/boards/clep7212/clep7212.c
> new file mode 100644
> index 0000000..1d5828d
> --- /dev/null
> +++ b/arch/arm/boards/clep7212/clep7212.c
> @@ -0,0 +1,64 @@
> +/*
> + * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include <common.h>
> +#include <driver.h>
> +#include <init.h>
> +#include <partition.h>
> +#include <io.h>
> +#include <sizes.h>
> +#include <asm/armlinux.h>
> +#include <generated/mach-types.h>
> +
> +#include <mach/clps711x.h>
> +#include <mach/devices.h>
> +
> +static int clps711x_mem_init(void)
> +{
> +	ulong memsize = get_ram_size((ulong *)SDRAM_BASE, SZ_32M);
> +
> +	arm_add_mem_device("ram0", SDRAM_BASE, memsize);
create a generic fuction as soc level
clps711x_add_mem(x);
> +
> +	return 0;
> +}
> +mem_initcall(clps711x_mem_init);
> +
> +static int clps711x_devices_init(void)
> +{
> +	u32 serial_h = 0, serial_l = readl(UNIQID);
> +
> +	/* Setup Chipselects */
> +	clps711x_setup_memcfg(0, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_16);
> +	clps711x_setup_memcfg(1, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_8);
> +	clps711x_setup_memcfg(2, MEMCFG_WAITSTATE_8_3 | MEMCFG_BUS_WIDTH_16 |
> +			      MEMCFG_CLKENB);
> +	clps711x_setup_memcfg(3, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_32);
> +
> +	add_cfi_flash_device(0, CS0_BASE, SZ_32M, 0);
> +
> +	devfs_add_partition("nor0", 0x00000, SZ_256K, DEVFS_PARTITION_FIXED,
> +			    "self0");
> +	devfs_add_partition("nor0", SZ_256K, SZ_256K, DEVFS_PARTITION_FIXED,
> +			    "env0");
> +
> +	armlinux_set_bootparams((void *)SDRAM_BASE + 0x100);
> +	armlinux_set_architecture(MACH_TYPE_CLEP7212);
> +	armlinux_set_serial(((u64)serial_h << 32) | serial_l);
> +
> +	return 0;
> +}
> +device_initcall(clps711x_devices_init);
> +
> +static int clps711x_console_init(void)
> +{
> +	clps711x_add_uart(0);
> +
> +	return 0;
> +}
> +console_initcall(clps711x_console_init);
> diff --git a/arch/arm/boards/clep7212/config.h b/arch/arm/boards/clep7212/config.h
> new file mode 100644
> index 0000000..6ae9a40
> --- /dev/null
> +++ b/arch/arm/boards/clep7212/config.h
> @@ -0,0 +1,4 @@
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#endif  /* __CONFIG_H */
> diff --git a/arch/arm/boards/clep7212/env/bin/mtdparts-add b/arch/arm/boards/clep7212/env/bin/mtdparts-add
> new file mode 100644
> index 0000000..ef1bc02
> --- /dev/null
> +++ b/arch/arm/boards/clep7212/env/bin/mtdparts-add
> @@ -0,0 +1,21 @@
> +#!/bin/sh
> +
> +if [ "$1" = menu ]; then
> +	init-menu-add-entry "$0" "Partitions"
> +	exit
> +fi
> +
> +norparts="256k(barebox),256k(bareboxenv),3584k(kernel),-(root)"
> +ramparts="-(ramdisk)"
> +
> +if [ -e /dev/nor0 ]; then
> +	addpart -n /dev/nor0 "${norparts}"
> +
> +	global linux.mtdparts.nor
> +	global.linux.mtdparts.nor="physmap-flash.0:${norparts}"
> +else
> +	echo "NOR Flash not found."
> +fi
> +
> +global linux.mtdparts.ram
> +global.linux.mtdparts.ram="mtd-ram.0:${ramparts}"
> diff --git a/arch/arm/boards/clep7212/env/boot/nor b/arch/arm/boards/clep7212/env/boot/nor
> new file mode 100644
> index 0000000..5cf1e15
> --- /dev/null
> +++ b/arch/arm/boards/clep7212/env/boot/nor
> @@ -0,0 +1,9 @@
> +#!/bin/sh
> +
> +if [ "$1" = menu ]; then
> +	boot-menu-add-entry "$0" "NOR Flash"
> +	exit
> +fi
> +
> +global.bootm.image="/dev/kernel"
> +global.linux.bootargs.dyn.root="root=/dev/mtdblock4 ro"
> diff --git a/arch/arm/boards/clep7212/env/init/automount b/arch/arm/boards/clep7212/env/init/automount
> new file mode 100644
> index 0000000..2ceefc3
> --- /dev/null
> +++ b/arch/arm/boards/clep7212/env/init/automount
> @@ -0,0 +1,12 @@
> +#!/bin/sh
> +
> +if [ "$1" = menu ]; then
> +	init-menu-add-entry "$0" "Automountpoints"
> +	exit
> +fi
> +
> +mkdir -p /mnt/disk0
> +automount -d /mnt/disk0 '[ -e /dev/disk0.0 ] && mount /dev/disk0.0 /mnt/disk0'
> +
> +mkdir -p /mnt/disk1
I do not see any block driver
> +automount -d /mnt/disk1 '[ -e /dev/disk1.0 ] && mount /dev/disk1.0 /mnt/disk1'
> diff --git a/arch/arm/boards/clep7212/env/init/bootargs-base b/arch/arm/boards/clep7212/env/init/bootargs-base
> new file mode 100644
> index 0000000..ec08e39
> --- /dev/null
> +++ b/arch/arm/boards/clep7212/env/init/bootargs-base
> @@ -0,0 +1,8 @@
> +#!/bin/sh
> +
> +if [ "$1" = menu ]; then
> +	init-menu-add-entry "$0" "Base bootargs"
> +	exit
> +fi
> +
> +global.linux.bootargs.base="earlyprintk console=ttyCL0,57600n8"
> diff --git a/arch/arm/boards/clep7212/env/init/general b/arch/arm/boards/clep7212/env/init/general
> new file mode 100644
> index 0000000..77e6a59
> --- /dev/null
> +++ b/arch/arm/boards/clep7212/env/init/general
> @@ -0,0 +1,12 @@
> +#!/bin/sh
> +
> +if [ "$1" = menu ]; then
> +	init-menu-add-entry "$0" "general config settings"
> +	exit
> +fi
> +
> +global.user=barebox
> +global.autoboot_timeout=2
> +global.boot.default=nor
> +
> +/env/bin/mtdparts-add
> diff --git a/arch/arm/boards/clep7212/env/init/hostname b/arch/arm/boards/clep7212/env/init/hostname
> new file mode 100644
> index 0000000..684ee63
> --- /dev/null
> +++ b/arch/arm/boards/clep7212/env/init/hostname
> @@ -0,0 +1,8 @@
> +#!/bin/sh
> +
> +if [ "$1" = menu ]; then
> +	init-menu-add-entry "$0" "hostname"
> +	exit
> +fi
> +
> +global.hostname=clep7212
> diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c
> new file mode 100644
> index 0000000..9b7e241
> --- /dev/null
> +++ b/arch/arm/boards/clep7212/lowlevel.c
> @@ -0,0 +1,56 @@
> +/*
> + * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +
> +#include <asm/io.h>
> +#include <asm/barebox-arm.h>
> +#include <asm/barebox-arm-head.h>
> +
> +#include <mach/clps711x.h>
> +
> +#define MAIN_CLOCK		3686400
> +#define CPU_SPEED		92160000
> +#define BUS_SPEED		(CPU_SPEED / 2)
> +
> +#define PLL_VALUE		(((CPU_SPEED * 2) / MAIN_CLOCK) << 24)
> +#define SDRAM_REFRESH_RATE	(64 * (BUS_SPEED / (8192 * 1000)))
> +
> +void __naked __bare_init reset(void)
> +{
> +	u32 tmp;
> +
> +	common_reset();
> +
> +	/* Setup base clock */
> +	writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3);
> +	asm("nop");
> +
> +	/* Setup PLL */
> +	writel(PLL_VALUE, PLLW);
> +	asm("nop");
> +
> +	/* CLKEN select, SDRAM width=32 */
> +	writel(SYSCON2_CLKENSL, SYSCON2);
> +
> +	/* Enable SDQM pins */
> +	tmp = readl(SYSCON3);
> +	tmp &= ~SYSCON3_ENPD67;
> +	writel(tmp, SYSCON3);
> +
> +	/* Setup Refresh Rate (64ms 8K Blocks) */
> +	writel(SDRAM_REFRESH_RATE, SDRFPR);
> +
> +	/* Setup SDRAM (32MB, 16Bit*2, CAS=3) */
> +	writel(SDCONF_CASLAT_3 | SDCONF_SIZE_256 | SDCONF_WIDTH_16 |
> +	       SDCONF_CLKCTL | SDCONF_ACTIVE, SDCONF);
> +
> +	board_init_lowlevel_return();
> +}
> diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
> new file mode 100644
> index 0000000..cf2b3b6
> --- /dev/null
> +++ b/arch/arm/configs/clps711x_defconfig
> @@ -0,0 +1,42 @@
> +CONFIG_ARCH_CLPS711X=y
> +CONFIG_AEABI=y
> +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
> +# CONFIG_MEMINFO is not set
> +CONFIG_TEXT_BASE=0xc0780000
> +CONFIG_EXPERIMENTAL=y
> +CONFIG_BAUDRATE=57600
> +CONFIG_CMDLINE_EDITING=y
> +CONFIG_AUTO_COMPLETE=y
> +CONFIG_DEFAULT_ENVIRONMENT_COMPRESSED_LZO=y
> +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
> +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/clep7212/env"
> +CONFIG_CMD_EDIT=y
> +CONFIG_CMD_SAVEENV=y
> +CONFIG_CMD_EXPORT=y
> +CONFIG_CMD_PRINTENV=y
> +CONFIG_CMD_ECHO_E=y
> +CONFIG_CMD_IOMEM=y
> +CONFIG_CMD_CRC=y
> +CONFIG_CMD_CRC_CMP=y
> +CONFIG_CMD_FLASH=y
> +CONFIG_CMD_BOOTM_SHOW_TYPE=y
> +CONFIG_CMD_BOOTM_INITRD=y
> +CONFIG_CMD_BOOTZ=y
> +# CONFIG_CMD_BOOTU is not set
> +CONFIG_CMD_RESET=y
> +CONFIG_CMD_TIMEOUT=y
> +CONFIG_CMD_PARTITION=y
> +CONFIG_CMD_MAGICVAR=y
> +CONFIG_CMD_MAGICVAR_HELP=y
> +# CONFIG_SPI is not set
> +CONFIG_DRIVER_CFI=y
> +# CONFIG_DRIVER_CFI_BANK_WIDTH_1 is not set
> +# CONFIG_DRIVER_CFI_BANK_WIDTH_4 is not set
> +CONFIG_MTD=y
> +CONFIG_DISK=y
> +CONFIG_DISK_WRITE=y
> +CONFIG_DISK_INTF_PLATFORM_IDE=y
> +CONFIG_FS_CRAMFS=y
> +CONFIG_FS_FAT=y
> +CONFIG_FS_FAT_LFN=y
no DO_LOWLEVEL_INIT
> +CONFIG_LZO_DECOMPRESS=y
> diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
> index c5e97ed..f531587 100644
> --- a/arch/arm/mach-clps711x/Kconfig
> +++ b/arch/arm/mach-clps711x/Kconfig
> @@ -3,8 +3,17 @@ if ARCH_CLPS711X
>  choice
>  	prompt "Cirrus Logic EP711x/EP721x/EP731x Board Type"
>  
> +config MACH_CLEP7212
> +	bool "Cirrus Logic CLEP7212"
> +	select MACH_HAS_LOWLEVEL_INIT
> +	help
> +	  Boards based on the Cirrus Logic 7212/7312 CPU
> +
>  endchoice
>  
> +config BOARDINFO
> +	default "Cirrus Logic CLEP7212"
if MACH...
> +
>  config ARCH_TEXT_BASE
>  	hex
>  	default 0xc0780000
> -- 
> 1.7.8.6
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox

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^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH v2 1/3] ARM: Add CLPS711X architecture
  2012-10-15 17:54 ` [PATCH v2 1/3] ARM: Add CLPS711X architecture Jean-Christophe PLAGNIOL-VILLARD
@ 2012-10-15 18:56   ` Alexander Shiyan
  2012-10-16  8:09     ` Jean-Christophe PLAGNIOL-VILLARD
  0 siblings, 1 reply; 16+ messages in thread
From: Alexander Shiyan @ 2012-10-15 18:56 UTC (permalink / raw)
  To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox

On Mon, 15 Oct 2012 19:54:14 +0200
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> wrote:

> On 20:26 Mon 15 Oct     , Alexander Shiyan wrote:
> > This patch adds new architecture (CLPS711X) into barebox.
> > The core-logic functionality of the device is built around an ARM720T
> > processor running at clock speeds up to 90 MHz.
> > 
> > Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
...
> > +#include <linux/clkdev.h>
> split the code in 2
>  - clock
>  - clocksource in drivers/clocksource
>  and cs as a driver
drivers/clocksource is missing in master repository and as far I know we are
made patches for "master" but not for "next".

...
> > +	osc = 3686400;
> > +	ext = 13000000;
> creaet a clock for this
This is constant frequencies and it is used only here. Is this really need?

...
> > +void clps711x_add_uart(unsigned int id)
> > +{
> > +	add_generic_device_res("clps711x_serial", id, NULL, 0, NULL);
> where is the base address address?
Base address is not needed because it is impossible to request resource for
registers for this CPU. Registers is shared for all devices.

> where is the check on the id?
Simple check is provided in serial driver by definition, for example:
SYSFLG(x) ? SYSFLG2 : SYSFLG1, where x is "id".
But, you are right, I will made one more check for id in "probe".

-- 
Alexander Shiyan <shc_work@mail.ru>

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^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/3] ARM: clps711x: Add serial driver
  2012-10-15 17:58   ` Jean-Christophe PLAGNIOL-VILLARD
@ 2012-10-15 19:00     ` Alexander Shiyan
  2012-10-15 21:58     ` Sascha Hauer
  1 sibling, 0 replies; 16+ messages in thread
From: Alexander Shiyan @ 2012-10-15 19:00 UTC (permalink / raw)
  To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox

On Mon, 15 Oct 2012 19:58:52 +0200
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> wrote:

> > +static int clps711x_tstc(struct console_device *cdev)
> > +{
> > +	return !(readl(SYSFLG(cdev->dev->id)) & SYSFLG_URXFE);
> factorise those pull status as
> 
> status int xxx(data, mask) {}
Not clean understand this comment. You mean about one more define
for check status?

-- 
Alexander Shiyan <shc_work@mail.ru>

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^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH v2 3/3] ARM: clps711x: Add generic board support (CLEP7212)
  2012-10-15 18:03   ` Jean-Christophe PLAGNIOL-VILLARD
@ 2012-10-15 19:05     ` Alexander Shiyan
  0 siblings, 0 replies; 16+ messages in thread
From: Alexander Shiyan @ 2012-10-15 19:05 UTC (permalink / raw)
  To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox

On Mon, 15 Oct 2012 20:03:59 +0200
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> wrote:

...
> > +mkdir -p /mnt/disk0
> > +automount -d /mnt/disk0 '[ -e /dev/disk0.0 ] && mount /dev/disk0.0 /mnt/disk0'
> > +
> > +mkdir -p /mnt/disk1
> I do not see any block driver
Sorry, this is my upstream :)

-- 
Alexander Shiyan <shc_work@mail.ru>

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^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/3] ARM: clps711x: Add serial driver
  2012-10-15 17:58   ` Jean-Christophe PLAGNIOL-VILLARD
  2012-10-15 19:00     ` Alexander Shiyan
@ 2012-10-15 21:58     ` Sascha Hauer
  2012-10-16  8:08       ` Jean-Christophe PLAGNIOL-VILLARD
  1 sibling, 1 reply; 16+ messages in thread
From: Sascha Hauer @ 2012-10-15 21:58 UTC (permalink / raw)
  To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox

On Mon, Oct 15, 2012 at 07:58:52PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 20:26 Mon 15 Oct     , Alexander Shiyan wrote:
> > 
> > +
> > +#define UBRLCR(x)	(UBRLCR1 + (x) * 0x1000)
> > +#define SYSCON(x)	(SYSCON1 + (x) * 0x1000)
> > +#define SYSFLG(x)	(SYSFLG1 + (x) * 0x1000)
> > +#define UARTDR(x)	(UARTDR1 + (x) * 0x1000)
> provide this via resoure
> 
> here 4 resources

We already had this. This SoC has a very strange register layout. The
registers for the UARTs are spread around the SoC and the registers
are not even exclusively used for the UARTs. They have bits which are
also used for the timer and other stuff.

> > +static int clps711x_tstc(struct console_device *cdev)
> > +{
> > +	return !(readl(SYSFLG(cdev->dev->id)) & SYSFLG_URXFE);
> factorise those pull status as
> 
> status int xxx(data, mask) {}

I don'r understand this. This is a single register read, there's not
much to factorize and the code is easy to read.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/3] ARM: clps711x: Add serial driver
  2012-10-15 21:58     ` Sascha Hauer
@ 2012-10-16  8:08       ` Jean-Christophe PLAGNIOL-VILLARD
  2012-10-16 21:39         ` Sascha Hauer
  0 siblings, 1 reply; 16+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-10-16  8:08 UTC (permalink / raw)
  To: Sascha Hauer; +Cc: barebox

On 23:58 Mon 15 Oct     , Sascha Hauer wrote:
> On Mon, Oct 15, 2012 at 07:58:52PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 20:26 Mon 15 Oct     , Alexander Shiyan wrote:
> > > 
> > > +
> > > +#define UBRLCR(x)	(UBRLCR1 + (x) * 0x1000)
> > > +#define SYSCON(x)	(SYSCON1 + (x) * 0x1000)
> > > +#define SYSFLG(x)	(SYSFLG1 + (x) * 0x1000)
> > > +#define UARTDR(x)	(UARTDR1 + (x) * 0x1000)
> > provide this via resoure
> > 
> > here 4 resources
> 
> We already had this. This SoC has a very strange register layout. The
> registers for the UARTs are spread around the SoC and the registers
> are not even exclusively used for the UARTs. They have bits which are
> also used for the timer and other stuff.
use the device id to select the register is wrong

we need to pass the register via resource (without request) or platform data
> 
> > > +static int clps711x_tstc(struct console_device *cdev)
> > > +{
> > > +	return !(readl(SYSFLG(cdev->dev->id)) & SYSFLG_URXFE);
> > factorise those pull status as
> > 
> > status int xxx(data, mask) {}
> 
> I don'r understand this. This is a single register read, there's not
> much to factorize and the code is easy to read.
he use the code at a least 2 place

Best Regards,
J.

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^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH v2 1/3] ARM: Add CLPS711X architecture
  2012-10-15 18:56   ` Alexander Shiyan
@ 2012-10-16  8:09     ` Jean-Christophe PLAGNIOL-VILLARD
  2012-10-16 21:42       ` Sascha Hauer
  0 siblings, 1 reply; 16+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-10-16  8:09 UTC (permalink / raw)
  To: Alexander Shiyan; +Cc: barebox

On 22:56 Mon 15 Oct     , Alexander Shiyan wrote:
> On Mon, 15 Oct 2012 19:54:14 +0200
> Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> wrote:
> 
> > On 20:26 Mon 15 Oct     , Alexander Shiyan wrote:
> > > This patch adds new architecture (CLPS711X) into barebox.
> > > The core-logic functionality of the device is built around an ARM720T
> > > processor running at clock speeds up to 90 MHz.
> > > 
> > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> ...
> > > +#include <linux/clkdev.h>
> > split the code in 2
> >  - clock
> >  - clocksource in drivers/clocksource
> >  and cs as a driver
> drivers/clocksource is missing in master repository and as far I know we are
> made patches for "master" but not for "next".
so base your code on next
> 
> ...
> > > +	osc = 3686400;
> > > +	ext = 13000000;
> > creaet a clock for this
> This is constant frequencies and it is used only here. Is this really need?
but it's still a clock if the driver need clock info fixed or not he request a
clock as the value can change across soc
> 
> ...
> > > +void clps711x_add_uart(unsigned int id)
> > > +{
> > > +	add_generic_device_res("clps711x_serial", id, NULL, 0, NULL);
> > where is the base address address?
> Base address is not needed because it is impossible to request resource for
> registers for this CPU. Registers is shared for all devices.
> 
> > where is the check on the id?
> Simple check is provided in serial driver by definition, for example:
> SYSFLG(x) ? SYSFLG2 : SYSFLG1, where x is "id".
> But, you are right, I will made one more check for id in "probe".
> 
> -- 
> Alexander Shiyan <shc_work@mail.ru>

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^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/3] ARM: clps711x: Add serial driver
  2012-10-16  8:08       ` Jean-Christophe PLAGNIOL-VILLARD
@ 2012-10-16 21:39         ` Sascha Hauer
  2012-10-20 13:50           ` Alexander Shiyan
  0 siblings, 1 reply; 16+ messages in thread
From: Sascha Hauer @ 2012-10-16 21:39 UTC (permalink / raw)
  To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox

On Tue, Oct 16, 2012 at 10:08:01AM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > 
> > > here 4 resources
> > 
> > We already had this. This SoC has a very strange register layout. The
> > registers for the UARTs are spread around the SoC and the registers
> > are not even exclusively used for the UARTs. They have bits which are
> > also used for the timer and other stuff.
> use the device id to select the register is wrong
> 
> we need to pass the register via resource (without request) or platform data
> > 
> > > > +static int clps711x_tstc(struct console_device *cdev)
> > > > +{
> > > > +	return !(readl(SYSFLG(cdev->dev->id)) & SYSFLG_URXFE);
> > > factorise those pull status as
> > > 
> > > status int xxx(data, mask) {}
> > 
> > I don'r understand this. This is a single register read, there's not
> > much to factorize and the code is easy to read.
> he use the code at a least 2 place

Testing for a bit like above is done a thousand times all around the
kernel and barebox. There is nothing to factorize. The way Alexander did
it is perfectly fine.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH v2 1/3] ARM: Add CLPS711X architecture
  2012-10-16  8:09     ` Jean-Christophe PLAGNIOL-VILLARD
@ 2012-10-16 21:42       ` Sascha Hauer
  0 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2012-10-16 21:42 UTC (permalink / raw)
  To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox

On Tue, Oct 16, 2012 at 10:09:47AM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 22:56 Mon 15 Oct     , Alexander Shiyan wrote:
> > On Mon, 15 Oct 2012 19:54:14 +0200
> > Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> wrote:
> > 
> > > On 20:26 Mon 15 Oct     , Alexander Shiyan wrote:
> > > > This patch adds new architecture (CLPS711X) into barebox.
> > > > The core-logic functionality of the device is built around an ARM720T
> > > > processor running at clock speeds up to 90 MHz.
> > > > 
> > > > Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> > ...
> > > > +#include <linux/clkdev.h>
> > > split the code in 2
> > >  - clock
> > >  - clocksource in drivers/clocksource
> > >  and cs as a driver
> > drivers/clocksource is missing in master repository and as far I know we are
> > made patches for "master" but not for "next".
> so base your code on next

Generally basing code on next causes maintenance burden. I really prefer
patches on master. In this case it means that the location for the
clocksource driver is fine. What we can look at is that this files
really only contains the clocksource so that it can simply be moved
later.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/3] ARM: clps711x: Add serial driver
  2012-10-16 21:39         ` Sascha Hauer
@ 2012-10-20 13:50           ` Alexander Shiyan
  2012-10-23  6:38             ` Sascha Hauer
  0 siblings, 1 reply; 16+ messages in thread
From: Alexander Shiyan @ 2012-10-20 13:50 UTC (permalink / raw)
  To: Sascha Hauer; +Cc: barebox

On Tue, 16 Oct 2012 23:39:56 +0200
Sascha Hauer <s.hauer@pengutronix.de> wrote:

...
> > > We already had this. This SoC has a very strange register layout. The
> > > registers for the UARTs are spread around the SoC and the registers
> > > are not even exclusively used for the UARTs. They have bits which are
> > > also used for the timer and other stuff.
> > use the device id to select the register is wrong
> > 
> > we need to pass the register via resource (without request) or platform data
> > > 
> > > > > +static int clps711x_tstc(struct console_device *cdev)
> > > > > +{
> > > > > +	return !(readl(SYSFLG(cdev->dev->id)) & SYSFLG_URXFE);
> > > > factorise those pull status as
> > > > 
> > > > status int xxx(data, mask) {}
> > > 
> > > I don'r understand this. This is a single register read, there's not
> > > much to factorize and the code is easy to read.
> > he use the code at a least 2 place
> 
> Testing for a bit like above is done a thousand times all around the
> kernel and barebox. There is nothing to factorize. The way Alexander did
> it is perfectly fine.
Please look on new version below. If it looks OK, I will make complete v2 patch.
Thanks!

/*
 * Simple CLPS711X serial driver
 *
 * (C) Copyright 2012 Alexander Shiyan <shc_work@mail.ru>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

#include <common.h>
#include <malloc.h>
#include <init.h>
#include <io.h>
#include <linux/clk.h>

#include <mach/clps711x.h>

struct clps711x_uart {
	void __iomem		*UBRLCR;
	void __iomem		*SYSCON;
	void __iomem		*SYSFLG;
	void __iomem		*UARTDR;
	struct clk		*uart_clk;
	struct console_device	cdev;
};

static int clps711x_setbaudrate(struct console_device *cdev, int baudrate)
{
	struct clps711x_uart *s = cdev->dev->priv;
	int divisor;
	u32 tmp;

	divisor = (clk_get_rate(s->uart_clk) / 16) / baudrate;

	tmp = readl(s->UBRLCR) & ~UBRLCR_BAUD_MASK;
	tmp |= divisor - 1;
	writel(tmp, s->UBRLCR);

	return 0;
}

static void clps711x_init_port(struct console_device *cdev)
{
	struct clps711x_uart *s = cdev->dev->priv;
	u32 tmp;

	/* Disable the UART */
	writel(readl(s->SYSCON) & ~SYSCON_UARTEN, s->SYSCON);

	/* Setup Line Control Register */
	tmp = readl(s->UBRLCR) & UBRLCR_BAUD_MASK;
	tmp |= UBRLCR_FIFOEN | UBRLCR_WRDLEN8; /* FIFO on, 8N1 mode */
	writel(tmp, s->UBRLCR);

	/* Set default baudrate on initialization */
	clps711x_setbaudrate(cdev, CONFIG_BAUDRATE);

	/* Enable the UART */
	writel(readl(s->SYSCON) | SYSCON_UARTEN, s->SYSCON);
}

static void clps711x_putc(struct console_device *cdev, char c)
{
	struct clps711x_uart *s = cdev->dev->priv;

	/* Wait until there is space in the FIFO */
	while (readl(s->SYSFLG) & SYSFLG_UTXFF)
		barrier();

	/* Send the character */
	writew(c, s->UARTDR);
}

static int clps711x_getc(struct console_device *cdev)
{
	struct clps711x_uart *s = cdev->dev->priv;
	u16 data;

	/* Wait until there is data in the FIFO */
	while (readl(s->SYSFLG) & SYSFLG_URXFE)
		barrier();

	data = readw(s->UARTDR);

	/* Check for an error flag */
	if (data & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR))
		return -1;

	return (int)data;
}

static int clps711x_tstc(struct console_device *cdev)
{
	struct clps711x_uart *s = cdev->dev->priv;

	return !(readl(s->SYSFLG) & SYSFLG_URXFE);
}

static void clps711x_flush(struct console_device *cdev)
{
	struct clps711x_uart *s = cdev->dev->priv;

	while (readl(s->SYSFLG) & SYSFLG_UBUSY)
		barrier();
}

static int clps711x_probe(struct device_d *dev)
{
	struct clps711x_uart *s;

	BUG_ON(dev->num_resources != 4);

	s = xzalloc(sizeof(struct clps711x_uart));
	s->uart_clk = clk_get(dev, NULL);
	BUG_ON(!s->uart_clk);

	s->UBRLCR = dev_get_mem_region(dev, 0);
	s->SYSCON = dev_get_mem_region(dev, 1);
	s->SYSFLG = dev_get_mem_region(dev, 2);
	s->UARTDR = dev_get_mem_region(dev, 3);

	dev->priv	= s;
	s->cdev.dev	= dev;
	s->cdev.f_caps	= CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
	s->cdev.tstc	= clps711x_tstc;
	s->cdev.putc	= clps711x_putc;
	s->cdev.getc	= clps711x_getc;
	s->cdev.flush	= clps711x_flush;
	s->cdev.setbrg	= clps711x_setbaudrate;
	clps711x_init_port(&s->cdev);

	return console_register(&s->cdev);
}

static void clps711x_remove(struct device_d *dev)
{
	struct clps711x_uart *s = dev->priv;

	clps711x_flush(&s->cdev);
	console_unregister(&s->cdev);
	free(s);
}

static struct driver_d clps711x_driver = {
	.name	= "clps711x_serial",
	.probe	= clps711x_probe,
	.remove	= clps711x_remove,
};

static int clps711x_init(void)
{
	return platform_driver_register(&clps711x_driver);
}
console_initcall(clps711x_init);

-- 
Alexander Shiyan <shc_work@mail.ru>

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^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/3] ARM: clps711x: Add serial driver
  2012-10-20 13:50           ` Alexander Shiyan
@ 2012-10-23  6:38             ` Sascha Hauer
  0 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2012-10-23  6:38 UTC (permalink / raw)
  To: Alexander Shiyan; +Cc: barebox

On Sat, Oct 20, 2012 at 05:50:58PM +0400, Alexander Shiyan wrote:
> On Tue, 16 Oct 2012 23:39:56 +0200
> Sascha Hauer <s.hauer@pengutronix.de> wrote:
> 
> ...
> > > > We already had this. This SoC has a very strange register layout. The
> > > > registers for the UARTs are spread around the SoC and the registers
> > > > are not even exclusively used for the UARTs. They have bits which are
> > > > also used for the timer and other stuff.
> > > use the device id to select the register is wrong
> > > 
> > > we need to pass the register via resource (without request) or platform data
> > > > 
> > > > > > +static int clps711x_tstc(struct console_device *cdev)
> > > > > > +{
> > > > > > +	return !(readl(SYSFLG(cdev->dev->id)) & SYSFLG_URXFE);
> > > > > factorise those pull status as
> > > > > 
> > > > > status int xxx(data, mask) {}
> > > > 
> > > > I don'r understand this. This is a single register read, there's not
> > > > much to factorize and the code is easy to read.
> > > he use the code at a least 2 place
> > 
> > Testing for a bit like above is done a thousand times all around the
> > kernel and barebox. There is nothing to factorize. The way Alexander did
> > it is perfectly fine.
> Please look on new version below. If it looks OK, I will make complete v2 patch.
> Thanks!
> 
> /*
>  * Simple CLPS711X serial driver
>  *
>  * (C) Copyright 2012 Alexander Shiyan <shc_work@mail.ru>
>  *
>  * This program is free software; you can redistribute it and/or
>  * modify it under the terms of the GNU General Public License as
>  * published by the Free Software Foundation; either version 2 of
>  * the License, or (at your option) any later version.
>  */
> 
> #include <common.h>
> #include <malloc.h>
> #include <init.h>
> #include <io.h>
> #include <linux/clk.h>
> 
> #include <mach/clps711x.h>
> 
> struct clps711x_uart {
> 	void __iomem		*UBRLCR;
> 	void __iomem		*SYSCON;
> 	void __iomem		*SYSFLG;
> 	void __iomem		*UARTDR;
> 	struct clk		*uart_clk;
> 	struct console_device	cdev;
> };
> 
> static int clps711x_setbaudrate(struct console_device *cdev, int baudrate)
> {
> 	struct clps711x_uart *s = cdev->dev->priv;
> 	int divisor;
> 	u32 tmp;
> 
> 	divisor = (clk_get_rate(s->uart_clk) / 16) / baudrate;
> 
> 	tmp = readl(s->UBRLCR) & ~UBRLCR_BAUD_MASK;
> 	tmp |= divisor - 1;
> 	writel(tmp, s->UBRLCR);
> 
> 	return 0;
> }
> 
> static void clps711x_init_port(struct console_device *cdev)
> {
> 	struct clps711x_uart *s = cdev->dev->priv;
> 	u32 tmp;
> 
> 	/* Disable the UART */
> 	writel(readl(s->SYSCON) & ~SYSCON_UARTEN, s->SYSCON);
> 
> 	/* Setup Line Control Register */
> 	tmp = readl(s->UBRLCR) & UBRLCR_BAUD_MASK;
> 	tmp |= UBRLCR_FIFOEN | UBRLCR_WRDLEN8; /* FIFO on, 8N1 mode */
> 	writel(tmp, s->UBRLCR);
> 
> 	/* Set default baudrate on initialization */
> 	clps711x_setbaudrate(cdev, CONFIG_BAUDRATE);
> 
> 	/* Enable the UART */
> 	writel(readl(s->SYSCON) | SYSCON_UARTEN, s->SYSCON);
> }
> 
> static void clps711x_putc(struct console_device *cdev, char c)
> {
> 	struct clps711x_uart *s = cdev->dev->priv;
> 
> 	/* Wait until there is space in the FIFO */
> 	while (readl(s->SYSFLG) & SYSFLG_UTXFF)
> 		barrier();
> 
> 	/* Send the character */
> 	writew(c, s->UARTDR);
> }
> 
> static int clps711x_getc(struct console_device *cdev)
> {
> 	struct clps711x_uart *s = cdev->dev->priv;
> 	u16 data;
> 
> 	/* Wait until there is data in the FIFO */
> 	while (readl(s->SYSFLG) & SYSFLG_URXFE)
> 		barrier();
> 
> 	data = readw(s->UARTDR);
> 
> 	/* Check for an error flag */
> 	if (data & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR))
> 		return -1;
> 
> 	return (int)data;
> }
> 
> static int clps711x_tstc(struct console_device *cdev)
> {
> 	struct clps711x_uart *s = cdev->dev->priv;
> 
> 	return !(readl(s->SYSFLG) & SYSFLG_URXFE);
> }
> 
> static void clps711x_flush(struct console_device *cdev)
> {
> 	struct clps711x_uart *s = cdev->dev->priv;
> 
> 	while (readl(s->SYSFLG) & SYSFLG_UBUSY)
> 		barrier();
> }
> 
> static int clps711x_probe(struct device_d *dev)
> {
> 	struct clps711x_uart *s;
> 
> 	BUG_ON(dev->num_resources != 4);
> 
> 	s = xzalloc(sizeof(struct clps711x_uart));
> 	s->uart_clk = clk_get(dev, NULL);
> 	BUG_ON(!s->uart_clk);

clk_get returns error pointers, you have to use IS_ERR() to test for
errors.

> 
> 	s->UBRLCR = dev_get_mem_region(dev, 0);
> 	s->SYSCON = dev_get_mem_region(dev, 1);
> 	s->SYSFLG = dev_get_mem_region(dev, 2);
> 	s->UARTDR = dev_get_mem_region(dev, 3);

From my point of view this looks ok.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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^ permalink raw reply	[flat|nested] 16+ messages in thread
end of thread, other threads:[~2012-10-23  6:38 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-10-15 16:26 [PATCH v2 1/3] ARM: Add CLPS711X architecture Alexander Shiyan
2012-10-15 16:26 ` [PATCH v2 2/3] ARM: clps711x: Add serial driver Alexander Shiyan
2012-10-15 17:58   ` Jean-Christophe PLAGNIOL-VILLARD
2012-10-15 19:00     ` Alexander Shiyan
2012-10-15 21:58     ` Sascha Hauer
2012-10-16  8:08       ` Jean-Christophe PLAGNIOL-VILLARD
2012-10-16 21:39         ` Sascha Hauer
2012-10-20 13:50           ` Alexander Shiyan
2012-10-23  6:38             ` Sascha Hauer
2012-10-15 16:26 ` [PATCH v2 3/3] ARM: clps711x: Add generic board support (CLEP7212) Alexander Shiyan
2012-10-15 18:03   ` Jean-Christophe PLAGNIOL-VILLARD
2012-10-15 19:05     ` Alexander Shiyan
2012-10-15 17:54 ` [PATCH v2 1/3] ARM: Add CLPS711X architecture Jean-Christophe PLAGNIOL-VILLARD
2012-10-15 18:56   ` Alexander Shiyan
2012-10-16  8:09     ` Jean-Christophe PLAGNIOL-VILLARD
2012-10-16 21:42       ` Sascha Hauer

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