On Wed, Dec 05, 2012 at 07:37:32PM +0100, Sascha Hauer wrote:
> On Wed, Dec 05, 2012 at 03:53:53PM +0100, Wolfram Sang wrote:
> > It could happen (1 out of 100 times) that NAND did not start up
> > correctly after warm rebooting, so barebox could not find its
> > environment or DMA timed out due to a stalled BCH. When resetting BCH
> > together with GPMI, the issue could not be observed anymore. We probably
> > need the consistent state already before sending commands to NAND.
> 
> The subject suggests that the BCH engine is resetted earlier, but
> instead of moving the reset this patch adds another reset. Is this
> intended?

Yes, I wanted to keep resetting BCH before applying a new layout. Maybe
the subject should have been named "earlier, too,". I can drop the other
check and rerun my tests if this seems overcautios to you.

Thanks,

   Wolfram

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