* [PATCH 0/7] at91: add bootstrap support
@ 2012-12-29 10:04 Jean-Christophe PLAGNIOL-VILLARD
2012-12-29 10:08 ` [PATCH 1/7] at91: add test commamd to emulate bootrom boot Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-29 10:04 UTC (permalink / raw)
To: barebox
Hi,
This patch serie introduce a common bootstrap code
aka xloder for TI and at91bootstrap for Atmel
to barebox
As I do not have with me right now a TI platform I did not switch
it to the new generic bootstrap code.
On at91 add it on the calao usb-a9263 test on nand and spi
This patch serie depends on the previous at91 patch series
The following changes since commit 9f7f67ca887b26a4488edf5fa171a78e142e0a5b:
at91: drop AT91_BASE_PIOx for soc specific one for none boot code (2012-12-29 01:37:47 +0800)
are available in the git repository at:
git://git.jcrosoft.org/barebox.git delivery/at91_bootstrap
for you to fetch changes up to 44bfbedb17c35a99aa0f9a2a16330d2928b9ba31:
at91: usb_a9263: add bootstrap version (2012-12-29 17:56:45 +0800)
----------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD (7):
at91: add test commamd to emulate bootrom boot
at91sam926x: lowlevel add external boot support
at91: sam926x: switch lowlevel param to c code
at91: usb-a9263 add lowlevel init
introduce common bootstrap code
at91: add bootstrap version
at91: usb_a9263: add bootstrap version
arch/arm/boards/at91sam9263ek/Makefile | 5 ++
arch/arm/boards/at91sam9263ek/config.h | 87 -------------------------------
arch/arm/boards/at91sam9263ek/lowlevel_init.c | 104 +++++++++++++++++++++++++++++++++++++
arch/arm/boards/mmccpu/Makefile | 5 ++
arch/arm/boards/mmccpu/config.h | 118 ------------------------------------------
arch/arm/boards/mmccpu/lowlevel_init.c | 135 ++++++++++++++++++++++++++++++++++++++++++++++++
arch/arm/boards/pm9261/Makefile | 5 ++
arch/arm/boards/pm9261/config.h | 87 -------------------------------
arch/arm/boards/pm9261/lowlevel_init.c | 102 ++++++++++++++++++++++++++++++++++++
arch/arm/boards/pm9263/Makefile | 5 ++
arch/arm/boards/pm9263/config.h | 103 ------------------------------------
arch/arm/boards/usb-a926x/Makefile | 9 ++++
arch/arm/boards/usb-a926x/config.h | 97 ++++++++++++++++++++++++++++++++++
arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c | 16 ++++++
arch/arm/boards/usb-a926x/usb_a9263_lowlevel_init.c | 111 +++++++++++++++++++++++++++++++++++++++
arch/arm/configs/usb_a9263_128mib_bootstrap_defconfig | 24 +++++++++
arch/arm/configs/usb_a9263_bootstrap_defconfig | 23 +++++++++
arch/arm/mach-at91/Kconfig | 7 +++
arch/arm/mach-at91/Makefile | 2 +
arch/arm/mach-at91/at91sam926x_lowlevel_init.c | 84 +++++++++++++++++++++---------
arch/arm/mach-at91/boot_test_cmd.c | 97 ++++++++++++++++++++++++++++++++++
arch/arm/mach-at91/bootstrap.c | 86 ++++++++++++++++++++++++++++++
arch/arm/mach-at91/include/mach/at91_lowlevel_init.h | 33 ++++++++++++
arch/arm/mach-at91/include/mach/bootstrap.h | 28 ++++++++++
include/bootstrap.h | 34 ++++++++++++
lib/Kconfig | 2 +
lib/Makefile | 1 +
lib/bootstrap/Kconfig | 13 +++++
lib/bootstrap/Makefile | 3 ++
lib/bootstrap/common.c | 21 ++++++++
lib/bootstrap/devfs.c | 98 +++++++++++++++++++++++++++++++++++
lib/bootstrap/disk.c | 36 +++++++++++++
32 files changed, 1161 insertions(+), 420 deletions(-)
create mode 100644 arch/arm/boards/at91sam9263ek/lowlevel_init.c
create mode 100644 arch/arm/boards/mmccpu/lowlevel_init.c
create mode 100644 arch/arm/boards/pm9261/lowlevel_init.c
create mode 100644 arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c
create mode 100644 arch/arm/boards/usb-a926x/usb_a9263_lowlevel_init.c
create mode 100644 arch/arm/configs/usb_a9263_128mib_bootstrap_defconfig
create mode 100644 arch/arm/configs/usb_a9263_bootstrap_defconfig
create mode 100644 arch/arm/mach-at91/boot_test_cmd.c
create mode 100644 arch/arm/mach-at91/bootstrap.c
create mode 100644 arch/arm/mach-at91/include/mach/at91_lowlevel_init.h
create mode 100644 arch/arm/mach-at91/include/mach/bootstrap.h
create mode 100644 include/bootstrap.h
create mode 100644 lib/bootstrap/Kconfig
create mode 100644 lib/bootstrap/Makefile
create mode 100644 lib/bootstrap/common.c
create mode 100644 lib/bootstrap/devfs.c
create mode 100644 lib/bootstrap/disk.c
Best Regards,
J.
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/7] at91: add test commamd to emulate bootrom boot
2012-12-29 10:04 [PATCH 0/7] at91: add bootstrap support Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-29 10:08 ` Jean-Christophe PLAGNIOL-VILLARD
2012-12-29 10:08 ` [PATCH 2/7] at91sam926x: lowlevel add external boot support Jean-Christophe PLAGNIOL-VILLARD
` (6 more replies)
0 siblings, 7 replies; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-29 10:08 UTC (permalink / raw)
To: barebox
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/mach-at91/Kconfig | 5 ++
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/boot_test_cmd.c | 97 ++++++++++++++++++++++++++++++++++++
3 files changed, 103 insertions(+)
create mode 100644 arch/arm/mach-at91/boot_test_cmd.c
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index fcba7fb..264b975 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -483,4 +483,9 @@ config CMD_AT91MUX
bool "at91mux dump command"
default y
+config CONFIG_CMD_AT91_BOOT_TEST
+ bool "at91_boot_test"
+ help
+ allow to upload a boot binary to sram and execute it
+
endif
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 53b4dd8..4404d23 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,4 +1,5 @@
obj-y += setup.o clock.o gpio.o
+obj-$(CONFIG_CMD_AT91_BOOT_TEST) += boot_test_cmd.o
lowlevel_init-y = at91sam926x_lowlevel_init.o
lowlevel_init-$(CONFIG_ARCH_AT91RM9200) = at91rm9200_lowlevel_init.o
diff --git a/arch/arm/mach-at91/boot_test_cmd.c b/arch/arm/mach-at91/boot_test_cmd.c
new file mode 100644
index 0000000..274d59e
--- /dev/null
+++ b/arch/arm/mach-at91/boot_test_cmd.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2 only
+ */
+
+#include <common.h>
+#include <command.h>
+#include <libbb.h>
+#include <getopt.h>
+#include <fs.h>
+#include <fcntl.h>
+#include <malloc.h>
+#include <errno.h>
+
+static int do_at91_boot_test(int argc, char *argv[])
+{
+ int opt;
+ u32 *buf32;
+ void *buf;
+ u32 jump = 0;
+ int fd;
+ int ret = 1;
+ char *sram = "/dev/sram0";
+ u32 read_size, write_size;
+ u32 tmp = 0;
+
+ while ((opt = getopt(argc, argv, "j:s:")) > 0) {
+ switch (opt) {
+ case 'j':
+ jump = simple_strtoul(optarg, NULL, 0);
+ break;
+ case 's':
+ sram = optarg;
+ break;
+ }
+ }
+
+ if (argc < optind + 1)
+ return COMMAND_ERROR_USAGE;
+
+ buf32 = buf = read_file(argv[optind], &read_size);
+ if (!buf)
+ return -EINVAL;
+
+ write_size = buf32[5];
+
+ printf("size of the size %d\n", read_size);
+ printf("size to load in sram %d\n", write_size);
+
+ if (write_size > read_size) {
+ printf("file smaller than requested sram loading size (%d < %d)\n", write_size, read_size);
+ goto err;
+ }
+
+ fd = open(sram, O_WRONLY);
+ if (fd < 0) {
+ printf("could not open %s: %s\n", sram, errno_str());
+ ret = fd;
+ goto err;
+ }
+
+ while(write_size) {
+ tmp = write(fd, buf, write_size);
+ if (tmp < 0) {
+ perror("write");
+ goto err_open;
+ }
+ buf += tmp;
+ write_size -= tmp;
+ }
+
+ shutdown_barebox();
+
+ __asm__ __volatile__(
+ "mov pc, %0\n"
+ :
+ : "r"(jump)
+ :);
+
+err_open:
+ close(fd);
+err:
+ free(buf);
+ return ret;
+}
+
+BAREBOX_CMD_HELP_START(at91_boot_test)
+BAREBOX_CMD_HELP_USAGE("at91_boot_test [-j <jump addr>] [-s <sram>] file\n")
+BAREBOX_CMD_HELP_SHORT("upload the binary to sram and jump as will do the romcode\n")
+BAREBOX_CMD_HELP_END
+
+BAREBOX_CMD_START(at91_boot_test)
+ .cmd = do_at91_boot_test,
+ .usage = "upload the binary to sram and jump as will do the romcode",
+ BAREBOX_CMD_HELP(cmd_at91_boot_test_help)
+BAREBOX_CMD_END
--
1.7.10.4
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/7] at91sam926x: lowlevel add external boot support
2012-12-29 10:08 ` [PATCH 1/7] at91: add test commamd to emulate bootrom boot Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-29 10:08 ` Jean-Christophe PLAGNIOL-VILLARD
2012-12-29 10:08 ` [PATCH 3/7] at91: sam926x: switch lowlevel param to c code Jean-Christophe PLAGNIOL-VILLARD
` (5 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-29 10:08 UTC (permalink / raw)
To: barebox
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/mach-at91/at91sam926x_lowlevel_init.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
index cfae982..4dec275 100644
--- a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
@@ -36,10 +36,19 @@ static void inline pmc_check_mckrdy(void)
} while (!(r & AT91_PMC_MCKRDY));
}
+static int inline running_in_sram(void)
+{
+ u32 addr = get_pc();
+
+ addr >>= 28;
+ return addr == 0;
+}
+
void __naked __bare_init reset(void)
{
u32 r;
int i;
+ int in_sram = running_in_sram();
common_reset();
@@ -74,7 +83,7 @@ void __naked __bare_init reset(void)
* PMC Check if the PLL is already initialized
*/
r = at91_pmc_read(AT91_PMC_MCKR);
- if (r & AT91_PMC_CSS)
+ if (r & AT91_PMC_CSS && !in_sram)
goto end;
/*
@@ -117,7 +126,7 @@ void __naked __bare_init reset(void)
* SDRAMC Check if Refresh Timer Counter is already initialized
*/
r = at91_sys_read(AT91_SDRAMC_TR);
- if (r)
+ if (r && !in_sram)
goto end;
/* SDRAMC_MR : Normal Mode */
@@ -170,6 +179,13 @@ void __naked __bare_init reset(void)
/* MATRIX_MCFG - REMAP all masters */
at91_sys_write(AT91_MATRIX_MCFG0, 0x1FF);
#endif
+ /*
+ * When boot from external boot
+ * we need to enable mck and ohter clock
+ * so enable all of them
+ * We will shutdown what we don't need later
+ */
+ at91_pmc_write(AT91_PMC_PCER, 0xffffffff);
end:
board_init_lowlevel_return();
--
1.7.10.4
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barebox@lists.infradead.org
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 3/7] at91: sam926x: switch lowlevel param to c code
2012-12-29 10:08 ` [PATCH 1/7] at91: add test commamd to emulate bootrom boot Jean-Christophe PLAGNIOL-VILLARD
2012-12-29 10:08 ` [PATCH 2/7] at91sam926x: lowlevel add external boot support Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-29 10:08 ` Jean-Christophe PLAGNIOL-VILLARD
2013-01-02 10:18 ` Sascha Hauer
2012-12-29 10:08 ` [PATCH 4/7] at91: usb-a9263 add lowlevel init Jean-Christophe PLAGNIOL-VILLARD
` (4 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-29 10:08 UTC (permalink / raw)
To: barebox
Instead of hardcode define use a struct that the board fill
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/boards/at91sam9263ek/Makefile | 5 +
arch/arm/boards/at91sam9263ek/config.h | 87 -------------
arch/arm/boards/at91sam9263ek/lowlevel_init.c | 104 +++++++++++++++
arch/arm/boards/mmccpu/Makefile | 5 +
arch/arm/boards/mmccpu/config.h | 118 -----------------
arch/arm/boards/mmccpu/lowlevel_init.c | 135 ++++++++++++++++++++
arch/arm/boards/pm9261/Makefile | 5 +
arch/arm/boards/pm9261/config.h | 87 -------------
arch/arm/boards/pm9261/lowlevel_init.c | 102 +++++++++++++++
arch/arm/boards/pm9263/Makefile | 5 +
arch/arm/boards/pm9263/config.h | 103 ---------------
arch/arm/mach-at91/at91sam926x_lowlevel_init.c | 64 ++++++----
.../mach-at91/include/mach/at91_lowlevel_init.h | 33 +++++
13 files changed, 435 insertions(+), 418 deletions(-)
create mode 100644 arch/arm/boards/at91sam9263ek/lowlevel_init.c
create mode 100644 arch/arm/boards/mmccpu/lowlevel_init.c
create mode 100644 arch/arm/boards/pm9261/lowlevel_init.c
create mode 100644 arch/arm/mach-at91/include/mach/at91_lowlevel_init.h
diff --git a/arch/arm/boards/at91sam9263ek/Makefile b/arch/arm/boards/at91sam9263ek/Makefile
index eb072c0..aecbc5a 100644
--- a/arch/arm/boards/at91sam9263ek/Makefile
+++ b/arch/arm/boards/at91sam9263ek/Makefile
@@ -1 +1,6 @@
obj-y += init.o
+
+lowlevel_init-y = lowlevel_init.o
+obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
+
+pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
diff --git a/arch/arm/boards/at91sam9263ek/config.h b/arch/arm/boards/at91sam9263ek/config.h
index 14eb4fe..cc12040 100644
--- a/arch/arm/boards/at91sam9263ek/config.h
+++ b/arch/arm/boards/at91sam9263ek/config.h
@@ -3,91 +3,4 @@
#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
-#define MASTER_PLL_MUL 171
-#define MASTER_PLL_DIV 14
-
-/* clocks */
-#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOSCEN | \
- (255 << 8)) /* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- AT91_PMC_OUT | \
- AT91_PMC_PLLCOUNT | /* PLL Counter */ \
- (2 << 28) | /* PLL Clock Frequency Range */ \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
-
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-
-/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
-/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
-/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
- (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
- AT91_MATRIX_EBI0_CS1A_SDRAMC)
-
-/* SDRAM */
-/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
-/* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_3 | \
- AT91_SDRAMC_DBW_32 | \
- (1 << 8) | /* Write Recovery Delay */ \
- (7 << 12) | /* Row Cycle Delay */ \
- (2 << 16) | /* Row Precharge Delay */ \
- (2 << 20) | /* Row to Column Delay */ \
- (5 << 24) | /* Active to Precharge Delay */ \
- (1 << 28)) /* Exit Self Refresh to Active Delay */
-
-/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-
-/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC_CS 0
-#define CONFIG_SYS_SMC_SETUP_VAL \
- (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
- AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
-#define CONFIG_SYS_SMC_PULSE_VAL \
- (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
- AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
-#define CONFIG_SYS_SMC_CYCLE_VAL \
- (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
-#define CONFIG_SYS_SMC_MODE_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(6))
-
-/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
- (AT91_RSTC_KEY | \
- AT91_RSTC_PROCRST | \
- AT91_RSTC_RSTTYP_WAKEUP | \
- AT91_RSTC_RSTTYP_WATCHDOG)
-
-/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
- AT91_WDT_WDV | \
- AT91_WDT_WDDIS | \
- AT91_WDT_WDD)
-
#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/at91sam9263ek/lowlevel_init.c b/arch/arm/boards/at91sam9263ek/lowlevel_init.c
new file mode 100644
index 0000000..2f8b312
--- /dev/null
+++ b/arch/arm/boards/at91sam9263ek/lowlevel_init.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/hardware.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_wdt.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9_matrix.h>
+#include <mach/at91_lowlevel_init.h>
+
+#define MASTER_PLL_MUL 171
+#define MASTER_PLL_DIV 14
+
+void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
+{
+ /* Disable Watchdog */
+ cfg->wdt_mr =
+ AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
+ AT91_WDT_WDV |
+ AT91_WDT_WDDIS |
+ AT91_WDT_WDD;
+
+ /* define PDC[31:16] as DATA[31:16] */
+ cfg->ebi_pio_pdr = 0xFFFF0000;
+ /* no pull-up for D[31:16] */
+ cfg->ebi_pio_ppudr = 0xFFFF0000;
+ /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+ cfg->ebi_csa =
+ AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
+ AT91_MATRIX_EBI0_CS1A_SDRAMC;
+
+ cfg->smc_cs = 0;
+ cfg->smc_mode =
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_DBW_16 |
+ AT91_SMC_TDFMODE |
+ AT91_SMC_TDF_(6);
+ cfg->smc_cycle =
+ AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
+ cfg->smc_pulse =
+ AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
+ AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
+ cfg->smc_setup =
+ AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
+ AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
+
+ cfg->pmc_mor =
+ AT91_PMC_MOSCEN |
+ (255 << 8); /* Main Oscillator Start-up Time */
+ cfg->pmc_pllar =
+ AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
+ AT91_PMC_OUT |
+ AT91_PMC_PLLCOUNT | /* PLL Counter */
+ (2 << 28) | /* PLL Clock Frequency Range */
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr1 =
+ AT91_PMC_CSS_SLOW |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr2 =
+ AT91_PMC_CSS_PLLA |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+
+ /* SDRAM */
+ /* SDRAMC_TR - Refresh Timer register */
+ cfg->sdrc_tr1 = 0x13C;
+ /* SDRAMC_CR - Configuration register*/
+ cfg->sdrc_cr =
+ AT91_SDRAMC_NC_9 |
+ AT91_SDRAMC_NR_13 |
+ AT91_SDRAMC_NB_4 |
+ AT91_SDRAMC_CAS_3 |
+ AT91_SDRAMC_DBW_32 |
+ (1 << 8) | /* Write Recovery Delay */
+ (7 << 12) | /* Row Cycle Delay */
+ (2 << 16) | /* Row Precharge Delay */
+ (2 << 20) | /* Row to Column Delay */
+ (5 << 24) | /* Active to Precharge Delay */
+ (1 << 28); /* Exit Self Refresh to Active Delay */
+
+ /* Memory Device Register -> SDRAM */
+ cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
+ /* SDRAM_TR */
+ cfg->sdrc_tr2 = 1200;
+
+ /* user reset enable */
+ cfg->rstc_rmr =
+ AT91_RSTC_KEY |
+ AT91_RSTC_PROCRST |
+ AT91_RSTC_RSTTYP_WAKEUP |
+ AT91_RSTC_RSTTYP_WATCHDOG;
+}
diff --git a/arch/arm/boards/mmccpu/Makefile b/arch/arm/boards/mmccpu/Makefile
index eb072c0..aecbc5a 100644
--- a/arch/arm/boards/mmccpu/Makefile
+++ b/arch/arm/boards/mmccpu/Makefile
@@ -1 +1,6 @@
obj-y += init.o
+
+lowlevel_init-y = lowlevel_init.o
+obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
+
+pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
diff --git a/arch/arm/boards/mmccpu/config.h b/arch/arm/boards/mmccpu/config.h
index e6215dc..c896a93 100644
--- a/arch/arm/boards/mmccpu/config.h
+++ b/arch/arm/boards/mmccpu/config.h
@@ -3,122 +3,4 @@
#define AT91_MAIN_CLOCK 18432000
-/* values */
-#define MASTER_PLL_MUL 54
-#define MASTER_PLL_DIV 4
-
-/* clocks */
-#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOSCEN | \
- (255 << 8)) /* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- AT91_PMC_OUT | \
- AT91_PMC_PLLCOUNT | /* PLL Counter */ \
- (2 << 28) | /* PLL Clock Frequency Range */ \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
-
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-
-/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
-/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
-/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 1.8V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
- (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_1_8V | \
- AT91_MATRIX_EBI0_CS1A_SDRAMC | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA)
-
-/* SDRAM */
-/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x13c
-/* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_3 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* tWR - Write Recovery Delay */ \
- (8 << 12) | /* tRC - Row Cycle Delay */ \
- (2 << 16) | /* tRP - Row Precharge Delay */ \
- (2 << 20) | /* tRCD - Row to Column Delay */ \
- (5 << 24) | /* tRAS - Active to Precharge Delay */ \
- (12 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
-
-/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_TR_VAL2 780 /* SDRAM_TR */
-
-/* setup CS0 (NOR Flash) - 16-bit */
-#define CONFIG_SYS_SMC_CS 0
-#if 1
-#define CONFIG_SYS_SMC_SETUP_VAL \
- (AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | \
- AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0))
-#define CONFIG_SYS_SMC_PULSE_VAL \
- (AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | \
- AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13))
-#define CONFIG_SYS_SMC_CYCLE_VAL \
- (AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16))
-#define CONFIG_SYS_SMC_MODE_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(6))
-#elif 0 /* slow setup */
-#define CONFIG_SYS_SMC_SETUP_VAL \
- (AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | \
- AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0))
-#define CONFIG_SYS_SMC_PULSE_VAL \
- (AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | \
- AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13))
-#define CONFIG_SYS_SMC_CYCLE_VAL \
- (AT91_SMC_NWECYCLE_(0xd00) | AT91_SMC_NRDCYCLE_(0xd00))
-#define CONFIG_SYS_SMC_MODE_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(1))
-#else /* RONETIX' original values */
-#define CONFIG_SYS_SMC_SETUP_VAL \
- (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
- AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
-#define CONFIG_SYS_SMC_PULSE_VAL \
- (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
- AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
-#define CONFIG_SYS_SMC_CYCLE_VAL \
- (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
-#define CONFIG_SYS_SMC_MODE_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(6))
-#endif
-
-/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
- (AT91_RSTC_KEY | \
- AT91_RSTC_PROCRST | \
- AT91_RSTC_RSTTYP_WAKEUP | \
- AT91_RSTC_RSTTYP_WATCHDOG)
-
-/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
- AT91_WDT_WDV | \
- AT91_WDT_WDDIS | \
- AT91_WDT_WDD)
-
#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/mmccpu/lowlevel_init.c b/arch/arm/boards/mmccpu/lowlevel_init.c
new file mode 100644
index 0000000..82500eb
--- /dev/null
+++ b/arch/arm/boards/mmccpu/lowlevel_init.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/hardware.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_wdt.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9_matrix.h>
+#include <mach/at91_lowlevel_init.h>
+
+#define MASTER_PLL_MUL 54
+#define MASTER_PLL_DIV 4
+
+void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
+{
+ /* Disable Watchdog */
+ cfg->wdt_mr =
+ AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
+ AT91_WDT_WDV |
+ AT91_WDT_WDDIS |
+ AT91_WDT_WDD;
+
+ /* define PDC[31:16] as DATA[31:16] */
+ cfg->ebi_pio_pdr = 0xFFFF0000;
+ /* no pull-up for D[31:16] */
+ cfg->ebi_pio_ppudr = 0xFFFF0000;
+ /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+ cfg->ebi_csa =
+ AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_1_8V |
+ AT91_MATRIX_EBI0_CS1A_SDRAMC |
+ AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA;
+
+ cfg->smc_cs = 0;
+#if 1
+ cfg->smc_mode =
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_DBW_16 |
+ AT91_SMC_TDFMODE |
+ AT91_SMC_TDF_(6);
+ cfg->smc_cycle =
+ AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16);
+ cfg->smc_pulse =
+ AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) |
+ AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13);
+ cfg->smc_setup =
+ AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) |
+ AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0);
+#elif 0
+ cfg->smc_mode =
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_DBW_16 |
+ AT91_SMC_TDFMODE |
+ AT91_SMC_TDF_(1);
+ cfg->smc_cycle =
+ AT91_SMC_NWECYCLE_(0xd00) | AT91_SMC_NRDCYCLE_(0xd00);
+ cfg->smc_pulse =
+ AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) |
+ AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13);
+ cfg->smc_setup =
+ AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) |
+ AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0);
+#else
+ cfg->smc_mode =
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_DBW_16 |
+ AT91_SMC_TDFMODE |
+ AT91_SMC_TDF_(6);
+ cfg->smc_cycle =
+ AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
+ cfg->smc_pulse =
+ AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
+ AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
+ cfg->smc_setup =
+ AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
+ AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
+#endif
+
+ cfg->pmc_mor =
+ AT91_PMC_MSCEN |
+ (255 << 8); /* Main Oscillator Start-up Time */
+ cfg->pmc_pllar =
+ AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
+ AT91_PMC_OUT |
+ AT91_PMC_PLLCOUNT | /* PLL Counter */
+ (2 << 28) | /* PLL Clock Frequency Range */
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr1 =
+ AT91_PMC_CSS_SLOW |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr2 =
+ AT91_PMC_CSS_PLLA |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+
+ /* SDRAM */
+ /* SDRAMC_TR - Refresh Timer register */
+ cfg->sdrc_tr1 = 0x13C;
+ /* SDRAMC_CR - Configuration register*/
+ cfg->sdrc_cr =
+ AT91_SDRAMC_NC_9 |
+ AT91_SDRAMC_NR_13 |
+ AT91_SDRAMC_NB_4 |
+ AT91_SDRAMC_CAS_3 |
+ AT91_SDRAMC_DBW_32 |
+ (2 << 8) | /* tWR - Write Recovery Delay */
+ (8 << 12) | /* tRC - Row Cycle Delay */
+ (2 << 16) | /* tRP - Row Precharge Delay */
+ (2 << 20) | /* tRCD - Row to Column Delay */
+ (5 << 24) | /* tRAS - Active to Precharge Delay */
+ (12 << 28); /* tXSR - Exit Self Refresh to Active Delay */
+
+ /* Memory Device Register -> SDRAM */
+ cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
+ /* SDRAM_TR */
+ cfg->sdrc_tr2 = 780;
+
+ /* user reset enable */
+ cfg->rstc_rmr =
+ AT91_RSTC_KEY |
+ AT91_RSTC_PROCRST |
+ AT91_RSTC_RSTTYP_WAKEUP |
+ AT91_RSTC_RSTTYP_WATCHDOG;
+}
diff --git a/arch/arm/boards/pm9261/Makefile b/arch/arm/boards/pm9261/Makefile
index eb072c0..aecbc5a 100644
--- a/arch/arm/boards/pm9261/Makefile
+++ b/arch/arm/boards/pm9261/Makefile
@@ -1 +1,6 @@
obj-y += init.o
+
+lowlevel_init-y = lowlevel_init.o
+obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
+
+pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
diff --git a/arch/arm/boards/pm9261/config.h b/arch/arm/boards/pm9261/config.h
index 4602aa7..006820c 100644
--- a/arch/arm/boards/pm9261/config.h
+++ b/arch/arm/boards/pm9261/config.h
@@ -3,91 +3,4 @@
#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
-#define MASTER_PLL_DIV 15
-#define MASTER_PLL_MUL 162
-#define MAIN_PLL_DIV 2
-
-/* clocks */
-#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOSCEN | \
- (255 << 8)) /* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- AT91_PMC_OUT | \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
-
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-
-/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
-/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
-
-/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
-#define CONFIG_SYS_MATRIX_EBICSA_VAL \
- (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC)
-
-/* SDRAM */
-/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
-/* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_3 | \
- AT91_SDRAMC_DBW_32 | \
- (1 << 8) | /* Write Recovery Delay */ \
- (7 << 12) | /* Row Cycle Delay */ \
- (3 << 16) | /* Row Precharge Delay */ \
- (2 << 20) | /* Row to Column Delay */ \
- (5 << 24) | /* Active to Precharge Delay */ \
- (1 << 28)) /* Exit Self Refresh to Active Delay */
-
-/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-
-/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC_CS 0
-#define CONFIG_SYS_SMC_SETUP_VAL \
- (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
- AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
-#define CONFIG_SYS_SMC_PULSE_VAL \
- (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
- AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
-#define CONFIG_SYS_SMC_CYCLE_VAL \
- (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
-#define CONFIG_SYS_SMC_MODE_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(6))
-
-/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
- (AT91_RSTC_KEY | \
- AT91_RSTC_PROCRST | \
- AT91_RSTC_RSTTYP_WAKEUP | \
- AT91_RSTC_RSTTYP_WATCHDOG)
-
-/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
- AT91_WDT_WDV | \
- AT91_WDT_WDDIS | \
- AT91_WDT_WDD)
-
#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/pm9261/lowlevel_init.c b/arch/arm/boards/pm9261/lowlevel_init.c
new file mode 100644
index 0000000..c97f398
--- /dev/null
+++ b/arch/arm/boards/pm9261/lowlevel_init.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/hardware.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_wdt.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9_matrix.h>
+#include <mach/at91_lowlevel_init.h>
+
+#define MASTER_PLL_DIV 15
+#define MASTER_PLL_MUL 162
+#define MAIN_PLL_DIV 2
+
+void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
+{
+ /* Disable Watchdog */
+ cfg->wdt_mr =
+ AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
+ AT91_WDT_WDV |
+ AT91_WDT_WDDIS |
+ AT91_WDT_WDD;
+
+ /* define PDC[31:16] as DATA[31:16] */
+ cfg->ebi_pio_pdr = 0xFFFF0000;
+ /* no pull-up for D[31:16] */
+ cfg->ebi_pio_ppudr = 0xFFFF0000;
+ /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+ cfg->ebi_csa =
+ AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC;
+
+ cfg->smc_cs = 0;
+ cfg->smc_mode =
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_DBW_16 |
+ AT91_SMC_TDFMODE |
+ AT91_SMC_TDF_(6);
+ cfg->smc_cycle =
+ AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
+ cfg->smc_pulse =
+ AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
+ AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
+ cfg->smc_setup =
+ AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
+ AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
+
+ cfg->pmc_mor =
+ AT91_PMC_MOSCEN |
+ (255 << 8); /* Main Oscillator Start-up Time */
+ cfg->pmc_pllar =
+ AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
+ AT91_PMC_OUT |
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr1 =
+ AT91_PMC_CSS_SLOW |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr2 =
+ AT91_PMC_CSS_PLLA |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+
+ /* SDRAM */
+ /* SDRAMC_TR - Refresh Timer register */
+ cfg->sdrc_tr1 = 0x13C;
+ /* SDRAMC_CR - Configuration register*/
+ cfg->sdrc_cr =
+ AT91_SDRAMC_NC_9 |
+ AT91_SDRAMC_NR_13 |
+ AT91_SDRAMC_NB_4 |
+ AT91_SDRAMC_CAS_3 |
+ AT91_SDRAMC_DBW_32 |
+ (1 << 8) | /* Write Recovery Delay */
+ (7 << 12) | /* Row Cycle Delay */
+ (3 << 16) | /* Row Precharge Delay */
+ (2 << 20) | /* Row to Column Delay */
+ (5 << 24) | /* Active to Precharge Delay */
+ (1 << 28); /* Exit Self Refresh to Active Delay */
+
+ /* Memory Device Register -> SDRAM */
+ cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
+ /* SDRAM_TR */
+ cfg->sdrc_tr2 = 1200;
+
+ /* user reset enable */
+ cfg->rstc_rmr =
+ AT91_RSTC_KEY |
+ AT91_RSTC_PROCRST |
+ AT91_RSTC_RSTTYP_WAKEUP |
+ AT91_RSTC_RSTTYP_WATCHDOG;
+}
diff --git a/arch/arm/boards/pm9263/Makefile b/arch/arm/boards/pm9263/Makefile
index eb072c0..aecbc5a 100644
--- a/arch/arm/boards/pm9263/Makefile
+++ b/arch/arm/boards/pm9263/Makefile
@@ -1 +1,6 @@
obj-y += init.o
+
+lowlevel_init-y = lowlevel_init.o
+obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
+
+pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
diff --git a/arch/arm/boards/pm9263/config.h b/arch/arm/boards/pm9263/config.h
index 322c1f3..9066613 100644
--- a/arch/arm/boards/pm9263/config.h
+++ b/arch/arm/boards/pm9263/config.h
@@ -3,107 +3,4 @@
#define AT91_MAIN_CLOCK 18432000
-#define MASTER_PLL_DIV 6
-#define MASTER_PLL_MUL 65
-#define MAIN_PLL_DIV 2 /* 2 or 4 */
-
-/* clocks */
-#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOSCEN | \
- (255 << 8)) /* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- AT91_PMC_OUT | \
- AT91_PMC_PLLCOUNT | /* PLL Counter */ \
- (2 << 28) | /* PLL Clock Frequency Range */ \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
-
-#if (MAIN_PLL_DIV == 2)
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-#else
-/* PCK/4 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91RM9200_PMC_MDIV_3 | \
- AT91_PMC_PDIV_1)
-/* PCK/4 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91RM9200_PMC_MDIV_3 | \
- AT91_PMC_PDIV_1)
-#endif
-/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
-/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
-/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
- (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
- AT91_MATRIX_EBI0_CS1A_SDRAMC)
-
-/* SDRAM */
-/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
-/* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_2 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* tWR - Write Recovery Delay */ \
- (7 << 12) | /* tRC - Row Cycle Delay */ \
- (2 << 16) | /* tRP - Row Precharge Delay */ \
- (2 << 20) | /* tRCD - Row to Column Delay */ \
- (5 << 24) | /* tRAS - Active to Precharge Delay */ \
- (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
-
-/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-
-/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC_CS 0
-#define CONFIG_SYS_SMC_SETUP_VAL \
- (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
- AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
-#define CONFIG_SYS_SMC_PULSE_VAL \
- (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
- AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
-#define CONFIG_SYS_SMC_CYCLE_VAL \
- (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
-#define CONFIG_SYS_SMC_MODE_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(6))
-
-/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
- (AT91_RSTC_KEY | \
- AT91_RSTC_PROCRST | \
- AT91_RSTC_RSTTYP_WAKEUP | \
- AT91_RSTC_RSTTYP_WATCHDOG)
-
-/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
- AT91_WDT_WDV | \
- AT91_WDT_WDDIS | \
- AT91_WDT_WDD)
-
-
#endif /* __CONFIG_H */
diff --git a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
index 4dec275..e7145b4 100644
--- a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
@@ -19,8 +19,10 @@
#include <mach/at91sam9_matrix.h>
#include <mach/at91sam9_sdramc.h>
#include <mach/at91sam9_smc.h>
+#include <mach/at91_lowlevel_init.h>
#include <mach/io.h>
#include <init.h>
+#include <sizes.h>
static void inline access_sdram(void)
{
@@ -44,40 +46,41 @@ static int inline running_in_sram(void)
return addr == 0;
}
-void __naked __bare_init reset(void)
+void __bare_init at91sam926x_lowlevel_init(void)
{
u32 r;
int i;
int in_sram = running_in_sram();
+ struct at91sam926x_lowlevel_cfg cfg;
- common_reset();
+ at91sam926x_lowlevel_board_config(&cfg);
- __raw_writel(CONFIG_SYS_WDTC_WDMR_VAL, AT91_BASE_WDT + AT91_WDT_MR);
+ __raw_writel(cfg.wdt_mr, AT91_BASE_WDT + AT91_WDT_MR);
/* configure PIOx as EBI0 D[16-31] */
#ifdef CONFIG_ARCH_AT91SAM9263
- __raw_writel(CONFIG_SYS_PIOD_PDR_VAL1, AT91_BASE_PIOD + PIO_PDR);
- __raw_writel(CONFIG_SYS_PIOD_PPUDR_VAL, AT91_BASE_PIOD + PIO_PUDR);
- __raw_writel(CONFIG_SYS_PIOD_PPUDR_VAL, AT91_BASE_PIOD + PIO_ASR);
+ __raw_writel(cfg.ebi_pio_pdr, AT91_BASE_PIOD + PIO_PDR);
+ __raw_writel(cfg.ebi_pio_ppudr, AT91_BASE_PIOD + PIO_PUDR);
+ __raw_writel(cfg.ebi_pio_ppudr, AT91_BASE_PIOD + PIO_ASR);
#else
- __raw_writel(CONFIG_SYS_PIOC_PDR_VAL1, AT91_BASE_PIOC + PIO_PDR);
- __raw_writel(CONFIG_SYS_PIOC_PPUDR_VAL, AT91_BASE_PIOC + PIO_PUDR);
+ __raw_writel(cfg.ebi_pio_pdr, AT91_BASE_PIOC + PIO_PDR);
+ __raw_writel(cfg.ebi_pio_ppudrL, AT91_BASE_PIOC + PIO_PUDR);
#endif
#if defined(AT91_MATRIX_EBI0CSA)
- at91_sys_write(AT91_MATRIX_EBI0CSA, CONFIG_SYS_MATRIX_EBI0CSA_VAL);
+ at91_sys_write(AT91_MATRIX_EBI0CSA, cfg.ebi_csa);
#else /* AT91_MATRIX_EBICSA */
- at91_sys_write(AT91_MATRIX_EBICSA, CONFIG_SYS_MATRIX_EBICSA_VAL);
+ at91_sys_write(AT91_MATRIX_EBICSA, cfg.ebi_csa);
#endif
/* flash */
- at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_MODE, CONFIG_SYS_SMC_MODE_VAL);
+ at91_smc_write(cfg.smc_cs, AT91_SMC_MODE, cfg.smc_mode);
- at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_CYCLE, CONFIG_SYS_SMC_CYCLE_VAL);
+ at91_smc_write(cfg.smc_cs, AT91_SMC_CYCLE, cfg.smc_cycle);
- at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_PULSE, CONFIG_SYS_SMC_PULSE_VAL);
+ at91_smc_write(cfg.smc_cs, AT91_SMC_PULSE, cfg.smc_pulse);
- at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_SETUP, CONFIG_SYS_SMC_SETUP_VAL);
+ at91_smc_write(cfg.smc_cs, AT91_SMC_SETUP, cfg.smc_setup);
/*
* PMC Check if the PLL is already initialized
@@ -89,7 +92,7 @@ void __naked __bare_init reset(void)
/*
* Enable the Main Oscillator
*/
- at91_pmc_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL);
+ at91_pmc_write(AT91_CKGR_MOR, cfg.pmc_mor);
do {
r = at91_pmc_read(AT91_PMC_SR);
@@ -98,7 +101,7 @@ void __naked __bare_init reset(void)
/*
* PLLAR: x MHz for PCK
*/
- at91_pmc_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL);
+ at91_pmc_write(AT91_CKGR_PLLAR, cfg.pmc_pllar);
do {
r = at91_pmc_read(AT91_PMC_SR);
@@ -107,14 +110,14 @@ void __naked __bare_init reset(void)
/*
* PCK/x = MCK Master Clock from SLOW
*/
- at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR1_VAL);
+ at91_pmc_write(AT91_PMC_MCKR, cfg.pmc_mckr1);
pmc_check_mckrdy();
/*
* PCK/x = MCK Master Clock from PLLA
*/
- at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL);
+ at91_pmc_write(AT91_PMC_MCKR, cfg.pmc_mckr2);
pmc_check_mckrdy();
@@ -133,13 +136,13 @@ void __naked __bare_init reset(void)
at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
/* SDRAMC_TR - Refresh Timer register */
- at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL1);
+ at91_sys_write(AT91_SDRAMC_TR, cfg.sdrc_tr1);
/* SDRAMC_CR - Configuration register*/
- at91_sys_write(AT91_SDRAMC_CR, CONFIG_SYS_SDRC_CR_VAL);
+ at91_sys_write(AT91_SDRAMC_CR, cfg.sdrc_cr);
/* Memory Device Type */
- at91_sys_write(AT91_SDRAMC_MDR, CONFIG_SYS_SDRC_MDR_VAL);
+ at91_sys_write(AT91_SDRAMC_MDR, cfg.sdrc_mdr);
/* SDRAMC_MR : Precharge All */
at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
@@ -167,13 +170,13 @@ void __naked __bare_init reset(void)
access_sdram();
/* SDRAMC_TR : Refresh Timer Counter */
- at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL2);
+ at91_sys_write(AT91_SDRAMC_TR, cfg.sdrc_tr2);
/* access SDRAM */
access_sdram();
/* User reset enable*/
- at91_sys_write(AT91_RSTC_MR, CONFIG_SYS_RSTC_RMR_VAL);
+ at91_sys_write(AT91_RSTC_MR, cfg.rstc_rmr);
#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
/* MATRIX_MCFG - REMAP all masters */
@@ -190,3 +193,18 @@ void __naked __bare_init reset(void)
end:
board_init_lowlevel_return();
}
+
+void __naked __bare_init reset(void)
+{
+ common_reset();
+
+#ifdef CONFIG_ARCH_AT91SAM9263
+ arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE - 16);
+#elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10)
+ arm_setup_stack(AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 16);
+#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
+ arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16);
+#endif
+
+ at91sam926x_lowlevel_init();
+}
diff --git a/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h b/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h
new file mode 100644
index 0000000..29d9628
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#ifndef __AT91_LOWLEVEL_INIT_H__
+#define __AT91_LOWLEVEL_INIT_H__
+
+struct at91sam926x_lowlevel_cfg {
+ u32 wdt_mr;
+ u32 ebi_pio_pdr;
+ u32 ebi_pio_ppudr;
+ u32 ebi_csa;
+ u32 smc_cs;
+ u32 smc_mode;
+ u32 smc_cycle;
+ u32 smc_pulse;
+ u32 smc_setup;
+ u32 pmc_mor;
+ u32 pmc_pllar;
+ u32 pmc_mckr1;
+ u32 pmc_mckr2;
+ u32 sdrc_cr;
+ u32 sdrc_tr1;
+ u32 sdrc_mdr;
+ u32 sdrc_tr2;
+ u32 rstc_rmr;
+};
+
+void at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg);
+
+#endif /* __AT91_LOWLEVEL_INIT_H__ */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 4/7] at91: usb-a9263 add lowlevel init
2012-12-29 10:08 ` [PATCH 1/7] at91: add test commamd to emulate bootrom boot Jean-Christophe PLAGNIOL-VILLARD
2012-12-29 10:08 ` [PATCH 2/7] at91sam926x: lowlevel add external boot support Jean-Christophe PLAGNIOL-VILLARD
2012-12-29 10:08 ` [PATCH 3/7] at91: sam926x: switch lowlevel param to c code Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-29 10:08 ` Jean-Christophe PLAGNIOL-VILLARD
2012-12-29 10:08 ` [PATCH 5/7] introduce common bootstrap code Jean-Christophe PLAGNIOL-VILLARD
` (3 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-29 10:08 UTC (permalink / raw)
To: barebox
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/boards/usb-a926x/Makefile | 6 ++
arch/arm/boards/usb-a926x/config.h | 97 +++++++++++++++++
.../arm/boards/usb-a926x/usb_a9263_lowlevel_init.c | 111 ++++++++++++++++++++
arch/arm/mach-at91/Kconfig | 1 +
4 files changed, 215 insertions(+)
create mode 100644 arch/arm/boards/usb-a926x/usb_a9263_lowlevel_init.c
diff --git a/arch/arm/boards/usb-a926x/Makefile b/arch/arm/boards/usb-a926x/Makefile
index eb072c0..9511a76 100644
--- a/arch/arm/boards/usb-a926x/Makefile
+++ b/arch/arm/boards/usb-a926x/Makefile
@@ -1 +1,7 @@
obj-y += init.o
+
+lowlevel_init-$(CONFIG_MACH_USB_A9263) = usb_a9263_lowlevel_init.o
+
+obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
+
+pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
diff --git a/arch/arm/boards/usb-a926x/config.h b/arch/arm/boards/usb-a926x/config.h
index d971810..bb1498f 100644
--- a/arch/arm/boards/usb-a926x/config.h
+++ b/arch/arm/boards/usb-a926x/config.h
@@ -3,4 +3,101 @@
#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
+#ifdef CONFIG_MACH_USB_A9263
+#define MASTER_CLOCK 180
+
+#if MASTER_CLOCK == 200
+#define MASTER_PLL_MUL 100
+#else
+#define MASTER_PLL_MUL 90
+#endif
+#define MASTER_PLL_DIV 6
+
+/* clocks */
+#define CONFIG_SYS_MOR_VAL AT91_PMC_OSCBYPASS
+#define CONFIG_SYS_PLLAR_VAL \
+ (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
+ AT91_PMC_PLLCOUNT | /* PLL Counter */ \
+ (0 << 28) | /* PLL Clock Frequency Range */ \
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define CONFIG_SYS_MCKR1_VAL \
+ (AT91_PMC_CSS_SLOW | \
+ AT91_PMC_PRES_1 | \
+ AT91SAM9_PMC_MDIV_2 | \
+ AT91_PMC_PDIV_1)
+/* PCK/2 = MCK Master Clock from PLLA */
+#define CONFIG_SYS_MCKR2_VAL \
+ (AT91_PMC_CSS_PLLA | \
+ AT91_PMC_PRES_1 | \
+ AT91SAM9_PMC_MDIV_2 | \
+ AT91_PMC_PDIV_1)
+
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
+/* no pull-up for D[31:16] */
+#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
+/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
+ (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
+ AT91_MATRIX_EBI0_CS1A_SDRAMC)
+
+/* SDRAM */
+/* SDRAMC_TR - Refresh Timer register */
+#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
+/* SDRAMC_CR - Configuration register*/
+#ifdef CONFIG_AT91_HAVE_SRAM_128M
+#define BOARD_NC AT91_SDRAMC_NC_10
+#else
+#define BOARD_NC AT91_SDRAMC_NC_9
+#endif
+#define CONFIG_SYS_SDRC_CR_VAL \
+ (BOARD_NC | \
+ AT91_SDRAMC_NR_13 | \
+ AT91_SDRAMC_NB_4 | \
+ AT91_SDRAMC_CAS_2 | \
+ AT91_SDRAMC_DBW_32 | \
+ (2 << 8) | /* Write Recovery Delay */ \
+ (7 << 12) | /* Row Cycle Delay */ \
+ (2 << 16) | /* Row Precharge Delay */ \
+ (2 << 20) | /* Row to Column Delay */ \
+ (5 << 24) | /* Active to Precharge Delay */ \
+ (8 << 28)) /* Exit Self Refresh to Active Delay */
+
+/* Memory Device Register -> SDRAM */
+#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_TR_VAL2 (MASTER_CLOCK * 7) /* SDRAM_TR */
+
+/* setup SMC3, Nand Flash */
+#define CONFIG_SYS_SMC_CS 3
+#define CONFIG_SYS_SMC_SETUP_VAL \
+ (AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | \
+ AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0))
+#define CONFIG_SYS_SMC_PULSE_VAL \
+ (AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | \
+ AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3))
+#define CONFIG_SYS_SMC_CYCLE_VAL \
+ (AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5))
+#define CONFIG_SYS_SMC_MODE_VAL \
+ (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
+ AT91_SMC_DBW_8 | \
+ AT91_SMC_EXNWMODE_DISABLE | \
+ AT91_SMC_TDF_(2))
+#endif
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL \
+ (AT91_RSTC_KEY | \
+ AT91_RSTC_PROCRST | \
+ AT91_RSTC_RSTTYP_WAKEUP | \
+ AT91_RSTC_RSTTYP_WATCHDOG)
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL \
+ (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
+ AT91_WDT_WDV | \
+ AT91_WDT_WDDIS | \
+ AT91_WDT_WDD)
+
#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel_init.c b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel_init.c
new file mode 100644
index 0000000..f6dc58e
--- /dev/null
+++ b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel_init.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/hardware.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_wdt.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9_matrix.h>
+#include <mach/at91_lowlevel_init.h>
+
+#define MASTER_CLOCK 180
+
+#if MASTER_CLOCK == 200
+#define MASTER_PLL_MUL 100
+#else
+#define MASTER_PLL_MUL 90
+#endif
+#define MASTER_PLL_DIV 6
+
+void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
+{
+ /* Disable Watchdog */
+ cfg->wdt_mr =
+ AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
+ AT91_WDT_WDV |
+ AT91_WDT_WDDIS |
+ AT91_WDT_WDD;
+
+ /* define PDC[31:16] as DATA[31:16] */
+ cfg->ebi_pio_pdr = 0xFFFF0000;
+ /* no pull-up for D[31:16] */
+ cfg->ebi_pio_ppudr = 0xFFFF0000;
+ /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+ cfg->ebi_csa =
+ AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
+ AT91_MATRIX_EBI0_CS1A_SDRAMC;
+
+ cfg->smc_cs = 3;
+ cfg->smc_mode =
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_DBW_8 |
+ AT91_SMC_EXNWMODE_DISABLE |
+ AT91_SMC_TDF_(2);
+ cfg->smc_cycle =
+ AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5);
+ cfg->smc_pulse =
+ AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+ AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3);
+ cfg->smc_setup =
+ AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0);
+
+ cfg->pmc_mor = AT91_PMC_OSCBYPASS;
+ cfg->pmc_pllar =
+ AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
+ AT91_PMC_PLLCOUNT | /* PLL Counter */
+ (0 << 28) | /* PLL Clock Frequency Range */
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr1 =
+ AT91_PMC_CSS_SLOW |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr2 =
+ AT91_PMC_CSS_PLLA |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+
+ /* SDRAM */
+ /* SDRAMC_TR - Refresh Timer register */
+ cfg->sdrc_tr1 = 0x13C;
+ /* SDRAMC_CR - Configuration register*/
+ cfg->sdrc_cr =
+ AT91_SDRAMC_NR_13 |
+ AT91_SDRAMC_NB_4 |
+ AT91_SDRAMC_CAS_2 |
+ AT91_SDRAMC_DBW_32 |
+ (2 << 8) | /* Write Recovery Delay */
+ (7 << 12) | /* Row Cycle Delay */
+ (2 << 16) | /* Row Precharge Delay */
+ (2 << 20) | /* Row to Column Delay */
+ (5 << 24) | /* Active to Precharge Delay */
+ (8 << 28); /* Exit Self Refresh to Active Delay */
+
+ if (IS_ENABLED(CONFIG_AT91_HAVE_SRAM_128M))
+ cfg->sdrc_cr |= AT91_SDRAMC_NC_10;
+ else
+ cfg->sdrc_cr |= AT91_SDRAMC_NC_9;
+
+ /* Memory Device Register -> SDRAM */
+ cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
+ /* SDRAM_TR */
+ cfg->sdrc_tr2 = (MASTER_CLOCK * 7);
+
+ /* user reset enable */
+ cfg->rstc_rmr =
+ AT91_RSTC_KEY |
+ AT91_RSTC_PROCRST |
+ AT91_RSTC_RSTTYP_WAKEUP |
+ AT91_RSTC_RSTTYP_WATCHDOG;
+}
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 264b975..7740de5 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -357,6 +357,7 @@ config MACH_TNY_A9263
config MACH_USB_A9263
bool "CALAO USB-A9263"
+ select MACH_HAS_LOWLEVEL_INIT
help
Select this if you are using a Calao Systems USB-A9263.
<http://www.calao-systems.com>
--
1.7.10.4
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 5/7] introduce common bootstrap code
2012-12-29 10:08 ` [PATCH 1/7] at91: add test commamd to emulate bootrom boot Jean-Christophe PLAGNIOL-VILLARD
` (2 preceding siblings ...)
2012-12-29 10:08 ` [PATCH 4/7] at91: usb-a9263 add lowlevel init Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-29 10:08 ` Jean-Christophe PLAGNIOL-VILLARD
2012-12-29 10:08 ` [PATCH 6/7] at91: add bootstrap version Jean-Christophe PLAGNIOL-VILLARD
` (2 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-29 10:08 UTC (permalink / raw)
To: barebox
This will allow to have a generic code to create different bootstrap
As example
Barebox as TI Xloader
Barebox as AT91 Bootstrap
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
include/bootstrap.h | 34 +++++++++++++++++
lib/Kconfig | 2 +
lib/Makefile | 1 +
lib/bootstrap/Kconfig | 13 +++++++
lib/bootstrap/Makefile | 3 ++
lib/bootstrap/common.c | 21 +++++++++++
lib/bootstrap/devfs.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++++
lib/bootstrap/disk.c | 36 ++++++++++++++++++
8 files changed, 208 insertions(+)
create mode 100644 include/bootstrap.h
create mode 100644 lib/bootstrap/Kconfig
create mode 100644 lib/bootstrap/Makefile
create mode 100644 lib/bootstrap/common.c
create mode 100644 lib/bootstrap/devfs.c
create mode 100644 lib/bootstrap/disk.c
diff --git a/include/bootstrap.h b/include/bootstrap.h
new file mode 100644
index 0000000..26e9dbc
--- /dev/null
+++ b/include/bootstrap.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#ifndef __BOOSTRAP_H__
+#define __BOOSTRAP_H__
+
+#define bootstrap_err(fmt, arg...) printf(fmt, ##arg)
+
+void bootstrap_boot(int (*func)(void), bool barebox);
+
+#ifdef CONFIG_BOOTSTRAP_DEVFS
+void* bootstrap_read_devfs(char *devname, bool use_bb, int offset,
+ int default_size, int max_size);
+#else
+static inline void* bootstrap_read_devfs(char *devname, bool use_bb, int offset,
+ int default_size, int max_size)
+{
+ return NULL;
+}
+#endif
+
+#ifdef CONFIG_BOOTSTRAP_DISK
+void* bootstrap_read_disk(char *devname);
+#else
+static inline void* bootstrap_read_disk(char *devname)
+{
+ return NULL;
+}
+#endif
+
+#endif /* __BOOSTRAP_H__ */
diff --git a/lib/Kconfig b/lib/Kconfig
index db8a6ad..4578353 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -52,4 +52,6 @@ config LIBMTD
source lib/gui/Kconfig
+source lib/bootstrap/Kconfig
+
endmenu
diff --git a/lib/Makefile b/lib/Makefile
index 85f4ec9..43f6ea3 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_BOOTSTRAP) += bootstrap/
obj-y += ctype.o
obj-y += rbtree.o
obj-y += display_options.o
diff --git a/lib/bootstrap/Kconfig b/lib/bootstrap/Kconfig
new file mode 100644
index 0000000..558da00
--- /dev/null
+++ b/lib/bootstrap/Kconfig
@@ -0,0 +1,13 @@
+menuconfig BOOTSTRAP
+ bool "Library bootstrap routines "
+ depends on SHELL_NONE
+
+if BOOTSTRAP
+
+config BOOTSTRAP_DEVFS
+ bool "devfs support"
+
+config BOOTSTRAP_DISK
+ bool "disk support"
+
+endif
diff --git a/lib/bootstrap/Makefile b/lib/bootstrap/Makefile
new file mode 100644
index 0000000..cbaa49f
--- /dev/null
+++ b/lib/bootstrap/Makefile
@@ -0,0 +1,3 @@
+obj-y += common.o
+obj-$(CONFIG_BOOTSTRAP_DEVFS) += devfs.o
+obj-$(CONFIG_BOOTSTRAP_DISK) += disk.o
diff --git a/lib/bootstrap/common.c b/lib/bootstrap/common.c
new file mode 100644
index 0000000..bca3eb7
--- /dev/null
+++ b/lib/bootstrap/common.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <bootstrap.h>
+#include <filetype.h>
+
+void bootstrap_boot(int (*func)(void), bool barebox)
+{
+ if (barebox && !is_barebox_arm_head((void*)func))
+ return;
+
+ shutdown_barebox();
+ func();
+
+ while (1);
+}
diff --git a/lib/bootstrap/devfs.c b/lib/bootstrap/devfs.c
new file mode 100644
index 0000000..1da9920
--- /dev/null
+++ b/lib/bootstrap/devfs.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <partition.h>
+#include <nand.h>
+#include <driver.h>
+#include <linux/mtd/mtd.h>
+#include <fcntl.h>
+#include <filetype.h>
+#include <sizes.h>
+#include <errno.h>
+#include <malloc.h>
+#include <bootstrap.h>
+
+static void *read_image_head(const char *name)
+{
+ void *header = xmalloc(ARM_HEAD_SIZE);
+ struct cdev *cdev;
+ int ret;
+
+ cdev = cdev_open(name, O_RDONLY);
+ if (!cdev) {
+ bootstrap_err("failed to open partition\n");
+ return NULL;
+ }
+
+ ret = cdev_read(cdev, header, ARM_HEAD_SIZE, 0, 0);
+ cdev_close(cdev);
+
+ if (ret != ARM_HEAD_SIZE) {
+ bootstrap_err("failed to read from partition\n");
+ return NULL;
+ }
+
+ return header;
+}
+
+static unsigned int get_image_size(void *head)
+{
+ unsigned int ret = 0;
+ unsigned int *psize = head + ARM_HEAD_SIZE_OFFSET;
+
+ if (is_barebox_arm_head(head))
+ ret = *psize;
+ debug("Detected barebox image size %u\n", ret);
+
+ return ret;
+}
+
+void* bootstrap_read_devfs(char *devname, bool use_bb, int offset,
+ int default_size, int max_size)
+{
+ int ret;
+ int size = 0;
+ void *to, *header;
+ struct cdev *cdev;
+ char *partname = "x";
+
+ devfs_add_partition(devname, offset, max_size, DEVFS_PARTITION_FIXED, partname);
+ if (use_bb) {
+ dev_add_bb_dev(partname, "bbx");
+ partname = "bbx";
+ }
+
+ header = read_image_head(partname);
+ if (header) {
+ size = get_image_size(header);
+ if (!size)
+ bootstrap_err("%s: failed to get image size\n", devname);
+ }
+
+ if (!size) {
+ size = default_size;
+ bootstrap_err("%s: failed to detect barebox and it's image size so use %d\n",
+ devname, size);
+ }
+
+ to = xmalloc(size);
+
+ cdev = cdev_open(partname, O_RDONLY);
+ if (!cdev) {
+ bootstrap_err("%s: failed to open %s\n", devname, partname);
+ return NULL;
+ }
+
+ ret = cdev_read(cdev, to, size, 0, 0);
+ if (ret != size) {
+ bootstrap_err("%s: failed to read from %s\n", devname, partname);
+ return NULL;
+ }
+
+ return to;
+}
diff --git a/lib/bootstrap/disk.c b/lib/bootstrap/disk.c
new file mode 100644
index 0000000..647f608
--- /dev/null
+++ b/lib/bootstrap/disk.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <fs.h>
+#include <fcntl.h>
+#include <sizes.h>
+#include <errno.h>
+#include <malloc.h>
+
+void* bootstrap_read_disk(char *devname)
+{
+ int ret;
+ void *buf;
+ int len;
+ char *path = "/";
+
+ ret = mount(dev, "fat", path);
+ if (ret) {
+ boot_err("mounting %s failed with %d\n", dev, ret);
+ return NULL;
+ }
+
+ buf = read_file("/barebox.bin", &len);
+ if (!buf) {
+ boot_err("could not read barebox.bin from %s\n", dev);
+ umount(path);
+ return NULL;
+ }
+
+ return buf;
+}
--
1.7.10.4
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 6/7] at91: add bootstrap version
2012-12-29 10:08 ` [PATCH 1/7] at91: add test commamd to emulate bootrom boot Jean-Christophe PLAGNIOL-VILLARD
` (3 preceding siblings ...)
2012-12-29 10:08 ` [PATCH 5/7] introduce common bootstrap code Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-29 10:08 ` Jean-Christophe PLAGNIOL-VILLARD
2013-01-02 11:41 ` Jan Lübbe
2012-12-29 10:08 ` [PATCH 7/7] at91: usb_a9263: " Jean-Christophe PLAGNIOL-VILLARD
2013-01-02 10:10 ` [PATCH 1/7] at91: add test commamd to emulate bootrom boot Sascha Hauer
6 siblings, 1 reply; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-29 10:08 UTC (permalink / raw)
To: barebox
This will allow to boot from NAND/MMC and others.
This version of bootstrap is a non shell version of barebox compressed by the
pbl.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/mach-at91/Kconfig | 1 +
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/bootstrap.c | 86 +++++++++++++++++++++++++++
arch/arm/mach-at91/include/mach/bootstrap.h | 28 +++++++++
4 files changed, 116 insertions(+)
create mode 100644 arch/arm/mach-at91/bootstrap.c
create mode 100644 arch/arm/mach-at91/include/mach/bootstrap.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 7740de5..c1c4aaf 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -92,6 +92,7 @@ config SOC_AT91SAM9263
select HAVE_AT91_DBGU1
select HAS_MACB
select AT91SAM9_RESET
+ select HAVE_NOSHELL
config SOC_AT91SAM9G45
bool
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 4404d23..e582f1a 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,6 +1,7 @@
obj-y += setup.o clock.o gpio.o
obj-$(CONFIG_CMD_AT91_BOOT_TEST) += boot_test_cmd.o
+obj-$(CONFIG_SHELL_NONE) += bootstrap.o
lowlevel_init-y = at91sam926x_lowlevel_init.o
lowlevel_init-$(CONFIG_ARCH_AT91RM9200) = at91rm9200_lowlevel_init.o
obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
diff --git a/arch/arm/mach-at91/bootstrap.c b/arch/arm/mach-at91/bootstrap.c
new file mode 100644
index 0000000..2ec16f1
--- /dev/null
+++ b/arch/arm/mach-at91/bootstrap.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <bootstrap.h>
+#include <mach/bootstrap.h>
+#include <sizes.h>
+#include <malloc.h>
+
+#if defined(CONFIG_MCI_ATMEL)
+#define is_mmc() 1
+#else
+#define is_mmc() 0
+#endif
+
+#ifdef CONFIG_NAND_ATMEL
+#define is_nand() 1
+#else
+#define is_nand() 0
+#endif
+
+#ifdef CONFIG_MTD_M25P80
+#define is_m25p80() 1
+#else
+#define is_m25p80() 0
+#endif
+
+#ifdef CONFIG_MTD_DATAFLASH
+#define is_dataflash() 1
+#else
+#define is_dataflash() 0
+#endif
+
+static void boot_seq(bool is_barebox)
+{
+ char *name = is_barebox ? "barebox" : "unknown";
+ int (*func)(void) = NULL;
+
+ if (is_m25p80()) {
+ func = bootstrap_board_read_m25p80();
+ printf("Boot %s from m25p80\n", name);
+ bootstrap_boot(func, is_barebox);
+ bootstrap_err("... failled\n");
+ free(func);
+ }
+ if (is_dataflash()) {
+ printf("Boot %s from dataflash\n", name);
+ func = bootstrap_board_read_dataflash();
+ bootstrap_boot(func, is_barebox);
+ bootstrap_err("... failled\n");
+ free(func);
+ }
+ if (is_nand()) {
+ printf("Boot %s from nand\n", name);
+ func = bootstrap_read_devfs("nand0", true, SZ_128K, SZ_256K, SZ_1M);
+ bootstrap_boot(func, is_barebox);
+ bootstrap_err("... failled\n");
+ free(func);
+ }
+}
+
+int run_shell(void)
+{
+ int (*func)(void) = NULL;
+
+ if (is_mmc()) {
+ printf("Boot from mmc\n");
+ func = bootstrap_read_disk("disk0.0");
+ bootstrap_boot(func, false);
+ bootstrap_err("... failled\n");
+ free(func);
+ }
+
+ /* First only bootstrap_boot a barebox */
+ boot_seq(true);
+ /* Second bootstrap_boot any */
+ boot_seq(false);
+
+ bootstrap_err("bootstrap_booting failed\n");
+ while (1);
+
+ return 0;
+}
diff --git a/arch/arm/mach-at91/include/mach/bootstrap.h b/arch/arm/mach-at91/include/mach/bootstrap.h
new file mode 100644
index 0000000..a3d19dd
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/bootstrap.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#ifndef __MACH_BOOTSTRAP_H__
+#define __MACH_BOOTSTRAP_H__
+
+#ifdef CONFIG_MTD_M25P80
+void * bootstrap_board_read_m25p80(void);
+#else
+static inline void * bootstrap_board_read_m25p80(void)
+{
+ return NULL;
+}
+#endif
+
+#ifdef CONFIG_MTD_DATAFLASH
+void * bootstrap_board_read_dataflash(void);
+#else
+static inline void * bootstrap_board_read_dataflash(void)
+{
+ return NULL;
+}
+#endif
+
+#endif /* __MACH_BOOTSTRAP_H__ */
--
1.7.10.4
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 7/7] at91: usb_a9263: add bootstrap version
2012-12-29 10:08 ` [PATCH 1/7] at91: add test commamd to emulate bootrom boot Jean-Christophe PLAGNIOL-VILLARD
` (4 preceding siblings ...)
2012-12-29 10:08 ` [PATCH 6/7] at91: add bootstrap version Jean-Christophe PLAGNIOL-VILLARD
@ 2012-12-29 10:08 ` Jean-Christophe PLAGNIOL-VILLARD
2013-01-02 10:10 ` [PATCH 1/7] at91: add test commamd to emulate bootrom boot Sascha Hauer
6 siblings, 0 replies; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-12-29 10:08 UTC (permalink / raw)
To: barebox
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/boards/usb-a926x/Makefile | 3 +++
arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c | 16 +++++++++++++
.../configs/usb_a9263_128mib_bootstrap_defconfig | 24 ++++++++++++++++++++
arch/arm/configs/usb_a9263_bootstrap_defconfig | 23 +++++++++++++++++++
4 files changed, 66 insertions(+)
create mode 100644 arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c
create mode 100644 arch/arm/configs/usb_a9263_128mib_bootstrap_defconfig
create mode 100644 arch/arm/configs/usb_a9263_bootstrap_defconfig
diff --git a/arch/arm/boards/usb-a926x/Makefile b/arch/arm/boards/usb-a926x/Makefile
index 9511a76..4c8cd64 100644
--- a/arch/arm/boards/usb-a926x/Makefile
+++ b/arch/arm/boards/usb-a926x/Makefile
@@ -1,5 +1,8 @@
obj-y += init.o
+bootstrap-$(CONFIG_MACH_USB_A9263) = usb_a9263_bootstrap.o
+obj-$(CONFIG_BOOTSTRAP) += $(bootstrap-y)
+
lowlevel_init-$(CONFIG_MACH_USB_A9263) = usb_a9263_lowlevel_init.o
obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
diff --git a/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c b/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c
new file mode 100644
index 0000000..368c677
--- /dev/null
+++ b/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <bootstrap.h>
+#include <mach/bootstrap.h>
+
+#ifdef CONFIG_MTD_DATAFLASH
+void * bootstrap_board_read_dataflash(void)
+{
+ return bootstrap_read_devfs("dataflash0", false, 0xffc0, 204864, 204864);
+}
+#endif
diff --git a/arch/arm/configs/usb_a9263_128mib_bootstrap_defconfig b/arch/arm/configs/usb_a9263_128mib_bootstrap_defconfig
new file mode 100644
index 0000000..c4114a8
--- /dev/null
+++ b/arch/arm/configs/usb_a9263_128mib_bootstrap_defconfig
@@ -0,0 +1,24 @@
+CONFIG_ARCH_AT91SAM9263=y
+CONFIG_MACH_USB_A9263=y
+CONFIG_AT91_HAVE_SRAM_128M=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x12000
+CONFIG_AEABI=y
+# CONFIG_CMD_ARM_CPUINFO is not set
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ENVIRONMENT_VARIABLES=y
+CONFIG_PBL_IMAGE=y
+CONFIG_MMU=y
+CONFIG_MALLOC_DUMMY=y
+CONFIG_PROMPT="USB-9263:"
+CONFIG_SHELL_NONE=y
+# CONFIG_DEFAULT_ENVIRONMENT is not set
+# CONFIG_SPI is not set
+CONFIG_MTD=y
+# CONFIG_MTD_WRITE is not set
+# CONFIG_MTD_OOB_DEVICE is not set
+CONFIG_NAND=y
+# CONFIG_NAND_ECC_HW is not set
+# CONFIG_NAND_ECC_HW_SYNDROME is not set
+# CONFIG_NAND_ECC_HW_NONE is not set
+CONFIG_NAND_ATMEL=y
+# CONFIG_FS_RAMFS is not set
diff --git a/arch/arm/configs/usb_a9263_bootstrap_defconfig b/arch/arm/configs/usb_a9263_bootstrap_defconfig
new file mode 100644
index 0000000..6751dad
--- /dev/null
+++ b/arch/arm/configs/usb_a9263_bootstrap_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARCH_AT91SAM9263=y
+CONFIG_MACH_USB_A9263=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x12000
+CONFIG_AEABI=y
+# CONFIG_CMD_ARM_CPUINFO is not set
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ENVIRONMENT_VARIABLES=y
+CONFIG_PBL_IMAGE=y
+CONFIG_MMU=y
+CONFIG_MALLOC_DUMMY=y
+CONFIG_PROMPT="USB-9263:"
+CONFIG_SHELL_NONE=y
+# CONFIG_DEFAULT_ENVIRONMENT is not set
+# CONFIG_SPI is not set
+CONFIG_MTD=y
+# CONFIG_MTD_WRITE is not set
+# CONFIG_MTD_OOB_DEVICE is not set
+CONFIG_NAND=y
+# CONFIG_NAND_ECC_HW is not set
+# CONFIG_NAND_ECC_HW_SYNDROME is not set
+# CONFIG_NAND_ECC_HW_NONE is not set
+CONFIG_NAND_ATMEL=y
+# CONFIG_FS_RAMFS is not set
--
1.7.10.4
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/7] at91: add test commamd to emulate bootrom boot
2012-12-29 10:08 ` [PATCH 1/7] at91: add test commamd to emulate bootrom boot Jean-Christophe PLAGNIOL-VILLARD
` (5 preceding siblings ...)
2012-12-29 10:08 ` [PATCH 7/7] at91: usb_a9263: " Jean-Christophe PLAGNIOL-VILLARD
@ 2013-01-02 10:10 ` Sascha Hauer
6 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2013-01-02 10:10 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
On Sat, Dec 29, 2012 at 11:08:11AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> ---
> arch/arm/mach-at91/Kconfig | 5 ++
> arch/arm/mach-at91/Makefile | 1 +
> arch/arm/mach-at91/boot_test_cmd.c | 97 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 103 insertions(+)
> create mode 100644 arch/arm/mach-at91/boot_test_cmd.c
>
> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> index fcba7fb..264b975 100644
> --- a/arch/arm/mach-at91/Kconfig
> +++ b/arch/arm/mach-at91/Kconfig
> @@ -483,4 +483,9 @@ config CMD_AT91MUX
> bool "at91mux dump command"
> default y
>
> +config CONFIG_CMD_AT91_BOOT_TEST
> + bool "at91_boot_test"
> + help
> + allow to upload a boot binary to sram and execute it
You should mention here that this is for debugging/testing the bootstrap
support.
> + while ((opt = getopt(argc, argv, "j:s:")) > 0) {
> + switch (opt) {
> + case 'j':
> + jump = simple_strtoul(optarg, NULL, 0);
> + break;
> + case 's':
> + sram = optarg;
> + break;
default:
return COMMAND_ERROR_USAGE;
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/7] at91: sam926x: switch lowlevel param to c code
2012-12-29 10:08 ` [PATCH 3/7] at91: sam926x: switch lowlevel param to c code Jean-Christophe PLAGNIOL-VILLARD
@ 2013-01-02 10:18 ` Sascha Hauer
0 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2013-01-02 10:18 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
On Sat, Dec 29, 2012 at 11:08:13AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> Instead of hardcode define use a struct that the board fill
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> ---
> arch/arm/boards/at91sam9263ek/Makefile | 5 +
> arch/arm/boards/at91sam9263ek/config.h | 87 -------------
> arch/arm/boards/at91sam9263ek/lowlevel_init.c | 104 +++++++++++++++
> arch/arm/boards/mmccpu/Makefile | 5 +
> arch/arm/boards/mmccpu/config.h | 118 -----------------
> arch/arm/boards/mmccpu/lowlevel_init.c | 135 ++++++++++++++++++++
> arch/arm/boards/pm9261/Makefile | 5 +
> arch/arm/boards/pm9261/config.h | 87 -------------
> arch/arm/boards/pm9261/lowlevel_init.c | 102 +++++++++++++++
> arch/arm/boards/pm9263/Makefile | 5 +
> arch/arm/boards/pm9263/config.h | 103 ---------------
> arch/arm/mach-at91/at91sam926x_lowlevel_init.c | 64 ++++++----
> .../mach-at91/include/mach/at91_lowlevel_init.h | 33 +++++
> 13 files changed, 435 insertions(+), 418 deletions(-)
> create mode 100644 arch/arm/boards/at91sam9263ek/lowlevel_init.c
> create mode 100644 arch/arm/boards/mmccpu/lowlevel_init.c
> create mode 100644 arch/arm/boards/pm9261/lowlevel_init.c
> create mode 100644 arch/arm/mach-at91/include/mach/at91_lowlevel_init.h
>
> diff --git a/arch/arm/boards/at91sam9263ek/Makefile b/arch/arm/boards/at91sam9263ek/Makefile
> index eb072c0..aecbc5a 100644
> --- a/arch/arm/boards/at91sam9263ek/Makefile
> +++ b/arch/arm/boards/at91sam9263ek/Makefile
> @@ -1 +1,6 @@
> obj-y += init.o
> +
> +lowlevel_init-y = lowlevel_init.o
> +obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
> +
> +pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
> diff --git a/arch/arm/boards/at91sam9263ek/config.h b/arch/arm/boards/at91sam9263ek/config.h
> index 14eb4fe..cc12040 100644
> --- a/arch/arm/boards/at91sam9263ek/config.h
> +++ b/arch/arm/boards/at91sam9263ek/config.h
> @@ -3,91 +3,4 @@
>
> #define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
>
> -#define MASTER_PLL_MUL 171
> -#define MASTER_PLL_DIV 14
> -
> -/* clocks */
> -#define CONFIG_SYS_MOR_VAL \
> - (AT91_PMC_MOSCEN | \
> - (255 << 8)) /* Main Oscillator Start-up Time */
> -#define CONFIG_SYS_PLLAR_VAL \
> - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
> - AT91_PMC_OUT | \
> - AT91_PMC_PLLCOUNT | /* PLL Counter */ \
> - (2 << 28) | /* PLL Clock Frequency Range */ \
> - ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
> -
> -/* PCK/2 = MCK Master Clock from PLLA */
> -#define CONFIG_SYS_MCKR1_VAL \
> - (AT91_PMC_CSS_SLOW | \
> - AT91_PMC_PRES_1 | \
> - AT91SAM9_PMC_MDIV_2 | \
> - AT91_PMC_PDIV_1)
> -/* PCK/2 = MCK Master Clock from PLLA */
> -#define CONFIG_SYS_MCKR2_VAL \
> - (AT91_PMC_CSS_PLLA | \
> - AT91_PMC_PRES_1 | \
> - AT91SAM9_PMC_MDIV_2 | \
> - AT91_PMC_PDIV_1)
> -
> -/* define PDC[31:16] as DATA[31:16] */
> -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
> -/* no pull-up for D[31:16] */
> -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
> -/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
> -#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
> - (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
> - AT91_MATRIX_EBI0_CS1A_SDRAMC)
> -
> -/* SDRAM */
> -/* SDRAMC_TR - Refresh Timer register */
> -#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
> -/* SDRAMC_CR - Configuration register*/
> -#define CONFIG_SYS_SDRC_CR_VAL \
> - (AT91_SDRAMC_NC_9 | \
> - AT91_SDRAMC_NR_13 | \
> - AT91_SDRAMC_NB_4 | \
> - AT91_SDRAMC_CAS_3 | \
> - AT91_SDRAMC_DBW_32 | \
> - (1 << 8) | /* Write Recovery Delay */ \
> - (7 << 12) | /* Row Cycle Delay */ \
> - (2 << 16) | /* Row Precharge Delay */ \
> - (2 << 20) | /* Row to Column Delay */ \
> - (5 << 24) | /* Active to Precharge Delay */ \
> - (1 << 28)) /* Exit Self Refresh to Active Delay */
> -
> -/* Memory Device Register -> SDRAM */
> -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
> -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
> -
> -/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
> -#define CONFIG_SYS_SMC_CS 0
> -#define CONFIG_SYS_SMC_SETUP_VAL \
> - (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
> - AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
> -#define CONFIG_SYS_SMC_PULSE_VAL \
> - (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
> - AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
> -#define CONFIG_SYS_SMC_CYCLE_VAL \
> - (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
> -#define CONFIG_SYS_SMC_MODE_VAL \
> - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
> - AT91_SMC_DBW_16 | \
> - AT91_SMC_TDFMODE | \
> - AT91_SMC_TDF_(6))
> -
> -/* user reset enable */
> -#define CONFIG_SYS_RSTC_RMR_VAL \
> - (AT91_RSTC_KEY | \
> - AT91_RSTC_PROCRST | \
> - AT91_RSTC_RSTTYP_WAKEUP | \
> - AT91_RSTC_RSTTYP_WATCHDOG)
> -
> -/* Disable Watchdog */
> -#define CONFIG_SYS_WDTC_WDMR_VAL \
> - (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
> - AT91_WDT_WDV | \
> - AT91_WDT_WDDIS | \
> - AT91_WDT_WDD)
> -
> #endif /* __CONFIG_H */
> diff --git a/arch/arm/boards/at91sam9263ek/lowlevel_init.c b/arch/arm/boards/at91sam9263ek/lowlevel_init.c
> new file mode 100644
> index 0000000..2f8b312
> --- /dev/null
> +++ b/arch/arm/boards/at91sam9263ek/lowlevel_init.c
> @@ -0,0 +1,104 @@
> +/*
> + * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> + *
> + * Under GPLv2
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +#include <mach/hardware.h>
> +#include <mach/at91_rstc.h>
> +#include <mach/at91_wdt.h>
> +#include <mach/at91_pmc.h>
> +#include <mach/at91sam9_smc.h>
> +#include <mach/at91sam9_sdramc.h>
> +#include <mach/at91sam9_matrix.h>
> +#include <mach/at91_lowlevel_init.h>
> +
> +#define MASTER_PLL_MUL 171
> +#define MASTER_PLL_DIV 14
> +
> +void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
> +{
> + /* Disable Watchdog */
> + cfg->wdt_mr =
> + AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
> + AT91_WDT_WDV |
> + AT91_WDT_WDDIS |
> + AT91_WDT_WDD;
> +
> + /* define PDC[31:16] as DATA[31:16] */
> + cfg->ebi_pio_pdr = 0xFFFF0000;
> + /* no pull-up for D[31:16] */
> + cfg->ebi_pio_ppudr = 0xFFFF0000;
> + /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
> + cfg->ebi_csa =
> + AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
> + AT91_MATRIX_EBI0_CS1A_SDRAMC;
> +
> + cfg->smc_cs = 0;
> + cfg->smc_mode =
> + AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
> + AT91_SMC_DBW_16 |
> + AT91_SMC_TDFMODE |
> + AT91_SMC_TDF_(6);
> + cfg->smc_cycle =
> + AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
> + cfg->smc_pulse =
> + AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
> + AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
> + cfg->smc_setup =
> + AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
> + AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
> +
> + cfg->pmc_mor =
> + AT91_PMC_MOSCEN |
> + (255 << 8); /* Main Oscillator Start-up Time */
> + cfg->pmc_pllar =
> + AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
> + AT91_PMC_OUT |
> + AT91_PMC_PLLCOUNT | /* PLL Counter */
> + (2 << 28) | /* PLL Clock Frequency Range */
> + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
> + /* PCK/2 = MCK Master Clock from PLLA */
> + cfg->pmc_mckr1 =
> + AT91_PMC_CSS_SLOW |
> + AT91_PMC_PRES_1 |
> + AT91SAM9_PMC_MDIV_2 |
> + AT91_PMC_PDIV_1;
> + /* PCK/2 = MCK Master Clock from PLLA */
> + cfg->pmc_mckr2 =
> + AT91_PMC_CSS_PLLA |
> + AT91_PMC_PRES_1 |
> + AT91SAM9_PMC_MDIV_2 |
> + AT91_PMC_PDIV_1;
> +
> + /* SDRAM */
> + /* SDRAMC_TR - Refresh Timer register */
> + cfg->sdrc_tr1 = 0x13C;
> + /* SDRAMC_CR - Configuration register*/
> + cfg->sdrc_cr =
> + AT91_SDRAMC_NC_9 |
> + AT91_SDRAMC_NR_13 |
> + AT91_SDRAMC_NB_4 |
> + AT91_SDRAMC_CAS_3 |
> + AT91_SDRAMC_DBW_32 |
> + (1 << 8) | /* Write Recovery Delay */
> + (7 << 12) | /* Row Cycle Delay */
> + (2 << 16) | /* Row Precharge Delay */
> + (2 << 20) | /* Row to Column Delay */
> + (5 << 24) | /* Active to Precharge Delay */
> + (1 << 28); /* Exit Self Refresh to Active Delay */
> +
> + /* Memory Device Register -> SDRAM */
> + cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
> + /* SDRAM_TR */
> + cfg->sdrc_tr2 = 1200;
> +
> + /* user reset enable */
> + cfg->rstc_rmr =
> + AT91_RSTC_KEY |
> + AT91_RSTC_PROCRST |
> + AT91_RSTC_RSTTYP_WAKEUP |
> + AT91_RSTC_RSTTYP_WATCHDOG;
> +}
> diff --git a/arch/arm/boards/mmccpu/Makefile b/arch/arm/boards/mmccpu/Makefile
> index eb072c0..aecbc5a 100644
> --- a/arch/arm/boards/mmccpu/Makefile
> +++ b/arch/arm/boards/mmccpu/Makefile
> @@ -1 +1,6 @@
> obj-y += init.o
> +
> +lowlevel_init-y = lowlevel_init.o
> +obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
> +
> +pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
> diff --git a/arch/arm/boards/mmccpu/config.h b/arch/arm/boards/mmccpu/config.h
> index e6215dc..c896a93 100644
> --- a/arch/arm/boards/mmccpu/config.h
> +++ b/arch/arm/boards/mmccpu/config.h
> @@ -3,122 +3,4 @@
>
> #define AT91_MAIN_CLOCK 18432000
>
> -/* values */
> -#define MASTER_PLL_MUL 54
> -#define MASTER_PLL_DIV 4
> -
> -/* clocks */
> -#define CONFIG_SYS_MOR_VAL \
> - (AT91_PMC_MOSCEN | \
> - (255 << 8)) /* Main Oscillator Start-up Time */
> -#define CONFIG_SYS_PLLAR_VAL \
> - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
> - AT91_PMC_OUT | \
> - AT91_PMC_PLLCOUNT | /* PLL Counter */ \
> - (2 << 28) | /* PLL Clock Frequency Range */ \
> - ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
> -
> -/* PCK/2 = MCK Master Clock from PLLA */
> -#define CONFIG_SYS_MCKR1_VAL \
> - (AT91_PMC_CSS_SLOW | \
> - AT91_PMC_PRES_1 | \
> - AT91SAM9_PMC_MDIV_2 | \
> - AT91_PMC_PDIV_1)
> -/* PCK/2 = MCK Master Clock from PLLA */
> -#define CONFIG_SYS_MCKR2_VAL \
> - (AT91_PMC_CSS_PLLA | \
> - AT91_PMC_PRES_1 | \
> - AT91SAM9_PMC_MDIV_2 | \
> - AT91_PMC_PDIV_1)
> -
> -/* define PDC[31:16] as DATA[31:16] */
> -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
> -/* no pull-up for D[31:16] */
> -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
> -/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 1.8V memories */
> -#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
> - (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_1_8V | \
> - AT91_MATRIX_EBI0_CS1A_SDRAMC | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA)
> -
> -/* SDRAM */
> -/* SDRAMC_TR - Refresh Timer register */
> -#define CONFIG_SYS_SDRC_TR_VAL1 0x13c
> -/* SDRAMC_CR - Configuration register*/
> -#define CONFIG_SYS_SDRC_CR_VAL \
> - (AT91_SDRAMC_NC_9 | \
> - AT91_SDRAMC_NR_13 | \
> - AT91_SDRAMC_NB_4 | \
> - AT91_SDRAMC_CAS_3 | \
> - AT91_SDRAMC_DBW_32 | \
> - (2 << 8) | /* tWR - Write Recovery Delay */ \
> - (8 << 12) | /* tRC - Row Cycle Delay */ \
> - (2 << 16) | /* tRP - Row Precharge Delay */ \
> - (2 << 20) | /* tRCD - Row to Column Delay */ \
> - (5 << 24) | /* tRAS - Active to Precharge Delay */ \
> - (12 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
> -
> -/* Memory Device Register -> SDRAM */
> -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
> -#define CONFIG_SYS_SDRC_TR_VAL2 780 /* SDRAM_TR */
> -
> -/* setup CS0 (NOR Flash) - 16-bit */
> -#define CONFIG_SYS_SMC_CS 0
> -#if 1
> -#define CONFIG_SYS_SMC_SETUP_VAL \
> - (AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | \
> - AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0))
> -#define CONFIG_SYS_SMC_PULSE_VAL \
> - (AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | \
> - AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13))
> -#define CONFIG_SYS_SMC_CYCLE_VAL \
> - (AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16))
> -#define CONFIG_SYS_SMC_MODE_VAL \
> - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
> - AT91_SMC_DBW_16 | \
> - AT91_SMC_TDFMODE | \
> - AT91_SMC_TDF_(6))
> -#elif 0 /* slow setup */
> -#define CONFIG_SYS_SMC_SETUP_VAL \
> - (AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | \
> - AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0))
> -#define CONFIG_SYS_SMC_PULSE_VAL \
> - (AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | \
> - AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13))
> -#define CONFIG_SYS_SMC_CYCLE_VAL \
> - (AT91_SMC_NWECYCLE_(0xd00) | AT91_SMC_NRDCYCLE_(0xd00))
> -#define CONFIG_SYS_SMC_MODE_VAL \
> - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
> - AT91_SMC_DBW_16 | \
> - AT91_SMC_TDFMODE | \
> - AT91_SMC_TDF_(1))
> -#else /* RONETIX' original values */
> -#define CONFIG_SYS_SMC_SETUP_VAL \
> - (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
> - AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
> -#define CONFIG_SYS_SMC_PULSE_VAL \
> - (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
> - AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
> -#define CONFIG_SYS_SMC_CYCLE_VAL \
> - (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
> -#define CONFIG_SYS_SMC_MODE_VAL \
> - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
> - AT91_SMC_DBW_16 | \
> - AT91_SMC_TDFMODE | \
> - AT91_SMC_TDF_(6))
> -#endif
> -
> -/* user reset enable */
> -#define CONFIG_SYS_RSTC_RMR_VAL \
> - (AT91_RSTC_KEY | \
> - AT91_RSTC_PROCRST | \
> - AT91_RSTC_RSTTYP_WAKEUP | \
> - AT91_RSTC_RSTTYP_WATCHDOG)
> -
> -/* Disable Watchdog */
> -#define CONFIG_SYS_WDTC_WDMR_VAL \
> - (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
> - AT91_WDT_WDV | \
> - AT91_WDT_WDDIS | \
> - AT91_WDT_WDD)
> -
> #endif /* __CONFIG_H */
> diff --git a/arch/arm/boards/mmccpu/lowlevel_init.c b/arch/arm/boards/mmccpu/lowlevel_init.c
> new file mode 100644
> index 0000000..82500eb
> --- /dev/null
> +++ b/arch/arm/boards/mmccpu/lowlevel_init.c
> @@ -0,0 +1,135 @@
> +/*
> + * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> + *
> + * Under GPLv2
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +#include <mach/hardware.h>
> +#include <mach/at91_rstc.h>
> +#include <mach/at91_wdt.h>
> +#include <mach/at91_pmc.h>
> +#include <mach/at91sam9_smc.h>
> +#include <mach/at91sam9_sdramc.h>
> +#include <mach/at91sam9_matrix.h>
> +#include <mach/at91_lowlevel_init.h>
> +
> +#define MASTER_PLL_MUL 54
> +#define MASTER_PLL_DIV 4
> +
> +void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
> +{
> + /* Disable Watchdog */
> + cfg->wdt_mr =
> + AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
> + AT91_WDT_WDV |
> + AT91_WDT_WDDIS |
> + AT91_WDT_WDD;
> +
> + /* define PDC[31:16] as DATA[31:16] */
> + cfg->ebi_pio_pdr = 0xFFFF0000;
> + /* no pull-up for D[31:16] */
> + cfg->ebi_pio_ppudr = 0xFFFF0000;
> + /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
> + cfg->ebi_csa =
> + AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_1_8V |
> + AT91_MATRIX_EBI0_CS1A_SDRAMC |
> + AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA;
> +
> + cfg->smc_cs = 0;
> +#if 1
> + cfg->smc_mode =
> + AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
> + AT91_SMC_DBW_16 |
> + AT91_SMC_TDFMODE |
> + AT91_SMC_TDF_(6);
> + cfg->smc_cycle =
> + AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16);
> + cfg->smc_pulse =
> + AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) |
> + AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13);
> + cfg->smc_setup =
> + AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) |
> + AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0);
> +#elif 0
> + cfg->smc_mode =
> + AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
> + AT91_SMC_DBW_16 |
> + AT91_SMC_TDFMODE |
> + AT91_SMC_TDF_(1);
> + cfg->smc_cycle =
> + AT91_SMC_NWECYCLE_(0xd00) | AT91_SMC_NRDCYCLE_(0xd00);
> + cfg->smc_pulse =
> + AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) |
> + AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13);
> + cfg->smc_setup =
> + AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) |
> + AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0);
> +#else
> + cfg->smc_mode =
> + AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
> + AT91_SMC_DBW_16 |
> + AT91_SMC_TDFMODE |
> + AT91_SMC_TDF_(6);
> + cfg->smc_cycle =
> + AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
> + cfg->smc_pulse =
> + AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
> + AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
> + cfg->smc_setup =
> + AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
> + AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
> +#endif
Please keep the comments from the original code (slow, Ronetix
original), or (preferred), just drop the unused code.
> +
> + cfg->pmc_mor =
Trailing whitespace (some more in this patch)
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 6/7] at91: add bootstrap version
2012-12-29 10:08 ` [PATCH 6/7] at91: add bootstrap version Jean-Christophe PLAGNIOL-VILLARD
@ 2013-01-02 11:41 ` Jan Lübbe
2013-01-04 13:12 ` Sascha Hauer
0 siblings, 1 reply; 14+ messages in thread
From: Jan Lübbe @ 2013-01-02 11:41 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
On Sat, 2012-12-29 at 11:08 +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> diff --git a/arch/arm/mach-at91/bootstrap.c b/arch/arm/mach-at91/bootstrap.c
> new file mode 100644
> index 0000000..2ec16f1
> --- /dev/null
> +++ b/arch/arm/mach-at91/bootstrap.c
> @@ -0,0 +1,86 @@
> +/*
> + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
> + *
> + * Under GPLv2
> + */
> +
> +#include <common.h>
> +#include <bootstrap.h>
> +#include <mach/bootstrap.h>
> +#include <sizes.h>
> +#include <malloc.h>
> +
> +#if defined(CONFIG_MCI_ATMEL)
> +#define is_mmc() 1
> +#else
> +#define is_mmc() 0
> +#endif
> +
> +#ifdef CONFIG_NAND_ATMEL
> +#define is_nand() 1
> +#else
> +#define is_nand() 0
> +#endif
> +
> +#ifdef CONFIG_MTD_M25P80
> +#define is_m25p80() 1
> +#else
> +#define is_m25p80() 0
> +#endif
> +
> +#ifdef CONFIG_MTD_DATAFLASH
> +#define is_dataflash() 1
> +#else
> +#define is_dataflash() 0
> +#endif
> +
> +static void boot_seq(bool is_barebox)
> +{
> + char *name = is_barebox ? "barebox" : "unknown";
> + int (*func)(void) = NULL;
> +
> + if (is_m25p80()) {
> + func = bootstrap_board_read_m25p80();
> + printf("Boot %s from m25p80\n", name);
> + bootstrap_boot(func, is_barebox);
> + bootstrap_err("... failled\n");
> + free(func);
> + }
> + if (is_dataflash()) {
> + printf("Boot %s from dataflash\n", name);
> + func = bootstrap_board_read_dataflash();
> + bootstrap_boot(func, is_barebox);
> + bootstrap_err("... failled\n");
> + free(func);
> + }
> + if (is_nand()) {
> + printf("Boot %s from nand\n", name);
> + func = bootstrap_read_devfs("nand0", true, SZ_128K, SZ_256K, SZ_1M);
> + bootstrap_boot(func, is_barebox);
> + bootstrap_err("... failled\n");
> + free(func);
> + }
> +}
Why can't you use IS_ENABLED(CONFIG_xxx) here?
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 6/7] at91: add bootstrap version
2013-01-02 11:41 ` Jan Lübbe
@ 2013-01-04 13:12 ` Sascha Hauer
0 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2013-01-04 13:12 UTC (permalink / raw)
To: Jan Lübbe; +Cc: barebox
On Wed, Jan 02, 2013 at 12:41:31PM +0100, Jan Lübbe wrote:
> On Sat, 2012-12-29 at 11:08 +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > diff --git a/arch/arm/mach-at91/bootstrap.c b/arch/arm/mach-at91/bootstrap.c
> > new file mode 100644
> > index 0000000..2ec16f1
> > --- /dev/null
> > +++ b/arch/arm/mach-at91/bootstrap.c
> > @@ -0,0 +1,86 @@
> > +/*
> > + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
> > + *
> > + * Under GPLv2
> > + */
> > +
> > +#include <common.h>
> > +#include <bootstrap.h>
> > +#include <mach/bootstrap.h>
> > +#include <sizes.h>
> > +#include <malloc.h>
> > +
> > +#if defined(CONFIG_MCI_ATMEL)
> > +#define is_mmc() 1
> > +#else
> > +#define is_mmc() 0
> > +#endif
> > +
> > +#ifdef CONFIG_NAND_ATMEL
> > +#define is_nand() 1
> > +#else
> > +#define is_nand() 0
> > +#endif
> > +
> > +#ifdef CONFIG_MTD_M25P80
> > +#define is_m25p80() 1
> > +#else
> > +#define is_m25p80() 0
> > +#endif
> > +
> > +#ifdef CONFIG_MTD_DATAFLASH
> > +#define is_dataflash() 1
> > +#else
> > +#define is_dataflash() 0
> > +#endif
> > +
> > +static void boot_seq(bool is_barebox)
> > +{
> > + char *name = is_barebox ? "barebox" : "unknown";
> > + int (*func)(void) = NULL;
> > +
> > + if (is_m25p80()) {
> > + func = bootstrap_board_read_m25p80();
> > + printf("Boot %s from m25p80\n", name);
> > + bootstrap_boot(func, is_barebox);
> > + bootstrap_err("... failled\n");
btw:
s/failled/failed/
> > + free(func);
> > + }
> > + if (is_dataflash()) {
> > + printf("Boot %s from dataflash\n", name);
> > + func = bootstrap_board_read_dataflash();
> > + bootstrap_boot(func, is_barebox);
> > + bootstrap_err("... failled\n");
ditto
> > + free(func);
> > + }
> > + if (is_nand()) {
> > + printf("Boot %s from nand\n", name);
> > + func = bootstrap_read_devfs("nand0", true, SZ_128K, SZ_256K, SZ_1M);
> > + bootstrap_boot(func, is_barebox);
> > + bootstrap_err("... failled\n");
ditto
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 3/7] at91: sam926x: switch lowlevel param to c code
2013-01-19 11:26 ` [PATCH 1/7] at91: add test commamd to emulate bootrom boot Jean-Christophe PLAGNIOL-VILLARD
@ 2013-01-19 11:26 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-01-19 11:26 UTC (permalink / raw)
To: barebox
Instead of hardcode define use a struct that the board fill
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/boards/at91sam9263ek/Makefile | 5 +
arch/arm/boards/at91sam9263ek/config.h | 99 +-------------
arch/arm/boards/at91sam9263ek/lowlevel_init.c | 104 +++++++++++++++
arch/arm/boards/mmccpu/Makefile | 5 +
arch/arm/boards/mmccpu/config.h | 130 +------------------
arch/arm/boards/mmccpu/lowlevel_init.c | 135 ++++++++++++++++++++
arch/arm/boards/pm9261/Makefile | 5 +
arch/arm/boards/pm9261/config.h | 99 +-------------
arch/arm/boards/pm9261/lowlevel_init.c | 102 +++++++++++++++
arch/arm/boards/pm9263/Makefile | 5 +
arch/arm/boards/pm9263/config.h | 115 +----------------
arch/arm/boards/pm9263/lowlevel_init.c | 121 ++++++++++++++++++
arch/arm/mach-at91/at91sam926x_lowlevel_init.c | 64 ++++++----
.../mach-at91/include/mach/at91_lowlevel_init.h | 33 +++++
14 files changed, 580 insertions(+), 442 deletions(-)
rewrite arch/arm/boards/at91sam9263ek/config.h (95%)
create mode 100644 arch/arm/boards/at91sam9263ek/lowlevel_init.c
rewrite arch/arm/boards/mmccpu/config.h (97%)
create mode 100644 arch/arm/boards/mmccpu/lowlevel_init.c
rewrite arch/arm/boards/pm9261/config.h (95%)
create mode 100644 arch/arm/boards/pm9261/lowlevel_init.c
rewrite arch/arm/boards/pm9263/config.h (97%)
create mode 100644 arch/arm/boards/pm9263/lowlevel_init.c
create mode 100644 arch/arm/mach-at91/include/mach/at91_lowlevel_init.h
diff --git a/arch/arm/boards/at91sam9263ek/Makefile b/arch/arm/boards/at91sam9263ek/Makefile
index eb072c0..aecbc5a 100644
--- a/arch/arm/boards/at91sam9263ek/Makefile
+++ b/arch/arm/boards/at91sam9263ek/Makefile
@@ -1 +1,6 @@
obj-y += init.o
+
+lowlevel_init-y = lowlevel_init.o
+obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
+
+pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
diff --git a/arch/arm/boards/at91sam9263ek/config.h b/arch/arm/boards/at91sam9263ek/config.h
dissimilarity index 95%
index 14eb4fe..cc12040 100644
--- a/arch/arm/boards/at91sam9263ek/config.h
+++ b/arch/arm/boards/at91sam9263ek/config.h
@@ -1,93 +1,6 @@
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
-
-#define MASTER_PLL_MUL 171
-#define MASTER_PLL_DIV 14
-
-/* clocks */
-#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOSCEN | \
- (255 << 8)) /* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- AT91_PMC_OUT | \
- AT91_PMC_PLLCOUNT | /* PLL Counter */ \
- (2 << 28) | /* PLL Clock Frequency Range */ \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
-
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-
-/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
-/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
-/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
- (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
- AT91_MATRIX_EBI0_CS1A_SDRAMC)
-
-/* SDRAM */
-/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
-/* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_3 | \
- AT91_SDRAMC_DBW_32 | \
- (1 << 8) | /* Write Recovery Delay */ \
- (7 << 12) | /* Row Cycle Delay */ \
- (2 << 16) | /* Row Precharge Delay */ \
- (2 << 20) | /* Row to Column Delay */ \
- (5 << 24) | /* Active to Precharge Delay */ \
- (1 << 28)) /* Exit Self Refresh to Active Delay */
-
-/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-
-/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC_CS 0
-#define CONFIG_SYS_SMC_SETUP_VAL \
- (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
- AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
-#define CONFIG_SYS_SMC_PULSE_VAL \
- (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
- AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
-#define CONFIG_SYS_SMC_CYCLE_VAL \
- (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
-#define CONFIG_SYS_SMC_MODE_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(6))
-
-/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
- (AT91_RSTC_KEY | \
- AT91_RSTC_PROCRST | \
- AT91_RSTC_RSTTYP_WAKEUP | \
- AT91_RSTC_RSTTYP_WATCHDOG)
-
-/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
- AT91_WDT_WDV | \
- AT91_WDT_WDDIS | \
- AT91_WDT_WDD)
-
-#endif /* __CONFIG_H */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
+
+#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/at91sam9263ek/lowlevel_init.c b/arch/arm/boards/at91sam9263ek/lowlevel_init.c
new file mode 100644
index 0000000..2f8b312
--- /dev/null
+++ b/arch/arm/boards/at91sam9263ek/lowlevel_init.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/hardware.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_wdt.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9_matrix.h>
+#include <mach/at91_lowlevel_init.h>
+
+#define MASTER_PLL_MUL 171
+#define MASTER_PLL_DIV 14
+
+void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
+{
+ /* Disable Watchdog */
+ cfg->wdt_mr =
+ AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
+ AT91_WDT_WDV |
+ AT91_WDT_WDDIS |
+ AT91_WDT_WDD;
+
+ /* define PDC[31:16] as DATA[31:16] */
+ cfg->ebi_pio_pdr = 0xFFFF0000;
+ /* no pull-up for D[31:16] */
+ cfg->ebi_pio_ppudr = 0xFFFF0000;
+ /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+ cfg->ebi_csa =
+ AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
+ AT91_MATRIX_EBI0_CS1A_SDRAMC;
+
+ cfg->smc_cs = 0;
+ cfg->smc_mode =
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_DBW_16 |
+ AT91_SMC_TDFMODE |
+ AT91_SMC_TDF_(6);
+ cfg->smc_cycle =
+ AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
+ cfg->smc_pulse =
+ AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
+ AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
+ cfg->smc_setup =
+ AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
+ AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
+
+ cfg->pmc_mor =
+ AT91_PMC_MOSCEN |
+ (255 << 8); /* Main Oscillator Start-up Time */
+ cfg->pmc_pllar =
+ AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
+ AT91_PMC_OUT |
+ AT91_PMC_PLLCOUNT | /* PLL Counter */
+ (2 << 28) | /* PLL Clock Frequency Range */
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr1 =
+ AT91_PMC_CSS_SLOW |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr2 =
+ AT91_PMC_CSS_PLLA |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+
+ /* SDRAM */
+ /* SDRAMC_TR - Refresh Timer register */
+ cfg->sdrc_tr1 = 0x13C;
+ /* SDRAMC_CR - Configuration register*/
+ cfg->sdrc_cr =
+ AT91_SDRAMC_NC_9 |
+ AT91_SDRAMC_NR_13 |
+ AT91_SDRAMC_NB_4 |
+ AT91_SDRAMC_CAS_3 |
+ AT91_SDRAMC_DBW_32 |
+ (1 << 8) | /* Write Recovery Delay */
+ (7 << 12) | /* Row Cycle Delay */
+ (2 << 16) | /* Row Precharge Delay */
+ (2 << 20) | /* Row to Column Delay */
+ (5 << 24) | /* Active to Precharge Delay */
+ (1 << 28); /* Exit Self Refresh to Active Delay */
+
+ /* Memory Device Register -> SDRAM */
+ cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
+ /* SDRAM_TR */
+ cfg->sdrc_tr2 = 1200;
+
+ /* user reset enable */
+ cfg->rstc_rmr =
+ AT91_RSTC_KEY |
+ AT91_RSTC_PROCRST |
+ AT91_RSTC_RSTTYP_WAKEUP |
+ AT91_RSTC_RSTTYP_WATCHDOG;
+}
diff --git a/arch/arm/boards/mmccpu/Makefile b/arch/arm/boards/mmccpu/Makefile
index eb072c0..aecbc5a 100644
--- a/arch/arm/boards/mmccpu/Makefile
+++ b/arch/arm/boards/mmccpu/Makefile
@@ -1 +1,6 @@
obj-y += init.o
+
+lowlevel_init-y = lowlevel_init.o
+obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
+
+pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
diff --git a/arch/arm/boards/mmccpu/config.h b/arch/arm/boards/mmccpu/config.h
dissimilarity index 97%
index e6215dc..c896a93 100644
--- a/arch/arm/boards/mmccpu/config.h
+++ b/arch/arm/boards/mmccpu/config.h
@@ -1,124 +1,6 @@
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define AT91_MAIN_CLOCK 18432000
-
-/* values */
-#define MASTER_PLL_MUL 54
-#define MASTER_PLL_DIV 4
-
-/* clocks */
-#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOSCEN | \
- (255 << 8)) /* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- AT91_PMC_OUT | \
- AT91_PMC_PLLCOUNT | /* PLL Counter */ \
- (2 << 28) | /* PLL Clock Frequency Range */ \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
-
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-
-/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
-/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
-/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 1.8V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
- (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_1_8V | \
- AT91_MATRIX_EBI0_CS1A_SDRAMC | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA)
-
-/* SDRAM */
-/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x13c
-/* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_3 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* tWR - Write Recovery Delay */ \
- (8 << 12) | /* tRC - Row Cycle Delay */ \
- (2 << 16) | /* tRP - Row Precharge Delay */ \
- (2 << 20) | /* tRCD - Row to Column Delay */ \
- (5 << 24) | /* tRAS - Active to Precharge Delay */ \
- (12 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
-
-/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_TR_VAL2 780 /* SDRAM_TR */
-
-/* setup CS0 (NOR Flash) - 16-bit */
-#define CONFIG_SYS_SMC_CS 0
-#if 1
-#define CONFIG_SYS_SMC_SETUP_VAL \
- (AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | \
- AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0))
-#define CONFIG_SYS_SMC_PULSE_VAL \
- (AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | \
- AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13))
-#define CONFIG_SYS_SMC_CYCLE_VAL \
- (AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16))
-#define CONFIG_SYS_SMC_MODE_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(6))
-#elif 0 /* slow setup */
-#define CONFIG_SYS_SMC_SETUP_VAL \
- (AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | \
- AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0))
-#define CONFIG_SYS_SMC_PULSE_VAL \
- (AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | \
- AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13))
-#define CONFIG_SYS_SMC_CYCLE_VAL \
- (AT91_SMC_NWECYCLE_(0xd00) | AT91_SMC_NRDCYCLE_(0xd00))
-#define CONFIG_SYS_SMC_MODE_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(1))
-#else /* RONETIX' original values */
-#define CONFIG_SYS_SMC_SETUP_VAL \
- (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
- AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
-#define CONFIG_SYS_SMC_PULSE_VAL \
- (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
- AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
-#define CONFIG_SYS_SMC_CYCLE_VAL \
- (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
-#define CONFIG_SYS_SMC_MODE_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(6))
-#endif
-
-/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
- (AT91_RSTC_KEY | \
- AT91_RSTC_PROCRST | \
- AT91_RSTC_RSTTYP_WAKEUP | \
- AT91_RSTC_RSTTYP_WATCHDOG)
-
-/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
- AT91_WDT_WDV | \
- AT91_WDT_WDDIS | \
- AT91_WDT_WDD)
-
-#endif /* __CONFIG_H */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define AT91_MAIN_CLOCK 18432000
+
+#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/mmccpu/lowlevel_init.c b/arch/arm/boards/mmccpu/lowlevel_init.c
new file mode 100644
index 0000000..68c609f
--- /dev/null
+++ b/arch/arm/boards/mmccpu/lowlevel_init.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/hardware.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_wdt.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9_matrix.h>
+#include <mach/at91_lowlevel_init.h>
+
+#define MASTER_PLL_MUL 54
+#define MASTER_PLL_DIV 4
+
+void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
+{
+ /* Disable Watchdog */
+ cfg->wdt_mr =
+ AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
+ AT91_WDT_WDV |
+ AT91_WDT_WDDIS |
+ AT91_WDT_WDD;
+
+ /* define PDC[31:16] as DATA[31:16] */
+ cfg->ebi_pio_pdr = 0xFFFF0000;
+ /* no pull-up for D[31:16] */
+ cfg->ebi_pio_ppudr = 0xFFFF0000;
+ /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+ cfg->ebi_csa =
+ AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_1_8V |
+ AT91_MATRIX_EBI0_CS1A_SDRAMC |
+ AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA;
+
+ cfg->smc_cs = 0;
+#if 1
+ cfg->smc_mode =
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_DBW_16 |
+ AT91_SMC_TDFMODE |
+ AT91_SMC_TDF_(6);
+ cfg->smc_cycle =
+ AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16);
+ cfg->smc_pulse =
+ AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) |
+ AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13);
+ cfg->smc_setup =
+ AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) |
+ AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0);
+#elif 0 /* slow setup */
+ cfg->smc_mode =
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_DBW_16 |
+ AT91_SMC_TDFMODE |
+ AT91_SMC_TDF_(1);
+ cfg->smc_cycle =
+ AT91_SMC_NWECYCLE_(0xd00) | AT91_SMC_NRDCYCLE_(0xd00);
+ cfg->smc_pulse =
+ AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) |
+ AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13);
+ cfg->smc_setup =
+ AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) |
+ AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0);
+#else /* RONETIX' original values */
+ cfg->smc_mode =
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_DBW_16 |
+ AT91_SMC_TDFMODE |
+ AT91_SMC_TDF_(6);
+ cfg->smc_cycle =
+ AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
+ cfg->smc_pulse =
+ AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
+ AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
+ cfg->smc_setup =
+ AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
+ AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
+#endif
+
+ cfg->pmc_mor =
+ AT91_PMC_MSCEN |
+ (255 << 8); /* Main Oscillator Start-up Time */
+ cfg->pmc_pllar =
+ AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
+ AT91_PMC_OUT |
+ AT91_PMC_PLLCOUNT | /* PLL Counter */
+ (2 << 28) | /* PLL Clock Frequency Range */
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr1 =
+ AT91_PMC_CSS_SLOW |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr2 =
+ AT91_PMC_CSS_PLLA |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+
+ /* SDRAM */
+ /* SDRAMC_TR - Refresh Timer register */
+ cfg->sdrc_tr1 = 0x13C;
+ /* SDRAMC_CR - Configuration register*/
+ cfg->sdrc_cr =
+ AT91_SDRAMC_NC_9 |
+ AT91_SDRAMC_NR_13 |
+ AT91_SDRAMC_NB_4 |
+ AT91_SDRAMC_CAS_3 |
+ AT91_SDRAMC_DBW_32 |
+ (2 << 8) | /* tWR - Write Recovery Delay */
+ (8 << 12) | /* tRC - Row Cycle Delay */
+ (2 << 16) | /* tRP - Row Precharge Delay */
+ (2 << 20) | /* tRCD - Row to Column Delay */
+ (5 << 24) | /* tRAS - Active to Precharge Delay */
+ (12 << 28); /* tXSR - Exit Self Refresh to Active Delay */
+
+ /* Memory Device Register -> SDRAM */
+ cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
+ /* SDRAM_TR */
+ cfg->sdrc_tr2 = 780;
+
+ /* user reset enable */
+ cfg->rstc_rmr =
+ AT91_RSTC_KEY |
+ AT91_RSTC_PROCRST |
+ AT91_RSTC_RSTTYP_WAKEUP |
+ AT91_RSTC_RSTTYP_WATCHDOG;
+}
diff --git a/arch/arm/boards/pm9261/Makefile b/arch/arm/boards/pm9261/Makefile
index eb072c0..aecbc5a 100644
--- a/arch/arm/boards/pm9261/Makefile
+++ b/arch/arm/boards/pm9261/Makefile
@@ -1 +1,6 @@
obj-y += init.o
+
+lowlevel_init-y = lowlevel_init.o
+obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
+
+pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
diff --git a/arch/arm/boards/pm9261/config.h b/arch/arm/boards/pm9261/config.h
dissimilarity index 95%
index 4602aa7..006820c 100644
--- a/arch/arm/boards/pm9261/config.h
+++ b/arch/arm/boards/pm9261/config.h
@@ -1,93 +1,6 @@
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
-
-#define MASTER_PLL_DIV 15
-#define MASTER_PLL_MUL 162
-#define MAIN_PLL_DIV 2
-
-/* clocks */
-#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOSCEN | \
- (255 << 8)) /* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- AT91_PMC_OUT | \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
-
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-
-/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
-/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
-
-/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
-#define CONFIG_SYS_MATRIX_EBICSA_VAL \
- (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC)
-
-/* SDRAM */
-/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
-/* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_3 | \
- AT91_SDRAMC_DBW_32 | \
- (1 << 8) | /* Write Recovery Delay */ \
- (7 << 12) | /* Row Cycle Delay */ \
- (3 << 16) | /* Row Precharge Delay */ \
- (2 << 20) | /* Row to Column Delay */ \
- (5 << 24) | /* Active to Precharge Delay */ \
- (1 << 28)) /* Exit Self Refresh to Active Delay */
-
-/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-
-/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC_CS 0
-#define CONFIG_SYS_SMC_SETUP_VAL \
- (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
- AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
-#define CONFIG_SYS_SMC_PULSE_VAL \
- (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
- AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
-#define CONFIG_SYS_SMC_CYCLE_VAL \
- (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
-#define CONFIG_SYS_SMC_MODE_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(6))
-
-/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
- (AT91_RSTC_KEY | \
- AT91_RSTC_PROCRST | \
- AT91_RSTC_RSTTYP_WAKEUP | \
- AT91_RSTC_RSTTYP_WATCHDOG)
-
-/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
- AT91_WDT_WDV | \
- AT91_WDT_WDDIS | \
- AT91_WDT_WDD)
-
-#endif /* __CONFIG_H */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
+
+#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/pm9261/lowlevel_init.c b/arch/arm/boards/pm9261/lowlevel_init.c
new file mode 100644
index 0000000..91a64b4
--- /dev/null
+++ b/arch/arm/boards/pm9261/lowlevel_init.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/hardware.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_wdt.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9_matrix.h>
+#include <mach/at91_lowlevel_init.h>
+
+#define MASTER_PLL_DIV 15
+#define MASTER_PLL_MUL 162
+#define MAIN_PLL_DIV 2
+
+void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
+{
+ /* Disable Watchdog */
+ cfg->wdt_mr =
+ AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
+ AT91_WDT_WDV |
+ AT91_WDT_WDDIS |
+ AT91_WDT_WDD;
+
+ /* define PDC[31:16] as DATA[31:16] */
+ cfg->ebi_pio_pdr = 0xFFFF0000;
+ /* no pull-up for D[31:16] */
+ cfg->ebi_pio_ppudr = 0xFFFF0000;
+ /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+ cfg->ebi_csa =
+ AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC;
+
+ cfg->smc_cs = 0;
+ cfg->smc_mode =
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_DBW_16 |
+ AT91_SMC_TDFMODE |
+ AT91_SMC_TDF_(6);
+ cfg->smc_cycle =
+ AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
+ cfg->smc_pulse =
+ AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
+ AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
+ cfg->smc_setup =
+ AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
+ AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
+
+ cfg->pmc_mor =
+ AT91_PMC_MOSCEN |
+ (255 << 8); /* Main Oscillator Start-up Time */
+ cfg->pmc_pllar =
+ AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
+ AT91_PMC_OUT |
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr1 =
+ AT91_PMC_CSS_SLOW |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr2 =
+ AT91_PMC_CSS_PLLA |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+
+ /* SDRAM */
+ /* SDRAMC_TR - Refresh Timer register */
+ cfg->sdrc_tr1 = 0x13C;
+ /* SDRAMC_CR - Configuration register*/
+ cfg->sdrc_cr =
+ AT91_SDRAMC_NC_9 |
+ AT91_SDRAMC_NR_13 |
+ AT91_SDRAMC_NB_4 |
+ AT91_SDRAMC_CAS_3 |
+ AT91_SDRAMC_DBW_32 |
+ (1 << 8) | /* Write Recovery Delay */
+ (7 << 12) | /* Row Cycle Delay */
+ (3 << 16) | /* Row Precharge Delay */
+ (2 << 20) | /* Row to Column Delay */
+ (5 << 24) | /* Active to Precharge Delay */
+ (1 << 28); /* Exit Self Refresh to Active Delay */
+
+ /* Memory Device Register -> SDRAM */
+ cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
+ /* SDRAM_TR */
+ cfg->sdrc_tr2 = 1200;
+
+ /* user reset enable */
+ cfg->rstc_rmr =
+ AT91_RSTC_KEY |
+ AT91_RSTC_PROCRST |
+ AT91_RSTC_RSTTYP_WAKEUP |
+ AT91_RSTC_RSTTYP_WATCHDOG;
+}
diff --git a/arch/arm/boards/pm9263/Makefile b/arch/arm/boards/pm9263/Makefile
index eb072c0..aecbc5a 100644
--- a/arch/arm/boards/pm9263/Makefile
+++ b/arch/arm/boards/pm9263/Makefile
@@ -1 +1,6 @@
obj-y += init.o
+
+lowlevel_init-y = lowlevel_init.o
+obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
+
+pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
diff --git a/arch/arm/boards/pm9263/config.h b/arch/arm/boards/pm9263/config.h
dissimilarity index 97%
index 322c1f3..9066613 100644
--- a/arch/arm/boards/pm9263/config.h
+++ b/arch/arm/boards/pm9263/config.h
@@ -1,109 +1,6 @@
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define AT91_MAIN_CLOCK 18432000
-
-#define MASTER_PLL_DIV 6
-#define MASTER_PLL_MUL 65
-#define MAIN_PLL_DIV 2 /* 2 or 4 */
-
-/* clocks */
-#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOSCEN | \
- (255 << 8)) /* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- AT91_PMC_OUT | \
- AT91_PMC_PLLCOUNT | /* PLL Counter */ \
- (2 << 28) | /* PLL Clock Frequency Range */ \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
-
-#if (MAIN_PLL_DIV == 2)
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-#else
-/* PCK/4 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91RM9200_PMC_MDIV_3 | \
- AT91_PMC_PDIV_1)
-/* PCK/4 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91RM9200_PMC_MDIV_3 | \
- AT91_PMC_PDIV_1)
-#endif
-/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
-/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
-/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
- (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
- AT91_MATRIX_EBI0_CS1A_SDRAMC)
-
-/* SDRAM */
-/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
-/* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_2 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* tWR - Write Recovery Delay */ \
- (7 << 12) | /* tRC - Row Cycle Delay */ \
- (2 << 16) | /* tRP - Row Precharge Delay */ \
- (2 << 20) | /* tRCD - Row to Column Delay */ \
- (5 << 24) | /* tRAS - Active to Precharge Delay */ \
- (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
-
-/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-
-/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC_CS 0
-#define CONFIG_SYS_SMC_SETUP_VAL \
- (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
- AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
-#define CONFIG_SYS_SMC_PULSE_VAL \
- (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
- AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
-#define CONFIG_SYS_SMC_CYCLE_VAL \
- (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
-#define CONFIG_SYS_SMC_MODE_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(6))
-
-/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
- (AT91_RSTC_KEY | \
- AT91_RSTC_PROCRST | \
- AT91_RSTC_RSTTYP_WAKEUP | \
- AT91_RSTC_RSTTYP_WATCHDOG)
-
-/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
- AT91_WDT_WDV | \
- AT91_WDT_WDDIS | \
- AT91_WDT_WDD)
-
-
-#endif /* __CONFIG_H */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define AT91_MAIN_CLOCK 18432000
+
+#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/pm9263/lowlevel_init.c b/arch/arm/boards/pm9263/lowlevel_init.c
new file mode 100644
index 0000000..6336d51
--- /dev/null
+++ b/arch/arm/boards/pm9263/lowlevel_init.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/hardware.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_wdt.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9_matrix.h>
+#include <mach/at91_lowlevel_init.h>
+
+#define MASTER_PLL_DIV 6
+#define MASTER_PLL_MUL 65
+#define MAIN_PLL_DIV 2 /* 2 or 4 */
+
+void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
+{
+ /* Disable Watchdog */
+ cfg->wdt_mr =
+ AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
+ AT91_WDT_WDV |
+ AT91_WDT_WDDIS |
+ AT91_WDT_WDD;
+
+ /* define PDC[31:16] as DATA[31:16] */
+ cfg->ebi_pio_pdr = 0xFFFF0000;
+ /* no pull-up for D[31:16] */
+ cfg->ebi_pio_ppudr = 0xFFFF0000;
+ /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+ cfg->ebi_csa =
+ AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
+ AT91_MATRIX_EBI0_CS1A_SDRAMC;
+
+ cfg->smc_cs = 0;
+ cfg->smc_mode =
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_DBW_16 |
+ AT91_SMC_TDFMODE |
+ AT91_SMC_TDF_(6);
+ cfg->smc_cycle =
+ AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
+ cfg->smc_pulse =
+ AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
+ AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
+ cfg->smc_setup =
+ AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
+ AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
+
+ cfg->pmc_mor =
+ AT91_PMC_MOSCEN |
+ (255 << 8); /* Main Oscillator Start-up Time */
+ cfg->pmc_pllar =
+ AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
+ AT91_PMC_OUT |
+ AT91_PMC_PLLCOUNT | /* PLL Counter */
+ (2 << 28) | /* PLL Clock Frequency Range */
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
+
+ if (MAIN_PLL_DIV == 2) {
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr1 =
+ AT91_PMC_CSS_SLOW |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr2 =
+ AT91_PMC_CSS_PLLA |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+ } else {
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr1 =
+ AT91_PMC_CSS_SLOW |
+ AT91_PMC_PRES_1 |
+ AT91RM9200_PMC_MDIV_3 |
+ AT91_PMC_PDIV_1;
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr2 =
+ AT91_PMC_CSS_PLLA |
+ AT91_PMC_PRES_1 |
+ AT91RM9200_PMC_MDIV_3 |
+ AT91_PMC_PDIV_1;
+ }
+
+ /* SDRAM */
+ /* SDRAMC_TR - Refresh Timer register */
+ cfg->sdrc_tr1 = 0x3AA;
+ /* SDRAMC_CR - Configuration register*/
+ cfg->sdrc_cr =
+ AT91_SDRAMC_NC_9 |
+ AT91_SDRAMC_NR_13 |
+ AT91_SDRAMC_NB_4 |
+ AT91_SDRAMC_CAS_2 |
+ AT91_SDRAMC_DBW_32 |
+ (2 << 8) | /* tWR - Write Recovery Delay */
+ (7 << 12) | /* tRC - Row Cycle Delay */
+ (2 << 16) | /* tRP - Row Precharge Delay */
+ (2 << 20) | /* tRCD - Row to Column Delay */
+ (5 << 24) | /* tRAS - Active to Precharge Delay */
+ (8 << 28); /* tXSR - Exit Self Refresh to Active Delay */
+
+ /* Memory Device Register -> SDRAM */
+ cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
+ /* SDRAM_TR */
+ cfg->sdrc_tr2 = 1200;
+
+ /* user reset enable */
+ cfg->rstc_rmr =
+ AT91_RSTC_KEY |
+ AT91_RSTC_PROCRST |
+ AT91_RSTC_RSTTYP_WAKEUP |
+ AT91_RSTC_RSTTYP_WATCHDOG;
+}
diff --git a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
index 4dec275..e7145b4 100644
--- a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
@@ -19,8 +19,10 @@
#include <mach/at91sam9_matrix.h>
#include <mach/at91sam9_sdramc.h>
#include <mach/at91sam9_smc.h>
+#include <mach/at91_lowlevel_init.h>
#include <mach/io.h>
#include <init.h>
+#include <sizes.h>
static void inline access_sdram(void)
{
@@ -44,40 +46,41 @@ static int inline running_in_sram(void)
return addr == 0;
}
-void __naked __bare_init reset(void)
+void __bare_init at91sam926x_lowlevel_init(void)
{
u32 r;
int i;
int in_sram = running_in_sram();
+ struct at91sam926x_lowlevel_cfg cfg;
- common_reset();
+ at91sam926x_lowlevel_board_config(&cfg);
- __raw_writel(CONFIG_SYS_WDTC_WDMR_VAL, AT91_BASE_WDT + AT91_WDT_MR);
+ __raw_writel(cfg.wdt_mr, AT91_BASE_WDT + AT91_WDT_MR);
/* configure PIOx as EBI0 D[16-31] */
#ifdef CONFIG_ARCH_AT91SAM9263
- __raw_writel(CONFIG_SYS_PIOD_PDR_VAL1, AT91_BASE_PIOD + PIO_PDR);
- __raw_writel(CONFIG_SYS_PIOD_PPUDR_VAL, AT91_BASE_PIOD + PIO_PUDR);
- __raw_writel(CONFIG_SYS_PIOD_PPUDR_VAL, AT91_BASE_PIOD + PIO_ASR);
+ __raw_writel(cfg.ebi_pio_pdr, AT91_BASE_PIOD + PIO_PDR);
+ __raw_writel(cfg.ebi_pio_ppudr, AT91_BASE_PIOD + PIO_PUDR);
+ __raw_writel(cfg.ebi_pio_ppudr, AT91_BASE_PIOD + PIO_ASR);
#else
- __raw_writel(CONFIG_SYS_PIOC_PDR_VAL1, AT91_BASE_PIOC + PIO_PDR);
- __raw_writel(CONFIG_SYS_PIOC_PPUDR_VAL, AT91_BASE_PIOC + PIO_PUDR);
+ __raw_writel(cfg.ebi_pio_pdr, AT91_BASE_PIOC + PIO_PDR);
+ __raw_writel(cfg.ebi_pio_ppudrL, AT91_BASE_PIOC + PIO_PUDR);
#endif
#if defined(AT91_MATRIX_EBI0CSA)
- at91_sys_write(AT91_MATRIX_EBI0CSA, CONFIG_SYS_MATRIX_EBI0CSA_VAL);
+ at91_sys_write(AT91_MATRIX_EBI0CSA, cfg.ebi_csa);
#else /* AT91_MATRIX_EBICSA */
- at91_sys_write(AT91_MATRIX_EBICSA, CONFIG_SYS_MATRIX_EBICSA_VAL);
+ at91_sys_write(AT91_MATRIX_EBICSA, cfg.ebi_csa);
#endif
/* flash */
- at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_MODE, CONFIG_SYS_SMC_MODE_VAL);
+ at91_smc_write(cfg.smc_cs, AT91_SMC_MODE, cfg.smc_mode);
- at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_CYCLE, CONFIG_SYS_SMC_CYCLE_VAL);
+ at91_smc_write(cfg.smc_cs, AT91_SMC_CYCLE, cfg.smc_cycle);
- at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_PULSE, CONFIG_SYS_SMC_PULSE_VAL);
+ at91_smc_write(cfg.smc_cs, AT91_SMC_PULSE, cfg.smc_pulse);
- at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_SETUP, CONFIG_SYS_SMC_SETUP_VAL);
+ at91_smc_write(cfg.smc_cs, AT91_SMC_SETUP, cfg.smc_setup);
/*
* PMC Check if the PLL is already initialized
@@ -89,7 +92,7 @@ void __naked __bare_init reset(void)
/*
* Enable the Main Oscillator
*/
- at91_pmc_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL);
+ at91_pmc_write(AT91_CKGR_MOR, cfg.pmc_mor);
do {
r = at91_pmc_read(AT91_PMC_SR);
@@ -98,7 +101,7 @@ void __naked __bare_init reset(void)
/*
* PLLAR: x MHz for PCK
*/
- at91_pmc_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL);
+ at91_pmc_write(AT91_CKGR_PLLAR, cfg.pmc_pllar);
do {
r = at91_pmc_read(AT91_PMC_SR);
@@ -107,14 +110,14 @@ void __naked __bare_init reset(void)
/*
* PCK/x = MCK Master Clock from SLOW
*/
- at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR1_VAL);
+ at91_pmc_write(AT91_PMC_MCKR, cfg.pmc_mckr1);
pmc_check_mckrdy();
/*
* PCK/x = MCK Master Clock from PLLA
*/
- at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL);
+ at91_pmc_write(AT91_PMC_MCKR, cfg.pmc_mckr2);
pmc_check_mckrdy();
@@ -133,13 +136,13 @@ void __naked __bare_init reset(void)
at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
/* SDRAMC_TR - Refresh Timer register */
- at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL1);
+ at91_sys_write(AT91_SDRAMC_TR, cfg.sdrc_tr1);
/* SDRAMC_CR - Configuration register*/
- at91_sys_write(AT91_SDRAMC_CR, CONFIG_SYS_SDRC_CR_VAL);
+ at91_sys_write(AT91_SDRAMC_CR, cfg.sdrc_cr);
/* Memory Device Type */
- at91_sys_write(AT91_SDRAMC_MDR, CONFIG_SYS_SDRC_MDR_VAL);
+ at91_sys_write(AT91_SDRAMC_MDR, cfg.sdrc_mdr);
/* SDRAMC_MR : Precharge All */
at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
@@ -167,13 +170,13 @@ void __naked __bare_init reset(void)
access_sdram();
/* SDRAMC_TR : Refresh Timer Counter */
- at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL2);
+ at91_sys_write(AT91_SDRAMC_TR, cfg.sdrc_tr2);
/* access SDRAM */
access_sdram();
/* User reset enable*/
- at91_sys_write(AT91_RSTC_MR, CONFIG_SYS_RSTC_RMR_VAL);
+ at91_sys_write(AT91_RSTC_MR, cfg.rstc_rmr);
#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
/* MATRIX_MCFG - REMAP all masters */
@@ -190,3 +193,18 @@ void __naked __bare_init reset(void)
end:
board_init_lowlevel_return();
}
+
+void __naked __bare_init reset(void)
+{
+ common_reset();
+
+#ifdef CONFIG_ARCH_AT91SAM9263
+ arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE - 16);
+#elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10)
+ arm_setup_stack(AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 16);
+#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
+ arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16);
+#endif
+
+ at91sam926x_lowlevel_init();
+}
diff --git a/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h b/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h
new file mode 100644
index 0000000..29d9628
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#ifndef __AT91_LOWLEVEL_INIT_H__
+#define __AT91_LOWLEVEL_INIT_H__
+
+struct at91sam926x_lowlevel_cfg {
+ u32 wdt_mr;
+ u32 ebi_pio_pdr;
+ u32 ebi_pio_ppudr;
+ u32 ebi_csa;
+ u32 smc_cs;
+ u32 smc_mode;
+ u32 smc_cycle;
+ u32 smc_pulse;
+ u32 smc_setup;
+ u32 pmc_mor;
+ u32 pmc_pllar;
+ u32 pmc_mckr1;
+ u32 pmc_mckr2;
+ u32 sdrc_cr;
+ u32 sdrc_tr1;
+ u32 sdrc_mdr;
+ u32 sdrc_tr2;
+ u32 rstc_rmr;
+};
+
+void at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg);
+
+#endif /* __AT91_LOWLEVEL_INIT_H__ */
--
1.7.10.4
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 3/7] at91: sam926x: switch lowlevel param to c code
2013-01-19 7:35 ` [PATCH 1/7] at91: add test commamd to emulate bootrom boot Jean-Christophe PLAGNIOL-VILLARD
@ 2013-01-19 7:35 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 14+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-01-19 7:35 UTC (permalink / raw)
To: barebox
Instead of hardcode define use a struct that the board fill
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/boards/at91sam9263ek/Makefile | 5 +
arch/arm/boards/at91sam9263ek/config.h | 99 +-------------
arch/arm/boards/at91sam9263ek/lowlevel_init.c | 104 +++++++++++++++
arch/arm/boards/mmccpu/Makefile | 5 +
arch/arm/boards/mmccpu/config.h | 130 +------------------
arch/arm/boards/mmccpu/lowlevel_init.c | 135 ++++++++++++++++++++
arch/arm/boards/pm9261/Makefile | 5 +
arch/arm/boards/pm9261/config.h | 99 +-------------
arch/arm/boards/pm9261/lowlevel_init.c | 102 +++++++++++++++
arch/arm/boards/pm9263/Makefile | 5 +
arch/arm/boards/pm9263/config.h | 115 +----------------
arch/arm/boards/pm9263/lowlevel_init.c | 121 ++++++++++++++++++
arch/arm/mach-at91/at91sam926x_lowlevel_init.c | 64 ++++++----
.../mach-at91/include/mach/at91_lowlevel_init.h | 33 +++++
14 files changed, 580 insertions(+), 442 deletions(-)
rewrite arch/arm/boards/at91sam9263ek/config.h (95%)
create mode 100644 arch/arm/boards/at91sam9263ek/lowlevel_init.c
rewrite arch/arm/boards/mmccpu/config.h (97%)
create mode 100644 arch/arm/boards/mmccpu/lowlevel_init.c
rewrite arch/arm/boards/pm9261/config.h (95%)
create mode 100644 arch/arm/boards/pm9261/lowlevel_init.c
rewrite arch/arm/boards/pm9263/config.h (97%)
create mode 100644 arch/arm/boards/pm9263/lowlevel_init.c
create mode 100644 arch/arm/mach-at91/include/mach/at91_lowlevel_init.h
diff --git a/arch/arm/boards/at91sam9263ek/Makefile b/arch/arm/boards/at91sam9263ek/Makefile
index eb072c0..aecbc5a 100644
--- a/arch/arm/boards/at91sam9263ek/Makefile
+++ b/arch/arm/boards/at91sam9263ek/Makefile
@@ -1 +1,6 @@
obj-y += init.o
+
+lowlevel_init-y = lowlevel_init.o
+obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
+
+pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
diff --git a/arch/arm/boards/at91sam9263ek/config.h b/arch/arm/boards/at91sam9263ek/config.h
dissimilarity index 95%
index 14eb4fe..cc12040 100644
--- a/arch/arm/boards/at91sam9263ek/config.h
+++ b/arch/arm/boards/at91sam9263ek/config.h
@@ -1,93 +1,6 @@
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
-
-#define MASTER_PLL_MUL 171
-#define MASTER_PLL_DIV 14
-
-/* clocks */
-#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOSCEN | \
- (255 << 8)) /* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- AT91_PMC_OUT | \
- AT91_PMC_PLLCOUNT | /* PLL Counter */ \
- (2 << 28) | /* PLL Clock Frequency Range */ \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
-
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-
-/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
-/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
-/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
- (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
- AT91_MATRIX_EBI0_CS1A_SDRAMC)
-
-/* SDRAM */
-/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
-/* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_3 | \
- AT91_SDRAMC_DBW_32 | \
- (1 << 8) | /* Write Recovery Delay */ \
- (7 << 12) | /* Row Cycle Delay */ \
- (2 << 16) | /* Row Precharge Delay */ \
- (2 << 20) | /* Row to Column Delay */ \
- (5 << 24) | /* Active to Precharge Delay */ \
- (1 << 28)) /* Exit Self Refresh to Active Delay */
-
-/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-
-/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC_CS 0
-#define CONFIG_SYS_SMC_SETUP_VAL \
- (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
- AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
-#define CONFIG_SYS_SMC_PULSE_VAL \
- (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
- AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
-#define CONFIG_SYS_SMC_CYCLE_VAL \
- (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
-#define CONFIG_SYS_SMC_MODE_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(6))
-
-/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
- (AT91_RSTC_KEY | \
- AT91_RSTC_PROCRST | \
- AT91_RSTC_RSTTYP_WAKEUP | \
- AT91_RSTC_RSTTYP_WATCHDOG)
-
-/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
- AT91_WDT_WDV | \
- AT91_WDT_WDDIS | \
- AT91_WDT_WDD)
-
-#endif /* __CONFIG_H */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
+
+#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/at91sam9263ek/lowlevel_init.c b/arch/arm/boards/at91sam9263ek/lowlevel_init.c
new file mode 100644
index 0000000..2f8b312
--- /dev/null
+++ b/arch/arm/boards/at91sam9263ek/lowlevel_init.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/hardware.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_wdt.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9_matrix.h>
+#include <mach/at91_lowlevel_init.h>
+
+#define MASTER_PLL_MUL 171
+#define MASTER_PLL_DIV 14
+
+void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
+{
+ /* Disable Watchdog */
+ cfg->wdt_mr =
+ AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
+ AT91_WDT_WDV |
+ AT91_WDT_WDDIS |
+ AT91_WDT_WDD;
+
+ /* define PDC[31:16] as DATA[31:16] */
+ cfg->ebi_pio_pdr = 0xFFFF0000;
+ /* no pull-up for D[31:16] */
+ cfg->ebi_pio_ppudr = 0xFFFF0000;
+ /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+ cfg->ebi_csa =
+ AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
+ AT91_MATRIX_EBI0_CS1A_SDRAMC;
+
+ cfg->smc_cs = 0;
+ cfg->smc_mode =
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_DBW_16 |
+ AT91_SMC_TDFMODE |
+ AT91_SMC_TDF_(6);
+ cfg->smc_cycle =
+ AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
+ cfg->smc_pulse =
+ AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
+ AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
+ cfg->smc_setup =
+ AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
+ AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
+
+ cfg->pmc_mor =
+ AT91_PMC_MOSCEN |
+ (255 << 8); /* Main Oscillator Start-up Time */
+ cfg->pmc_pllar =
+ AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
+ AT91_PMC_OUT |
+ AT91_PMC_PLLCOUNT | /* PLL Counter */
+ (2 << 28) | /* PLL Clock Frequency Range */
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr1 =
+ AT91_PMC_CSS_SLOW |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr2 =
+ AT91_PMC_CSS_PLLA |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+
+ /* SDRAM */
+ /* SDRAMC_TR - Refresh Timer register */
+ cfg->sdrc_tr1 = 0x13C;
+ /* SDRAMC_CR - Configuration register*/
+ cfg->sdrc_cr =
+ AT91_SDRAMC_NC_9 |
+ AT91_SDRAMC_NR_13 |
+ AT91_SDRAMC_NB_4 |
+ AT91_SDRAMC_CAS_3 |
+ AT91_SDRAMC_DBW_32 |
+ (1 << 8) | /* Write Recovery Delay */
+ (7 << 12) | /* Row Cycle Delay */
+ (2 << 16) | /* Row Precharge Delay */
+ (2 << 20) | /* Row to Column Delay */
+ (5 << 24) | /* Active to Precharge Delay */
+ (1 << 28); /* Exit Self Refresh to Active Delay */
+
+ /* Memory Device Register -> SDRAM */
+ cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
+ /* SDRAM_TR */
+ cfg->sdrc_tr2 = 1200;
+
+ /* user reset enable */
+ cfg->rstc_rmr =
+ AT91_RSTC_KEY |
+ AT91_RSTC_PROCRST |
+ AT91_RSTC_RSTTYP_WAKEUP |
+ AT91_RSTC_RSTTYP_WATCHDOG;
+}
diff --git a/arch/arm/boards/mmccpu/Makefile b/arch/arm/boards/mmccpu/Makefile
index eb072c0..aecbc5a 100644
--- a/arch/arm/boards/mmccpu/Makefile
+++ b/arch/arm/boards/mmccpu/Makefile
@@ -1 +1,6 @@
obj-y += init.o
+
+lowlevel_init-y = lowlevel_init.o
+obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
+
+pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
diff --git a/arch/arm/boards/mmccpu/config.h b/arch/arm/boards/mmccpu/config.h
dissimilarity index 97%
index e6215dc..c896a93 100644
--- a/arch/arm/boards/mmccpu/config.h
+++ b/arch/arm/boards/mmccpu/config.h
@@ -1,124 +1,6 @@
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define AT91_MAIN_CLOCK 18432000
-
-/* values */
-#define MASTER_PLL_MUL 54
-#define MASTER_PLL_DIV 4
-
-/* clocks */
-#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOSCEN | \
- (255 << 8)) /* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- AT91_PMC_OUT | \
- AT91_PMC_PLLCOUNT | /* PLL Counter */ \
- (2 << 28) | /* PLL Clock Frequency Range */ \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
-
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-
-/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
-/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
-/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 1.8V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
- (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_1_8V | \
- AT91_MATRIX_EBI0_CS1A_SDRAMC | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA)
-
-/* SDRAM */
-/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x13c
-/* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_3 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* tWR - Write Recovery Delay */ \
- (8 << 12) | /* tRC - Row Cycle Delay */ \
- (2 << 16) | /* tRP - Row Precharge Delay */ \
- (2 << 20) | /* tRCD - Row to Column Delay */ \
- (5 << 24) | /* tRAS - Active to Precharge Delay */ \
- (12 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
-
-/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_TR_VAL2 780 /* SDRAM_TR */
-
-/* setup CS0 (NOR Flash) - 16-bit */
-#define CONFIG_SYS_SMC_CS 0
-#if 1
-#define CONFIG_SYS_SMC_SETUP_VAL \
- (AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | \
- AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0))
-#define CONFIG_SYS_SMC_PULSE_VAL \
- (AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | \
- AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13))
-#define CONFIG_SYS_SMC_CYCLE_VAL \
- (AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16))
-#define CONFIG_SYS_SMC_MODE_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(6))
-#elif 0 /* slow setup */
-#define CONFIG_SYS_SMC_SETUP_VAL \
- (AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | \
- AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0))
-#define CONFIG_SYS_SMC_PULSE_VAL \
- (AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | \
- AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13))
-#define CONFIG_SYS_SMC_CYCLE_VAL \
- (AT91_SMC_NWECYCLE_(0xd00) | AT91_SMC_NRDCYCLE_(0xd00))
-#define CONFIG_SYS_SMC_MODE_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(1))
-#else /* RONETIX' original values */
-#define CONFIG_SYS_SMC_SETUP_VAL \
- (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
- AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
-#define CONFIG_SYS_SMC_PULSE_VAL \
- (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
- AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
-#define CONFIG_SYS_SMC_CYCLE_VAL \
- (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
-#define CONFIG_SYS_SMC_MODE_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(6))
-#endif
-
-/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
- (AT91_RSTC_KEY | \
- AT91_RSTC_PROCRST | \
- AT91_RSTC_RSTTYP_WAKEUP | \
- AT91_RSTC_RSTTYP_WATCHDOG)
-
-/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
- AT91_WDT_WDV | \
- AT91_WDT_WDDIS | \
- AT91_WDT_WDD)
-
-#endif /* __CONFIG_H */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define AT91_MAIN_CLOCK 18432000
+
+#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/mmccpu/lowlevel_init.c b/arch/arm/boards/mmccpu/lowlevel_init.c
new file mode 100644
index 0000000..68c609f
--- /dev/null
+++ b/arch/arm/boards/mmccpu/lowlevel_init.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/hardware.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_wdt.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9_matrix.h>
+#include <mach/at91_lowlevel_init.h>
+
+#define MASTER_PLL_MUL 54
+#define MASTER_PLL_DIV 4
+
+void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
+{
+ /* Disable Watchdog */
+ cfg->wdt_mr =
+ AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
+ AT91_WDT_WDV |
+ AT91_WDT_WDDIS |
+ AT91_WDT_WDD;
+
+ /* define PDC[31:16] as DATA[31:16] */
+ cfg->ebi_pio_pdr = 0xFFFF0000;
+ /* no pull-up for D[31:16] */
+ cfg->ebi_pio_ppudr = 0xFFFF0000;
+ /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+ cfg->ebi_csa =
+ AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_1_8V |
+ AT91_MATRIX_EBI0_CS1A_SDRAMC |
+ AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA;
+
+ cfg->smc_cs = 0;
+#if 1
+ cfg->smc_mode =
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_DBW_16 |
+ AT91_SMC_TDFMODE |
+ AT91_SMC_TDF_(6);
+ cfg->smc_cycle =
+ AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16);
+ cfg->smc_pulse =
+ AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) |
+ AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13);
+ cfg->smc_setup =
+ AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) |
+ AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0);
+#elif 0 /* slow setup */
+ cfg->smc_mode =
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_DBW_16 |
+ AT91_SMC_TDFMODE |
+ AT91_SMC_TDF_(1);
+ cfg->smc_cycle =
+ AT91_SMC_NWECYCLE_(0xd00) | AT91_SMC_NRDCYCLE_(0xd00);
+ cfg->smc_pulse =
+ AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) |
+ AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13);
+ cfg->smc_setup =
+ AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) |
+ AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0);
+#else /* RONETIX' original values */
+ cfg->smc_mode =
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_DBW_16 |
+ AT91_SMC_TDFMODE |
+ AT91_SMC_TDF_(6);
+ cfg->smc_cycle =
+ AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
+ cfg->smc_pulse =
+ AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
+ AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
+ cfg->smc_setup =
+ AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
+ AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
+#endif
+
+ cfg->pmc_mor =
+ AT91_PMC_MSCEN |
+ (255 << 8); /* Main Oscillator Start-up Time */
+ cfg->pmc_pllar =
+ AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
+ AT91_PMC_OUT |
+ AT91_PMC_PLLCOUNT | /* PLL Counter */
+ (2 << 28) | /* PLL Clock Frequency Range */
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr1 =
+ AT91_PMC_CSS_SLOW |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr2 =
+ AT91_PMC_CSS_PLLA |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+
+ /* SDRAM */
+ /* SDRAMC_TR - Refresh Timer register */
+ cfg->sdrc_tr1 = 0x13C;
+ /* SDRAMC_CR - Configuration register*/
+ cfg->sdrc_cr =
+ AT91_SDRAMC_NC_9 |
+ AT91_SDRAMC_NR_13 |
+ AT91_SDRAMC_NB_4 |
+ AT91_SDRAMC_CAS_3 |
+ AT91_SDRAMC_DBW_32 |
+ (2 << 8) | /* tWR - Write Recovery Delay */
+ (8 << 12) | /* tRC - Row Cycle Delay */
+ (2 << 16) | /* tRP - Row Precharge Delay */
+ (2 << 20) | /* tRCD - Row to Column Delay */
+ (5 << 24) | /* tRAS - Active to Precharge Delay */
+ (12 << 28); /* tXSR - Exit Self Refresh to Active Delay */
+
+ /* Memory Device Register -> SDRAM */
+ cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
+ /* SDRAM_TR */
+ cfg->sdrc_tr2 = 780;
+
+ /* user reset enable */
+ cfg->rstc_rmr =
+ AT91_RSTC_KEY |
+ AT91_RSTC_PROCRST |
+ AT91_RSTC_RSTTYP_WAKEUP |
+ AT91_RSTC_RSTTYP_WATCHDOG;
+}
diff --git a/arch/arm/boards/pm9261/Makefile b/arch/arm/boards/pm9261/Makefile
index eb072c0..aecbc5a 100644
--- a/arch/arm/boards/pm9261/Makefile
+++ b/arch/arm/boards/pm9261/Makefile
@@ -1 +1,6 @@
obj-y += init.o
+
+lowlevel_init-y = lowlevel_init.o
+obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
+
+pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
diff --git a/arch/arm/boards/pm9261/config.h b/arch/arm/boards/pm9261/config.h
dissimilarity index 95%
index 4602aa7..006820c 100644
--- a/arch/arm/boards/pm9261/config.h
+++ b/arch/arm/boards/pm9261/config.h
@@ -1,93 +1,6 @@
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
-
-#define MASTER_PLL_DIV 15
-#define MASTER_PLL_MUL 162
-#define MAIN_PLL_DIV 2
-
-/* clocks */
-#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOSCEN | \
- (255 << 8)) /* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- AT91_PMC_OUT | \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
-
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-
-/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
-/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
-
-/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
-#define CONFIG_SYS_MATRIX_EBICSA_VAL \
- (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC)
-
-/* SDRAM */
-/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
-/* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_3 | \
- AT91_SDRAMC_DBW_32 | \
- (1 << 8) | /* Write Recovery Delay */ \
- (7 << 12) | /* Row Cycle Delay */ \
- (3 << 16) | /* Row Precharge Delay */ \
- (2 << 20) | /* Row to Column Delay */ \
- (5 << 24) | /* Active to Precharge Delay */ \
- (1 << 28)) /* Exit Self Refresh to Active Delay */
-
-/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-
-/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC_CS 0
-#define CONFIG_SYS_SMC_SETUP_VAL \
- (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
- AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
-#define CONFIG_SYS_SMC_PULSE_VAL \
- (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
- AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
-#define CONFIG_SYS_SMC_CYCLE_VAL \
- (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
-#define CONFIG_SYS_SMC_MODE_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(6))
-
-/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
- (AT91_RSTC_KEY | \
- AT91_RSTC_PROCRST | \
- AT91_RSTC_RSTTYP_WAKEUP | \
- AT91_RSTC_RSTTYP_WATCHDOG)
-
-/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
- AT91_WDT_WDV | \
- AT91_WDT_WDDIS | \
- AT91_WDT_WDD)
-
-#endif /* __CONFIG_H */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
+
+#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/pm9261/lowlevel_init.c b/arch/arm/boards/pm9261/lowlevel_init.c
new file mode 100644
index 0000000..91a64b4
--- /dev/null
+++ b/arch/arm/boards/pm9261/lowlevel_init.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/hardware.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_wdt.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9_matrix.h>
+#include <mach/at91_lowlevel_init.h>
+
+#define MASTER_PLL_DIV 15
+#define MASTER_PLL_MUL 162
+#define MAIN_PLL_DIV 2
+
+void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
+{
+ /* Disable Watchdog */
+ cfg->wdt_mr =
+ AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
+ AT91_WDT_WDV |
+ AT91_WDT_WDDIS |
+ AT91_WDT_WDD;
+
+ /* define PDC[31:16] as DATA[31:16] */
+ cfg->ebi_pio_pdr = 0xFFFF0000;
+ /* no pull-up for D[31:16] */
+ cfg->ebi_pio_ppudr = 0xFFFF0000;
+ /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+ cfg->ebi_csa =
+ AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC;
+
+ cfg->smc_cs = 0;
+ cfg->smc_mode =
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_DBW_16 |
+ AT91_SMC_TDFMODE |
+ AT91_SMC_TDF_(6);
+ cfg->smc_cycle =
+ AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
+ cfg->smc_pulse =
+ AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
+ AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
+ cfg->smc_setup =
+ AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
+ AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
+
+ cfg->pmc_mor =
+ AT91_PMC_MOSCEN |
+ (255 << 8); /* Main Oscillator Start-up Time */
+ cfg->pmc_pllar =
+ AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
+ AT91_PMC_OUT |
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr1 =
+ AT91_PMC_CSS_SLOW |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr2 =
+ AT91_PMC_CSS_PLLA |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+
+ /* SDRAM */
+ /* SDRAMC_TR - Refresh Timer register */
+ cfg->sdrc_tr1 = 0x13C;
+ /* SDRAMC_CR - Configuration register*/
+ cfg->sdrc_cr =
+ AT91_SDRAMC_NC_9 |
+ AT91_SDRAMC_NR_13 |
+ AT91_SDRAMC_NB_4 |
+ AT91_SDRAMC_CAS_3 |
+ AT91_SDRAMC_DBW_32 |
+ (1 << 8) | /* Write Recovery Delay */
+ (7 << 12) | /* Row Cycle Delay */
+ (3 << 16) | /* Row Precharge Delay */
+ (2 << 20) | /* Row to Column Delay */
+ (5 << 24) | /* Active to Precharge Delay */
+ (1 << 28); /* Exit Self Refresh to Active Delay */
+
+ /* Memory Device Register -> SDRAM */
+ cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
+ /* SDRAM_TR */
+ cfg->sdrc_tr2 = 1200;
+
+ /* user reset enable */
+ cfg->rstc_rmr =
+ AT91_RSTC_KEY |
+ AT91_RSTC_PROCRST |
+ AT91_RSTC_RSTTYP_WAKEUP |
+ AT91_RSTC_RSTTYP_WATCHDOG;
+}
diff --git a/arch/arm/boards/pm9263/Makefile b/arch/arm/boards/pm9263/Makefile
index eb072c0..aecbc5a 100644
--- a/arch/arm/boards/pm9263/Makefile
+++ b/arch/arm/boards/pm9263/Makefile
@@ -1 +1,6 @@
obj-y += init.o
+
+lowlevel_init-y = lowlevel_init.o
+obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
+
+pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
diff --git a/arch/arm/boards/pm9263/config.h b/arch/arm/boards/pm9263/config.h
dissimilarity index 97%
index 322c1f3..9066613 100644
--- a/arch/arm/boards/pm9263/config.h
+++ b/arch/arm/boards/pm9263/config.h
@@ -1,109 +1,6 @@
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define AT91_MAIN_CLOCK 18432000
-
-#define MASTER_PLL_DIV 6
-#define MASTER_PLL_MUL 65
-#define MAIN_PLL_DIV 2 /* 2 or 4 */
-
-/* clocks */
-#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOSCEN | \
- (255 << 8)) /* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- AT91_PMC_OUT | \
- AT91_PMC_PLLCOUNT | /* PLL Counter */ \
- (2 << 28) | /* PLL Clock Frequency Range */ \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
-
-#if (MAIN_PLL_DIV == 2)
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-#else
-/* PCK/4 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91RM9200_PMC_MDIV_3 | \
- AT91_PMC_PDIV_1)
-/* PCK/4 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91RM9200_PMC_MDIV_3 | \
- AT91_PMC_PDIV_1)
-#endif
-/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
-/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
-/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
- (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
- AT91_MATRIX_EBI0_CS1A_SDRAMC)
-
-/* SDRAM */
-/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
-/* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_2 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* tWR - Write Recovery Delay */ \
- (7 << 12) | /* tRC - Row Cycle Delay */ \
- (2 << 16) | /* tRP - Row Precharge Delay */ \
- (2 << 20) | /* tRCD - Row to Column Delay */ \
- (5 << 24) | /* tRAS - Active to Precharge Delay */ \
- (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
-
-/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-
-/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC_CS 0
-#define CONFIG_SYS_SMC_SETUP_VAL \
- (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
- AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
-#define CONFIG_SYS_SMC_PULSE_VAL \
- (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
- AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
-#define CONFIG_SYS_SMC_CYCLE_VAL \
- (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
-#define CONFIG_SYS_SMC_MODE_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(6))
-
-/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
- (AT91_RSTC_KEY | \
- AT91_RSTC_PROCRST | \
- AT91_RSTC_RSTTYP_WAKEUP | \
- AT91_RSTC_RSTTYP_WATCHDOG)
-
-/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
- AT91_WDT_WDV | \
- AT91_WDT_WDDIS | \
- AT91_WDT_WDD)
-
-
-#endif /* __CONFIG_H */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define AT91_MAIN_CLOCK 18432000
+
+#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/pm9263/lowlevel_init.c b/arch/arm/boards/pm9263/lowlevel_init.c
new file mode 100644
index 0000000..6336d51
--- /dev/null
+++ b/arch/arm/boards/pm9263/lowlevel_init.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/hardware.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_wdt.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91sam9_matrix.h>
+#include <mach/at91_lowlevel_init.h>
+
+#define MASTER_PLL_DIV 6
+#define MASTER_PLL_MUL 65
+#define MAIN_PLL_DIV 2 /* 2 or 4 */
+
+void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
+{
+ /* Disable Watchdog */
+ cfg->wdt_mr =
+ AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
+ AT91_WDT_WDV |
+ AT91_WDT_WDDIS |
+ AT91_WDT_WDD;
+
+ /* define PDC[31:16] as DATA[31:16] */
+ cfg->ebi_pio_pdr = 0xFFFF0000;
+ /* no pull-up for D[31:16] */
+ cfg->ebi_pio_ppudr = 0xFFFF0000;
+ /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+ cfg->ebi_csa =
+ AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
+ AT91_MATRIX_EBI0_CS1A_SDRAMC;
+
+ cfg->smc_cs = 0;
+ cfg->smc_mode =
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_DBW_16 |
+ AT91_SMC_TDFMODE |
+ AT91_SMC_TDF_(6);
+ cfg->smc_cycle =
+ AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
+ cfg->smc_pulse =
+ AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
+ AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
+ cfg->smc_setup =
+ AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
+ AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
+
+ cfg->pmc_mor =
+ AT91_PMC_MOSCEN |
+ (255 << 8); /* Main Oscillator Start-up Time */
+ cfg->pmc_pllar =
+ AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
+ AT91_PMC_OUT |
+ AT91_PMC_PLLCOUNT | /* PLL Counter */
+ (2 << 28) | /* PLL Clock Frequency Range */
+ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
+
+ if (MAIN_PLL_DIV == 2) {
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr1 =
+ AT91_PMC_CSS_SLOW |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr2 =
+ AT91_PMC_CSS_PLLA |
+ AT91_PMC_PRES_1 |
+ AT91SAM9_PMC_MDIV_2 |
+ AT91_PMC_PDIV_1;
+ } else {
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr1 =
+ AT91_PMC_CSS_SLOW |
+ AT91_PMC_PRES_1 |
+ AT91RM9200_PMC_MDIV_3 |
+ AT91_PMC_PDIV_1;
+ /* PCK/2 = MCK Master Clock from PLLA */
+ cfg->pmc_mckr2 =
+ AT91_PMC_CSS_PLLA |
+ AT91_PMC_PRES_1 |
+ AT91RM9200_PMC_MDIV_3 |
+ AT91_PMC_PDIV_1;
+ }
+
+ /* SDRAM */
+ /* SDRAMC_TR - Refresh Timer register */
+ cfg->sdrc_tr1 = 0x3AA;
+ /* SDRAMC_CR - Configuration register*/
+ cfg->sdrc_cr =
+ AT91_SDRAMC_NC_9 |
+ AT91_SDRAMC_NR_13 |
+ AT91_SDRAMC_NB_4 |
+ AT91_SDRAMC_CAS_2 |
+ AT91_SDRAMC_DBW_32 |
+ (2 << 8) | /* tWR - Write Recovery Delay */
+ (7 << 12) | /* tRC - Row Cycle Delay */
+ (2 << 16) | /* tRP - Row Precharge Delay */
+ (2 << 20) | /* tRCD - Row to Column Delay */
+ (5 << 24) | /* tRAS - Active to Precharge Delay */
+ (8 << 28); /* tXSR - Exit Self Refresh to Active Delay */
+
+ /* Memory Device Register -> SDRAM */
+ cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
+ /* SDRAM_TR */
+ cfg->sdrc_tr2 = 1200;
+
+ /* user reset enable */
+ cfg->rstc_rmr =
+ AT91_RSTC_KEY |
+ AT91_RSTC_PROCRST |
+ AT91_RSTC_RSTTYP_WAKEUP |
+ AT91_RSTC_RSTTYP_WATCHDOG;
+}
diff --git a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
index 4dec275..e7145b4 100644
--- a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
@@ -19,8 +19,10 @@
#include <mach/at91sam9_matrix.h>
#include <mach/at91sam9_sdramc.h>
#include <mach/at91sam9_smc.h>
+#include <mach/at91_lowlevel_init.h>
#include <mach/io.h>
#include <init.h>
+#include <sizes.h>
static void inline access_sdram(void)
{
@@ -44,40 +46,41 @@ static int inline running_in_sram(void)
return addr == 0;
}
-void __naked __bare_init reset(void)
+void __bare_init at91sam926x_lowlevel_init(void)
{
u32 r;
int i;
int in_sram = running_in_sram();
+ struct at91sam926x_lowlevel_cfg cfg;
- common_reset();
+ at91sam926x_lowlevel_board_config(&cfg);
- __raw_writel(CONFIG_SYS_WDTC_WDMR_VAL, AT91_BASE_WDT + AT91_WDT_MR);
+ __raw_writel(cfg.wdt_mr, AT91_BASE_WDT + AT91_WDT_MR);
/* configure PIOx as EBI0 D[16-31] */
#ifdef CONFIG_ARCH_AT91SAM9263
- __raw_writel(CONFIG_SYS_PIOD_PDR_VAL1, AT91_BASE_PIOD + PIO_PDR);
- __raw_writel(CONFIG_SYS_PIOD_PPUDR_VAL, AT91_BASE_PIOD + PIO_PUDR);
- __raw_writel(CONFIG_SYS_PIOD_PPUDR_VAL, AT91_BASE_PIOD + PIO_ASR);
+ __raw_writel(cfg.ebi_pio_pdr, AT91_BASE_PIOD + PIO_PDR);
+ __raw_writel(cfg.ebi_pio_ppudr, AT91_BASE_PIOD + PIO_PUDR);
+ __raw_writel(cfg.ebi_pio_ppudr, AT91_BASE_PIOD + PIO_ASR);
#else
- __raw_writel(CONFIG_SYS_PIOC_PDR_VAL1, AT91_BASE_PIOC + PIO_PDR);
- __raw_writel(CONFIG_SYS_PIOC_PPUDR_VAL, AT91_BASE_PIOC + PIO_PUDR);
+ __raw_writel(cfg.ebi_pio_pdr, AT91_BASE_PIOC + PIO_PDR);
+ __raw_writel(cfg.ebi_pio_ppudrL, AT91_BASE_PIOC + PIO_PUDR);
#endif
#if defined(AT91_MATRIX_EBI0CSA)
- at91_sys_write(AT91_MATRIX_EBI0CSA, CONFIG_SYS_MATRIX_EBI0CSA_VAL);
+ at91_sys_write(AT91_MATRIX_EBI0CSA, cfg.ebi_csa);
#else /* AT91_MATRIX_EBICSA */
- at91_sys_write(AT91_MATRIX_EBICSA, CONFIG_SYS_MATRIX_EBICSA_VAL);
+ at91_sys_write(AT91_MATRIX_EBICSA, cfg.ebi_csa);
#endif
/* flash */
- at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_MODE, CONFIG_SYS_SMC_MODE_VAL);
+ at91_smc_write(cfg.smc_cs, AT91_SMC_MODE, cfg.smc_mode);
- at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_CYCLE, CONFIG_SYS_SMC_CYCLE_VAL);
+ at91_smc_write(cfg.smc_cs, AT91_SMC_CYCLE, cfg.smc_cycle);
- at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_PULSE, CONFIG_SYS_SMC_PULSE_VAL);
+ at91_smc_write(cfg.smc_cs, AT91_SMC_PULSE, cfg.smc_pulse);
- at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_SETUP, CONFIG_SYS_SMC_SETUP_VAL);
+ at91_smc_write(cfg.smc_cs, AT91_SMC_SETUP, cfg.smc_setup);
/*
* PMC Check if the PLL is already initialized
@@ -89,7 +92,7 @@ void __naked __bare_init reset(void)
/*
* Enable the Main Oscillator
*/
- at91_pmc_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL);
+ at91_pmc_write(AT91_CKGR_MOR, cfg.pmc_mor);
do {
r = at91_pmc_read(AT91_PMC_SR);
@@ -98,7 +101,7 @@ void __naked __bare_init reset(void)
/*
* PLLAR: x MHz for PCK
*/
- at91_pmc_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL);
+ at91_pmc_write(AT91_CKGR_PLLAR, cfg.pmc_pllar);
do {
r = at91_pmc_read(AT91_PMC_SR);
@@ -107,14 +110,14 @@ void __naked __bare_init reset(void)
/*
* PCK/x = MCK Master Clock from SLOW
*/
- at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR1_VAL);
+ at91_pmc_write(AT91_PMC_MCKR, cfg.pmc_mckr1);
pmc_check_mckrdy();
/*
* PCK/x = MCK Master Clock from PLLA
*/
- at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL);
+ at91_pmc_write(AT91_PMC_MCKR, cfg.pmc_mckr2);
pmc_check_mckrdy();
@@ -133,13 +136,13 @@ void __naked __bare_init reset(void)
at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
/* SDRAMC_TR - Refresh Timer register */
- at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL1);
+ at91_sys_write(AT91_SDRAMC_TR, cfg.sdrc_tr1);
/* SDRAMC_CR - Configuration register*/
- at91_sys_write(AT91_SDRAMC_CR, CONFIG_SYS_SDRC_CR_VAL);
+ at91_sys_write(AT91_SDRAMC_CR, cfg.sdrc_cr);
/* Memory Device Type */
- at91_sys_write(AT91_SDRAMC_MDR, CONFIG_SYS_SDRC_MDR_VAL);
+ at91_sys_write(AT91_SDRAMC_MDR, cfg.sdrc_mdr);
/* SDRAMC_MR : Precharge All */
at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
@@ -167,13 +170,13 @@ void __naked __bare_init reset(void)
access_sdram();
/* SDRAMC_TR : Refresh Timer Counter */
- at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL2);
+ at91_sys_write(AT91_SDRAMC_TR, cfg.sdrc_tr2);
/* access SDRAM */
access_sdram();
/* User reset enable*/
- at91_sys_write(AT91_RSTC_MR, CONFIG_SYS_RSTC_RMR_VAL);
+ at91_sys_write(AT91_RSTC_MR, cfg.rstc_rmr);
#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
/* MATRIX_MCFG - REMAP all masters */
@@ -190,3 +193,18 @@ void __naked __bare_init reset(void)
end:
board_init_lowlevel_return();
}
+
+void __naked __bare_init reset(void)
+{
+ common_reset();
+
+#ifdef CONFIG_ARCH_AT91SAM9263
+ arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE - 16);
+#elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10)
+ arm_setup_stack(AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 16);
+#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
+ arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16);
+#endif
+
+ at91sam926x_lowlevel_init();
+}
diff --git a/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h b/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h
new file mode 100644
index 0000000..29d9628
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#ifndef __AT91_LOWLEVEL_INIT_H__
+#define __AT91_LOWLEVEL_INIT_H__
+
+struct at91sam926x_lowlevel_cfg {
+ u32 wdt_mr;
+ u32 ebi_pio_pdr;
+ u32 ebi_pio_ppudr;
+ u32 ebi_csa;
+ u32 smc_cs;
+ u32 smc_mode;
+ u32 smc_cycle;
+ u32 smc_pulse;
+ u32 smc_setup;
+ u32 pmc_mor;
+ u32 pmc_pllar;
+ u32 pmc_mckr1;
+ u32 pmc_mckr2;
+ u32 sdrc_cr;
+ u32 sdrc_tr1;
+ u32 sdrc_mdr;
+ u32 sdrc_tr2;
+ u32 rstc_rmr;
+};
+
+void at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg);
+
+#endif /* __AT91_LOWLEVEL_INIT_H__ */
--
1.7.10.4
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end of thread, other threads:[~2013-01-19 11:28 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-12-29 10:04 [PATCH 0/7] at91: add bootstrap support Jean-Christophe PLAGNIOL-VILLARD
2012-12-29 10:08 ` [PATCH 1/7] at91: add test commamd to emulate bootrom boot Jean-Christophe PLAGNIOL-VILLARD
2012-12-29 10:08 ` [PATCH 2/7] at91sam926x: lowlevel add external boot support Jean-Christophe PLAGNIOL-VILLARD
2012-12-29 10:08 ` [PATCH 3/7] at91: sam926x: switch lowlevel param to c code Jean-Christophe PLAGNIOL-VILLARD
2013-01-02 10:18 ` Sascha Hauer
2012-12-29 10:08 ` [PATCH 4/7] at91: usb-a9263 add lowlevel init Jean-Christophe PLAGNIOL-VILLARD
2012-12-29 10:08 ` [PATCH 5/7] introduce common bootstrap code Jean-Christophe PLAGNIOL-VILLARD
2012-12-29 10:08 ` [PATCH 6/7] at91: add bootstrap version Jean-Christophe PLAGNIOL-VILLARD
2013-01-02 11:41 ` Jan Lübbe
2013-01-04 13:12 ` Sascha Hauer
2012-12-29 10:08 ` [PATCH 7/7] at91: usb_a9263: " Jean-Christophe PLAGNIOL-VILLARD
2013-01-02 10:10 ` [PATCH 1/7] at91: add test commamd to emulate bootrom boot Sascha Hauer
2013-01-19 7:33 [PATCH 0/7 v2] at91: add bootstrap support Jean-Christophe PLAGNIOL-VILLARD
2013-01-19 7:35 ` [PATCH 1/7] at91: add test commamd to emulate bootrom boot Jean-Christophe PLAGNIOL-VILLARD
2013-01-19 7:35 ` [PATCH 3/7] at91: sam926x: switch lowlevel param to c code Jean-Christophe PLAGNIOL-VILLARD
2013-01-19 11:21 [PATCH 0/7 v3] at91: add bootstrap support Jean-Christophe PLAGNIOL-VILLARD
2013-01-19 11:26 ` [PATCH 1/7] at91: add test commamd to emulate bootrom boot Jean-Christophe PLAGNIOL-VILLARD
2013-01-19 11:26 ` [PATCH 3/7] at91: sam926x: switch lowlevel param to c code Jean-Christophe PLAGNIOL-VILLARD
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