[PATCH 0/5] at91sam926x: drop AT91_BASE_SYS for sdram controller + gpio cleanup

[PATCH 0/5] at91sam926x: drop AT91_BASE_SYS for sdram controller + gpio cleanup

[Jean-Christophe PLAGNIOL-VILLARD]

Hi,

The following changes since commit cd5f8e8aaf808ae19e7c1d2890f90f7de809a2c5:

  ARM pbl: inline decompress function (2013-02-03 08:27:59 +0800)

are available in the git repository at:

  git://git.jcrosoft.org/barebox.git delivery/at91sam926x_lowlevel_arm-entry

for you to fetch changes up to 453bfddd34c1c0babcd8389d63fd34b1bc764a34:

  at91sam9: drop AT91_BASE_SYS for sdram controller (2013-02-03 08:49:16 +0800)

----------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD (5):
      usb-a926x: only provide the resource if the driver is enable
      at91: gpio: split accessor so we can use them for early init
      at91sam926x_lowlevel_init: use pio macro
      at91sam926x_lowlevel_init: use struct to pass soc config
      at91sam9: drop AT91_BASE_SYS for sdram controller

 arch/arm/boards/tny-a926x/init.c                     |    2 +-
 arch/arm/boards/usb-a926x/init.c                     |   11 ++++++++-
 arch/arm/mach-at91/at91sam9260_devices.c             |    2 +-
 arch/arm/mach-at91/at91sam9260_lowlevel_init.c       |   19 +++++++++++----
 arch/arm/mach-at91/at91sam9261_devices.c             |    2 +-
 arch/arm/mach-at91/at91sam9261_lowlevel_init.c       |   19 +++++++++++----
 arch/arm/mach-at91/at91sam9263_devices.c             |    2 +-
 arch/arm/mach-at91/at91sam9263_lowlevel_init.c       |   19 +++++++++++----
 arch/arm/mach-at91/at91sam926x_lowlevel_init.c       |  152 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----------------------------------------------------
 arch/arm/mach-at91/at91sam9_reset.S                  |    4 ++--
 arch/arm/mach-at91/gpio.c                            |  131 +++++----------------------------------------------------------------------------------------------
 arch/arm/mach-at91/gpio.h                            |  148 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-at91/include/mach/at91_lowlevel_init.h |   11 +++++++--
 arch/arm/mach-at91/include/mach/at91sam9_sdramc.h    |  108 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----------
 14 files changed, 402 insertions(+), 228 deletions(-)
 create mode 100644 arch/arm/mach-at91/gpio.h

Best Regards,
J.

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[PATCH 1/5] usb-a926x: only provide the resource if the driver is enable

[Jean-Christophe PLAGNIOL-VILLARD]

usefull for bootstrap

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 arch/arm/boards/usb-a926x/init.c |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boards/usb-a926x/init.c b/arch/arm/boards/usb-a926x/init.c
index 0383280..e2da8ea 100644
--- a/arch/arm/boards/usb-a926x/init.c
+++ b/arch/arm/boards/usb-a926x/init.c
@@ -246,6 +246,15 @@ static struct at91_udc_data __initdata ek_udc_data = {
 	.pullup_pin	= -EINVAL,		/* pull-up driven by UDC */
 };
 
+static void usb_a9260_add_device_usb(void)
+{
+	at91_add_device_usbh_ohci(&ek_usbh_data);
+}
+#else
+static void usb_a9260_add_device_usb(void) {}
+#endif
+
+#ifdef CONFIG_USB_GADGET_DRIVER_AT91
 static void __init ek_add_device_udc(void)
 {
 	if (machine_is_usb_a9260() || machine_is_usb_a9g20())
-- 
1.7.10.4


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[PATCH 2/5] at91: gpio: split accessor so we can use them for early init

[Jean-Christophe PLAGNIOL-VILLARD]

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 arch/arm/mach-at91/gpio.c |  131 ++-------------------------------------
 arch/arm/mach-at91/gpio.h |  148 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 154 insertions(+), 125 deletions(-)
 create mode 100644 arch/arm/mach-at91/gpio.h

diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 10efccf..c2618c7 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -32,8 +32,9 @@
 #include <driver.h>
 #include <getopt.h>
 
+#include "gpio.h"
+
 #define MAX_GPIO_BANKS		5
-#define MAX_NB_GPIO_PER_BANK	32
 
 static int gpio_banks = 0;
 
@@ -50,16 +51,6 @@ struct at91_gpio_chip {
 
 static struct at91_gpio_chip gpio_chip[MAX_GPIO_BANKS];
 
-static inline unsigned pin_to_bank(unsigned pin)
-{
-	return pin / MAX_NB_GPIO_PER_BANK;
-}
-
-static inline unsigned pin_to_bank_offset(unsigned pin)
-{
-	return pin % MAX_NB_GPIO_PER_BANK;
-}
-
 static inline struct at91_gpio_chip *pin_to_controller(unsigned pin)
 {
 	pin /= MAX_NB_GPIO_PER_BANK;
@@ -69,11 +60,6 @@ static inline struct at91_gpio_chip *pin_to_controller(unsigned pin)
 	return NULL;
 }
 
-static inline unsigned pin_to_mask(unsigned pin)
-{
-	return 1 << pin_to_bank_offset(pin);
-}
-
 /**
  * struct at91_pinctrl_mux_ops - describes an At91 mux ops group
  * on new IP with support for periph C and D the way to mux in
@@ -106,94 +92,6 @@ struct at91_pinctrl_mux_ops {
 	void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
 };
 
-static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
-{
-	__raw_writel(mask, pio + PIO_IDR);
-}
-
-static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
-{
-	__raw_writel(mask, pio + (on ? PIO_PUER : PIO_PUDR));
-}
-
-static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
-{
-	__raw_writel(mask, pio + (on ? PIO_MDER : PIO_MDDR));
-}
-
-static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
-{
-	__raw_writel(mask, pio + PIO_ASR);
-}
-
-static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
-{
-	__raw_writel(mask, pio + PIO_BSR);
-}
-
-static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
-{
-
-	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
-						pio + PIO_ABCDSR1);
-	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
-						pio + PIO_ABCDSR2);
-}
-
-static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
-{
-	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
-						pio + PIO_ABCDSR1);
-	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
-						pio + PIO_ABCDSR2);
-}
-
-static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
-{
-	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
-	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
-}
-
-static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
-{
-	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
-	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
-}
-
-static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
-{
-	__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
-}
-
-static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
-{
-	if (is_on)
-		__raw_writel(mask, pio + PIO_IFSCDR);
-	at91_mux_set_deglitch(pio, mask, is_on);
-}
-
-static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
-				bool is_on, u32 div)
-{
-	if (is_on) {
-		__raw_writel(mask, pio + PIO_IFSCER);
-		__raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
-		__raw_writel(mask, pio + PIO_IFER);
-	} else {
-		__raw_writel(mask, pio + PIO_IFDR);
-	}
-}
-
-static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
-{
-	__raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
-}
-
-static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
-{
-	__raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
-}
-
 #ifdef CONFIG_CMD_AT91MUX
 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
 {
@@ -284,21 +182,6 @@ static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
 	.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
 };
 
-static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
-{
-	__raw_writel(mask, pio + PIO_PDR);
-}
-
-static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask)
-{
-	__raw_writel(mask, pio + PIO_PER);
-}
-
-static void at91_mux_gpio_input(void __iomem *pio, unsigned mask, bool input)
-{
-	__raw_writel(mask, pio + (input ? PIO_ODR : PIO_OER));
-}
-
 int at91_mux_pin(unsigned pin, enum at91_mux mux, int use_pullup)
 {
 	struct at91_gpio_chip *at91_gpio = pin_to_controller(pin);
@@ -398,7 +281,7 @@ int at91_set_gpio_output(unsigned pin, int value)
 		pin_to_bank(pin) + 'A', pin_to_bank_offset(pin), value);
 
 	at91_mux_gpio_input(pio, mask, false);
-	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
+	at91_mux_gpio_set(pio, mask, value);
 	return 0;
 }
 EXPORT_SYMBOL(at91_set_gpio_output);
@@ -643,10 +526,8 @@ static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
 	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
 	void __iomem *pio = at91_gpio->regbase;
 	unsigned mask = 1 << offset;
-	u32 pdsr;
 
-	pdsr = __raw_readl(pio + PIO_PDSR);
-	return (pdsr & mask) != 0;
+	return at91_mux_gpio_get(pio, mask);
 }
 
 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
@@ -655,7 +536,7 @@ static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 	void __iomem *pio = at91_gpio->regbase;
 	unsigned mask = 1 << offset;
 
-	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
+	at91_mux_gpio_set(pio, mask, value);
 }
 
 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
@@ -665,7 +546,7 @@ static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 	void __iomem *pio = at91_gpio->regbase;
 	unsigned mask = 1 << offset;
 
-	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
+	at91_mux_gpio_set(pio, mask, value);
 	__raw_writel(mask, pio + PIO_OER);
 
 	return 0;
diff --git a/arch/arm/mach-at91/gpio.h b/arch/arm/mach-at91/gpio.h
new file mode 100644
index 0000000..d40628b
--- /dev/null
+++ b/arch/arm/mach-at91/gpio.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2 only
+ */
+
+#ifndef __AT91_GPIO_H__
+#define __AT91_GPIO_H__
+
+#ifndef __gpio_init
+#define __gpio_init
+#endif
+
+#define MAX_NB_GPIO_PER_BANK	32
+
+static inline unsigned pin_to_bank(unsigned pin)
+{
+	return pin / MAX_NB_GPIO_PER_BANK;
+}
+
+static inline unsigned pin_to_bank_offset(unsigned pin)
+{
+	return pin % MAX_NB_GPIO_PER_BANK;
+}
+
+static inline unsigned pin_to_mask(unsigned pin)
+{
+	return 1 << pin_to_bank_offset(pin);
+}
+
+static __gpio_init void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(mask, pio + PIO_IDR);
+}
+
+static __gpio_init void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
+{
+	__raw_writel(mask, pio + (on ? PIO_PUER : PIO_PUDR));
+}
+
+static __gpio_init void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
+{
+	__raw_writel(mask, pio + (on ? PIO_MDER : PIO_MDDR));
+}
+
+static __gpio_init void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(mask, pio + PIO_ASR);
+}
+
+static __gpio_init void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(mask, pio + PIO_BSR);
+}
+
+static __gpio_init void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
+{
+
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
+						pio + PIO_ABCDSR1);
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
+						pio + PIO_ABCDSR2);
+}
+
+static __gpio_init void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
+						pio + PIO_ABCDSR1);
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
+						pio + PIO_ABCDSR2);
+}
+
+static __gpio_init void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
+}
+
+static __gpio_init void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
+}
+
+static __gpio_init void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
+{
+	__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
+}
+
+static __gpio_init void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
+{
+	if (is_on)
+		__raw_writel(mask, pio + PIO_IFSCDR);
+	at91_mux_set_deglitch(pio, mask, is_on);
+}
+
+static __gpio_init void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
+				bool is_on, u32 div)
+{
+	if (is_on) {
+		__raw_writel(mask, pio + PIO_IFSCER);
+		__raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
+		__raw_writel(mask, pio + PIO_IFER);
+	} else {
+		__raw_writel(mask, pio + PIO_IFDR);
+	}
+}
+
+static __gpio_init void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
+{
+	__raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
+}
+
+static __gpio_init void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
+}
+
+static __gpio_init void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(mask, pio + PIO_PDR);
+}
+
+static __gpio_init void at91_mux_gpio_enable(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(mask, pio + PIO_PER);
+}
+
+static __gpio_init void at91_mux_gpio_input(void __iomem *pio, unsigned mask, bool input)
+{
+	__raw_writel(mask, pio + (input ? PIO_ODR : PIO_OER));
+}
+
+static __gpio_init void at91_mux_gpio_set(void __iomem *pio, unsigned mask,
+int value)
+{
+	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
+}
+
+static __gpio_init int at91_mux_gpio_get(void __iomem *pio, unsigned mask)
+{
+       u32 pdsr;
+
+       pdsr = __raw_readl(pio + PIO_PDSR);
+       return (pdsr & mask) != 0;
+}
+
+#endif /* __AT91_GPIO_H__ */
-- 
1.7.10.4


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[PATCH 3/5] at91sam926x_lowlevel_init: use pio macro

[Jean-Christophe PLAGNIOL-VILLARD]

this will make the code more readble

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 arch/arm/mach-at91/at91sam926x_lowlevel_init.c |    9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
index b62615e..75b080d 100644
--- a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
@@ -24,6 +24,9 @@
 #include <init.h>
 #include <sizes.h>
 
+#define __gpio_init inline
+#include "gpio.h"
+
 static void inline access_sdram(void)
 {
 	writel(0x00000000, AT91_SDRAM_BASE);
@@ -59,10 +62,10 @@ void __bare_init at91sam926x_lowlevel_init(void *pio, bool is_pio_asr,
 	__raw_writel(cfg.wdt_mr, AT91_BASE_WDT + AT91_WDT_MR);
 
 	/* configure PIOx as EBI0 D[16-31] */
-	__raw_writel(cfg.ebi_pio_pdr, pio + PIO_PDR);
-	__raw_writel(cfg.ebi_pio_ppudr, pio + PIO_PUDR);
+	at91_mux_gpio_disable(pio, cfg.ebi_pio_pdr);
+	at91_mux_set_pullup(pio, cfg.ebi_pio_ppudr, true);
 	if (is_pio_asr)
-		__raw_writel(cfg.ebi_pio_ppudr, pio + PIO_ASR);
+		at91_mux_set_A_periph(pio, cfg.ebi_pio_ppudr);
 
 	at91_sys_write(matrix_csa, cfg.ebi_csa);
 
-- 
1.7.10.4


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[PATCH 4/5] at91sam926x_lowlevel_init: use struct to pass soc config

[Jean-Christophe PLAGNIOL-VILLARD]

this will allow to pass more paraemeter to at91sam926x_lowlevel_init
and drop AT91_BASE_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 arch/arm/mach-at91/at91sam9260_lowlevel_init.c     |   18 ++++++--
 arch/arm/mach-at91/at91sam9261_lowlevel_init.c     |   18 ++++++--
 arch/arm/mach-at91/at91sam9263_lowlevel_init.c     |   18 ++++++--
 arch/arm/mach-at91/at91sam926x_lowlevel_init.c     |   44 ++++++++++----------
 .../mach-at91/include/mach/at91_lowlevel_init.h    |   10 ++++-
 5 files changed, 71 insertions(+), 37 deletions(-)

diff --git a/arch/arm/mach-at91/at91sam9260_lowlevel_init.c b/arch/arm/mach-at91/at91sam9260_lowlevel_init.c
index 875c767..d12572d 100644
--- a/arch/arm/mach-at91/at91sam9260_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91sam9260_lowlevel_init.c
@@ -23,14 +23,24 @@
 #include <init.h>
 #include <sizes.h>
 
+void __bare_init at91sam9260_lowlevel_init(void)
+{
+	struct at91sam926x_lowlevel_cfg cfg;
+
+	cfg.pio = IOMEM(AT91SAM9260_BASE_PIOC);
+	cfg.ebi_pio_is_peripha = false;
+	cfg.matrix_csa = AT91_MATRIX_EBICSA;
+
+	at91sam926x_lowlevel_init(&cfg);
+
+	barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(), 0);
+}
+
 void __naked __bare_init reset(void)
 {
 	common_reset();
 
 	arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16);
 
-	at91sam926x_lowlevel_init(IOMEM(AT91SAM9260_BASE_PIOC), false,
-				  AT91_MATRIX_EBICSA);
-
-	barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(), 0);
+	at91sam9260_lowlevel_init();
 }
diff --git a/arch/arm/mach-at91/at91sam9261_lowlevel_init.c b/arch/arm/mach-at91/at91sam9261_lowlevel_init.c
index beaddc8..35d56b6 100644
--- a/arch/arm/mach-at91/at91sam9261_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91sam9261_lowlevel_init.c
@@ -23,14 +23,24 @@
 #include <init.h>
 #include <sizes.h>
 
+void __bare_init at91sam9261_lowlevel_init(void)
+{
+	struct at91sam926x_lowlevel_cfg cfg;
+
+	cfg.pio = IOMEM(AT91SAM9261_BASE_PIOC);
+	cfg.ebi_pio_is_peripha = false;
+	cfg.matrix_csa = AT91_MATRIX_EBICSA;
+
+	at91sam926x_lowlevel_init(&cfg);
+
+	barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(), 0);
+}
+
 void __naked __bare_init reset(void)
 {
 	common_reset();
 
 	arm_setup_stack(AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 16);
 
-	at91sam926x_lowlevel_init(IOMEM(AT91SAM9261_BASE_PIOC), false,
-				  AT91_MATRIX_EBICSA);
-
-	barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(), 0);
+	at91sam9261_lowlevel_init();
 }
diff --git a/arch/arm/mach-at91/at91sam9263_lowlevel_init.c b/arch/arm/mach-at91/at91sam9263_lowlevel_init.c
index 5102051..07a3ac9 100644
--- a/arch/arm/mach-at91/at91sam9263_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91sam9263_lowlevel_init.c
@@ -23,14 +23,24 @@
 #include <init.h>
 #include <sizes.h>
 
+void __bare_init at91sam9263_lowlevel_init(void)
+{
+	struct at91sam926x_lowlevel_cfg cfg;
+
+	cfg.pio = IOMEM(AT91SAM9263_BASE_PIOD);
+	cfg.ebi_pio_is_peripha = true;
+	cfg.matrix_csa = AT91_MATRIX_EBI0CSA;
+
+	at91sam926x_lowlevel_init(&cfg);
+
+	barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(), 0);
+}
+
 void __naked __bare_init reset(void)
 {
 	common_reset();
 
 	arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE - 16);
 
-	at91sam926x_lowlevel_init(IOMEM(AT91SAM9263_BASE_PIOD), true,
-				  AT91_MATRIX_EBI0CSA);
-
-	barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(), 0);
+	at91sam9263_lowlevel_init();
 }
diff --git a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
index 75b080d..1e3f939 100644
--- a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
@@ -49,34 +49,32 @@ static int inline running_in_sram(void)
 	return addr == 0;
 }
 
-void __bare_init at91sam926x_lowlevel_init(void *pio, bool is_pio_asr,
-					   u32 matrix_csa)
+void __bare_init at91sam926x_lowlevel_init(struct at91sam926x_lowlevel_cfg *cfg)
 {
 	u32 r;
 	int i;
 	int in_sram = running_in_sram();
-	struct at91sam926x_lowlevel_cfg cfg;
 
-	at91sam926x_lowlevel_board_config(&cfg);
+	at91sam926x_lowlevel_board_config(cfg);
 
-	__raw_writel(cfg.wdt_mr, AT91_BASE_WDT + AT91_WDT_MR);
+	__raw_writel(cfg->wdt_mr, AT91_BASE_WDT + AT91_WDT_MR);
 
 	/* configure PIOx as EBI0 D[16-31] */
-	at91_mux_gpio_disable(pio, cfg.ebi_pio_pdr);
-	at91_mux_set_pullup(pio, cfg.ebi_pio_ppudr, true);
-	if (is_pio_asr)
-		at91_mux_set_A_periph(pio, cfg.ebi_pio_ppudr);
+	at91_mux_gpio_disable(cfg->pio, cfg->ebi_pio_pdr);
+	at91_mux_set_pullup(cfg->pio, cfg->ebi_pio_ppudr, true);
+	if (cfg->ebi_pio_is_peripha)
+		at91_mux_set_A_periph(cfg->pio, cfg->ebi_pio_ppudr);
 
-	at91_sys_write(matrix_csa, cfg.ebi_csa);
+	at91_sys_write(cfg->matrix_csa, cfg->ebi_csa);
 
 	/* flash */
-	at91_smc_write(cfg.smc_cs, AT91_SMC_MODE, cfg.smc_mode);
+	at91_smc_write(cfg->smc_cs, AT91_SMC_MODE, cfg->smc_mode);
 
-	at91_smc_write(cfg.smc_cs, AT91_SMC_CYCLE, cfg.smc_cycle);
+	at91_smc_write(cfg->smc_cs, AT91_SMC_CYCLE, cfg->smc_cycle);
 
-	at91_smc_write(cfg.smc_cs, AT91_SMC_PULSE, cfg.smc_pulse);
+	at91_smc_write(cfg->smc_cs, AT91_SMC_PULSE, cfg->smc_pulse);
 
-	at91_smc_write(cfg.smc_cs, AT91_SMC_SETUP, cfg.smc_setup);
+	at91_smc_write(cfg->smc_cs, AT91_SMC_SETUP, cfg->smc_setup);
 
 	/*
 	 * PMC Check if the PLL is already initialized
@@ -88,7 +86,7 @@ void __bare_init at91sam926x_lowlevel_init(void *pio, bool is_pio_asr,
 	/*
 	 * Enable the Main Oscillator
 	 */
-	at91_pmc_write(AT91_CKGR_MOR, cfg.pmc_mor);
+	at91_pmc_write(AT91_CKGR_MOR, cfg->pmc_mor);
 
 	do {
 		r = at91_pmc_read(AT91_PMC_SR);
@@ -97,7 +95,7 @@ void __bare_init at91sam926x_lowlevel_init(void *pio, bool is_pio_asr,
 	/*
 	 * PLLAR: x MHz for PCK
 	 */
-	at91_pmc_write(AT91_CKGR_PLLAR, cfg.pmc_pllar);
+	at91_pmc_write(AT91_CKGR_PLLAR, cfg->pmc_pllar);
 
 	do {
 		r = at91_pmc_read(AT91_PMC_SR);
@@ -106,14 +104,14 @@ void __bare_init at91sam926x_lowlevel_init(void *pio, bool is_pio_asr,
 	/*
 	 * PCK/x = MCK Master Clock from SLOW
 	 */
-	at91_pmc_write(AT91_PMC_MCKR, cfg.pmc_mckr1);
+	at91_pmc_write(AT91_PMC_MCKR, cfg->pmc_mckr1);
 
 	pmc_check_mckrdy();
 
 	/*
 	 * PCK/x = MCK Master Clock from PLLA
 	 */
-	at91_pmc_write(AT91_PMC_MCKR, cfg.pmc_mckr2);
+	at91_pmc_write(AT91_PMC_MCKR, cfg->pmc_mckr2);
 
 	pmc_check_mckrdy();
 
@@ -132,13 +130,13 @@ void __bare_init at91sam926x_lowlevel_init(void *pio, bool is_pio_asr,
 	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
 
 	/* SDRAMC_TR - Refresh Timer register */
-	at91_sys_write(AT91_SDRAMC_TR, cfg.sdrc_tr1);
+	at91_sys_write(AT91_SDRAMC_TR, cfg->sdrc_tr1);
 
 	/* SDRAMC_CR - Configuration register*/
-	at91_sys_write(AT91_SDRAMC_CR, cfg.sdrc_cr);
+	at91_sys_write(AT91_SDRAMC_CR, cfg->sdrc_cr);
 
 	/* Memory Device Type */
-	at91_sys_write(AT91_SDRAMC_MDR, cfg.sdrc_mdr);
+	at91_sys_write(AT91_SDRAMC_MDR, cfg->sdrc_mdr);
 
 	/* SDRAMC_MR : Precharge All */
 	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
@@ -166,13 +164,13 @@ void __bare_init at91sam926x_lowlevel_init(void *pio, bool is_pio_asr,
 	access_sdram();
 
 	/* SDRAMC_TR : Refresh Timer Counter */
-	at91_sys_write(AT91_SDRAMC_TR, cfg.sdrc_tr2);
+	at91_sys_write(AT91_SDRAMC_TR, cfg->sdrc_tr2);
 
 	/* access SDRAM */
 	access_sdram();
 
 	/* User reset enable*/
-	at91_sys_write(AT91_RSTC_MR, cfg.rstc_rmr);
+	at91_sys_write(AT91_RSTC_MR, cfg->rstc_rmr);
 
 #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
 	/* MATRIX_MCFG - REMAP all masters */
diff --git a/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h b/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h
index f8c020b..4f4887e 100644
--- a/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h
+++ b/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h
@@ -8,6 +8,12 @@
 #define __AT91_LOWLEVEL_INIT_H__
 
 struct at91sam926x_lowlevel_cfg {
+	/* SoC specific */
+	void __iomem *pio;
+	u32 ebi_pio_is_peripha;
+	u32 matrix_csa;
+
+	/* board specific */
 	u32 wdt_mr;
 	u32 ebi_pio_pdr;
 	u32 ebi_pio_ppudr;
@@ -30,10 +36,10 @@ struct at91sam926x_lowlevel_cfg {
 
 #ifdef CONFIG_HAVE_AT91_LOWLEVEL_INIT
 void at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg);
-void at91sam926x_lowlevel_init(void *pio, bool is_pio_asr, u32 matrix_csa);
+void at91sam926x_lowlevel_init(struct at91sam926x_lowlevel_cfg *cfg);
 #else
 static inline void at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg) {}
-static inline void at91sam926x_lowlevel_init(void *pio, bool is_pio_asr, u32 matrix_csa) {}
+static inline void at91sam926x_lowlevel_init(struct at91sam926x_lowlevel_cfg *cfg) {}
 #endif
 
 #endif /* __AT91_LOWLEVEL_INIT_H__ */
-- 
1.7.10.4


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[PATCH 5/5] at91sam9: drop AT91_BASE_SYS for sdram controller

[Jean-Christophe PLAGNIOL-VILLARD]

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 arch/arm/boards/tny-a926x/init.c                   |    2 +-
 arch/arm/boards/usb-a926x/init.c                   |    2 +-
 arch/arm/mach-at91/at91sam9260_devices.c           |    2 +-
 arch/arm/mach-at91/at91sam9260_lowlevel_init.c     |    3 +-
 arch/arm/mach-at91/at91sam9261_devices.c           |    2 +-
 arch/arm/mach-at91/at91sam9261_lowlevel_init.c     |    3 +-
 arch/arm/mach-at91/at91sam9263_devices.c           |    2 +-
 arch/arm/mach-at91/at91sam9263_lowlevel_init.c     |    3 +-
 arch/arm/mach-at91/at91sam926x_lowlevel_init.c     |  115 +++++++++++---------
 arch/arm/mach-at91/at91sam9_reset.S                |    4 +-
 .../mach-at91/include/mach/at91_lowlevel_init.h    |    1 +
 arch/arm/mach-at91/include/mach/at91sam9_sdramc.h  |  108 +++++++++++++++---
 12 files changed, 173 insertions(+), 74 deletions(-)

diff --git a/arch/arm/boards/tny-a926x/init.c b/arch/arm/boards/tny-a926x/init.c
index 4228254..5ea6c53 100644
--- a/arch/arm/boards/tny-a926x/init.c
+++ b/arch/arm/boards/tny-a926x/init.c
@@ -202,7 +202,7 @@ static void __init ek_add_device_spi(void)
 			ARRAY_SIZE(tny_a9263_spi_devices));
 		at91_add_device_spi(0, &tny_a9263_spi0_pdata);
 
-	} else if (machine_is_tny_a9g20() && at91_is_low_power_sdram()) {
+	} else if (machine_is_tny_a9g20() && at91sam9260_is_low_power_sdram()) {
 		spi_register_board_info(tny_a9g20_lpw_spi_devices,
 			ARRAY_SIZE(tny_a9g20_lpw_spi_devices));
 		at91_add_device_spi(1, &tny_a9g20_spi1_pdata);
diff --git a/arch/arm/boards/usb-a926x/init.c b/arch/arm/boards/usb-a926x/init.c
index e2da8ea..fd74c8f 100644
--- a/arch/arm/boards/usb-a926x/init.c
+++ b/arch/arm/boards/usb-a926x/init.c
@@ -200,7 +200,7 @@ static void usb_a9260_add_spi(void)
 		spi_register_board_info(usb_a9263_spi_devices,
 				ARRAY_SIZE(usb_a9263_spi_devices));
 		at91_add_device_spi(0, &spi_a9263_pdata);
-	} else if (machine_is_usb_a9g20() && at91_is_low_power_sdram()) {
+	} else if (machine_is_usb_a9g20() && at91sam9260_is_low_power_sdram()) {
 		spi_register_board_info(usb_a9g20_spi_devices,
 				ARRAY_SIZE(usb_a9g20_spi_devices));
 		at91_add_device_spi(1, &spi_a9g20_pdata);
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 6e8c37b..1c375ee 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -27,7 +27,7 @@
 void at91_add_device_sdram(u32 size)
 {
 	if (!size)
-		size = at91_get_sdram_size();
+		size = at91sam9260_get_sdram_size();
 
 	arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
 	if (cpu_is_at91sam9g20()) {
diff --git a/arch/arm/mach-at91/at91sam9260_lowlevel_init.c b/arch/arm/mach-at91/at91sam9260_lowlevel_init.c
index d12572d..4f9a727 100644
--- a/arch/arm/mach-at91/at91sam9260_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91sam9260_lowlevel_init.c
@@ -28,12 +28,13 @@ void __bare_init at91sam9260_lowlevel_init(void)
 	struct at91sam926x_lowlevel_cfg cfg;
 
 	cfg.pio = IOMEM(AT91SAM9260_BASE_PIOC);
+	cfg.sdramc = IOMEM(AT91SAM9260_BASE_SDRAMC);
 	cfg.ebi_pio_is_peripha = false;
 	cfg.matrix_csa = AT91_MATRIX_EBICSA;
 
 	at91sam926x_lowlevel_init(&cfg);
 
-	barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(), 0);
+	barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc), 0);
 }
 
 void __naked __bare_init reset(void)
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index e9ca51c..e3e51bf 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -27,7 +27,7 @@
 void at91_add_device_sdram(u32 size)
 {
 	if (!size)
-		size = at91_get_sdram_size();
+		size = at91sam9261_get_sdram_size();
 
 	arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
 	if (cpu_is_at91sam9g10())
diff --git a/arch/arm/mach-at91/at91sam9261_lowlevel_init.c b/arch/arm/mach-at91/at91sam9261_lowlevel_init.c
index 35d56b6..363193c 100644
--- a/arch/arm/mach-at91/at91sam9261_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91sam9261_lowlevel_init.c
@@ -28,12 +28,13 @@ void __bare_init at91sam9261_lowlevel_init(void)
 	struct at91sam926x_lowlevel_cfg cfg;
 
 	cfg.pio = IOMEM(AT91SAM9261_BASE_PIOC);
+	cfg.sdramc = IOMEM(AT91SAM9261_BASE_SDRAMC);
 	cfg.ebi_pio_is_peripha = false;
 	cfg.matrix_csa = AT91_MATRIX_EBICSA;
 
 	at91sam926x_lowlevel_init(&cfg);
 
-	barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(), 0);
+	barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc), 0);
 }
 
 void __naked __bare_init reset(void)
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 528a07b..f47a5fe 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -26,7 +26,7 @@
 void at91_add_device_sdram(u32 size)
 {
 	if (!size)
-		size = at91_get_sdram_size();
+		size = at91sam9263_get_sdram_size(0);
 
 	arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
 	add_mem_device("sram0", AT91SAM9263_SRAM0_BASE,
diff --git a/arch/arm/mach-at91/at91sam9263_lowlevel_init.c b/arch/arm/mach-at91/at91sam9263_lowlevel_init.c
index 07a3ac9..d17c5c8 100644
--- a/arch/arm/mach-at91/at91sam9263_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91sam9263_lowlevel_init.c
@@ -28,12 +28,13 @@ void __bare_init at91sam9263_lowlevel_init(void)
 	struct at91sam926x_lowlevel_cfg cfg;
 
 	cfg.pio = IOMEM(AT91SAM9263_BASE_PIOD);
+	cfg.sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0);
 	cfg.ebi_pio_is_peripha = true;
 	cfg.matrix_csa = AT91_MATRIX_EBI0CSA;
 
 	at91sam926x_lowlevel_init(&cfg);
 
-	barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(), 0);
+	barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc), 0);
 }
 
 void __naked __bare_init reset(void)
diff --git a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
index 1e3f939..985203a 100644
--- a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
+++ b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c
@@ -49,12 +49,74 @@ static int inline running_in_sram(void)
 	return addr == 0;
 }
 
-void __bare_init at91sam926x_lowlevel_init(struct at91sam926x_lowlevel_cfg *cfg)
+#define at91_sdramc_read(field) \
+	__raw_readl(cfg->sdramc + field)
+
+#define at91_sdramc_write(field, value) \
+	__raw_writel(value, cfg->sdramc + field)
+
+void __bare_init at91sam926x_sdramc_init(struct at91sam926x_lowlevel_cfg *cfg)
 {
 	u32 r;
 	int i;
 	int in_sram = running_in_sram();
 
+	/*
+	 * SDRAMC Check if Refresh Timer Counter is already initialized
+	 */
+	r = at91_sdramc_read(AT91_SDRAMC_TR);
+	if (r && !in_sram)
+		return;
+
+	/* SDRAMC_MR : Normal Mode */
+	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
+
+	/* SDRAMC_TR - Refresh Timer register */
+	at91_sdramc_write(AT91_SDRAMC_TR, cfg->sdrc_tr1);
+
+	/* SDRAMC_CR - Configuration register*/
+	at91_sdramc_write(AT91_SDRAMC_CR, cfg->sdrc_cr);
+
+	/* Memory Device Type */
+	at91_sdramc_write(AT91_SDRAMC_MDR, cfg->sdrc_mdr);
+
+	/* SDRAMC_MR : Precharge All */
+	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
+
+	/* access SDRAM */
+	access_sdram();
+
+	/* SDRAMC_MR : refresh */
+	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);
+
+	/* access SDRAM 8 times */
+	for (i = 0; i < 8; i++)
+		access_sdram();
+
+	/* SDRAMC_MR : Load Mode Register */
+	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);
+
+	/* access SDRAM */
+	access_sdram();
+
+	/* SDRAMC_MR : Normal Mode */
+	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
+
+	/* access SDRAM */
+	access_sdram();
+
+	/* SDRAMC_TR : Refresh Timer Counter */
+	at91_sdramc_write(AT91_SDRAMC_TR, cfg->sdrc_tr2);
+
+	/* access SDRAM */
+	access_sdram();
+}
+
+void __bare_init at91sam926x_lowlevel_init(struct at91sam926x_lowlevel_cfg *cfg)
+{
+	u32 r;
+	int in_sram = running_in_sram();
+
 	at91sam926x_lowlevel_board_config(cfg);
 
 	__raw_writel(cfg->wdt_mr, AT91_BASE_WDT + AT91_WDT_MR);
@@ -118,56 +180,7 @@ void __bare_init at91sam926x_lowlevel_init(struct at91sam926x_lowlevel_cfg *cfg)
 	/*
 	 * Init SDRAM
 	 */
-
-	/*
-	 * SDRAMC Check if Refresh Timer Counter is already initialized
-	 */
-	r = at91_sys_read(AT91_SDRAMC_TR);
-	if (r && !in_sram)
-		return;
-
-	/* SDRAMC_MR : Normal Mode */
-	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
-
-	/* SDRAMC_TR - Refresh Timer register */
-	at91_sys_write(AT91_SDRAMC_TR, cfg->sdrc_tr1);
-
-	/* SDRAMC_CR - Configuration register*/
-	at91_sys_write(AT91_SDRAMC_CR, cfg->sdrc_cr);
-
-	/* Memory Device Type */
-	at91_sys_write(AT91_SDRAMC_MDR, cfg->sdrc_mdr);
-
-	/* SDRAMC_MR : Precharge All */
-	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
-
-	/* access SDRAM */
-	access_sdram();
-
-	/* SDRAMC_MR : refresh */
-	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);
-
-	/* access SDRAM 8 times */
-	for (i = 0; i < 8; i++)
-		access_sdram();
-
-	/* SDRAMC_MR : Load Mode Register */
-	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);
-
-	/* access SDRAM */
-	access_sdram();
-
-	/* SDRAMC_MR : Normal Mode */
-	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
-
-	/* access SDRAM */
-	access_sdram();
-
-	/* SDRAMC_TR : Refresh Timer Counter */
-	at91_sys_write(AT91_SDRAMC_TR, cfg->sdrc_tr2);
-
-	/* access SDRAM */
-	access_sdram();
+	at91sam926x_sdramc_init(cfg);
 
 	/* User reset enable*/
 	at91_sys_write(AT91_RSTC_MR, cfg->rstc_rmr);
diff --git a/arch/arm/mach-at91/at91sam9_reset.S b/arch/arm/mach-at91/at91sam9_reset.S
index 9a0bc0d..3a3e77a 100644
--- a/arch/arm/mach-at91/at91sam9_reset.S
+++ b/arch/arm/mach-at91/at91sam9_reset.S
@@ -31,8 +31,8 @@ reset_cpu:		ldr	r0, .at91_va_base_sdramc			@ preload constants
 
 			.balign	32						@ align to cache line
 
-			str	r2, [r0, #AT91_SDRAMC_TR - AT91_SDRAMC]		@ disable SDRAM access
-			str	r3, [r0, #AT91_SDRAMC_LPR - AT91_SDRAMC]	@ power down SDRAM
+			str	r2, [r0, #AT91_SDRAMC_TR]			@ disable SDRAM access
+			str	r3, [r0, #AT91_SDRAMC_LPR]			@ power down SDRAM
 			str	r4, [r1]					@ reset processor
 
 			b	.
diff --git a/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h b/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h
index 4f4887e..6b37e49 100644
--- a/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h
+++ b/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h
@@ -10,6 +10,7 @@
 struct at91sam926x_lowlevel_cfg {
 	/* SoC specific */
 	void __iomem *pio;
+	void __iomem *sdramc;
 	u32 ebi_pio_is_peripha;
 	u32 matrix_csa;
 
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index 971a772..91efa67 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -18,7 +18,7 @@
 #define AT91SAM9_SDRAMC_H
 
 /* SDRAM Controller (SDRAMC) registers */
-#define AT91_SDRAMC_MR		(AT91_SDRAMC + 0x00)	/* SDRAM Controller Mode Register */
+#define AT91_SDRAMC_MR		0x00	/* SDRAM Controller Mode Register */
 #define		AT91_SDRAMC_MODE	(0xf << 0)		/* Command Mode */
 #define			AT91_SDRAMC_MODE_NORMAL		0
 #define			AT91_SDRAMC_MODE_NOP		1
@@ -28,10 +28,10 @@
 #define			AT91_SDRAMC_MODE_EXT_LMR	5
 #define			AT91_SDRAMC_MODE_DEEP		6
 
-#define AT91_SDRAMC_TR		(AT91_SDRAMC + 0x04)	/* SDRAM Controller Refresh Timer Register */
+#define AT91_SDRAMC_TR		0x04	/* SDRAM Controller Refresh Timer Register */
 #define		AT91_SDRAMC_COUNT	(0xfff << 0)		/* Refresh Timer Counter */
 
-#define AT91_SDRAMC_CR		(AT91_SDRAMC + 0x08)	/* SDRAM Controller Configuration Register */
+#define AT91_SDRAMC_CR		0x08	/* SDRAM Controller Configuration Register */
 #define		AT91_SDRAMC_NC		(3 << 0)		/* Number of Column Bits */
 #define			AT91_SDRAMC_NC_8	(0 << 0)
 #define			AT91_SDRAMC_NC_9	(1 << 0)
@@ -58,7 +58,7 @@
 #define		AT91_SDRAMC_TRAS	(0xf << 24)		/* Active to Precharge Delay */
 #define		AT91_SDRAMC_TXSR	(0xf << 28)		/* Exit Self Refresh to Active Delay */
 
-#define AT91_SDRAMC_LPR		(AT91_SDRAMC + 0x10)	/* SDRAM Controller Low Power Register */
+#define AT91_SDRAMC_LPR		0x10	/* SDRAM Controller Low Power Register */
 #define		AT91_SDRAMC_LPCB		(3 << 0)	/* Low-power Configurations */
 #define			AT91_SDRAMC_LPCB_DISABLE		0
 #define			AT91_SDRAMC_LPCB_SELF_REFRESH		1
@@ -72,25 +72,25 @@
 #define			AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES	(1 << 12)
 #define			AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES	(2 << 12)
 
-#define AT91_SDRAMC_IER		(AT91_SDRAMC + 0x14)	/* SDRAM Controller Interrupt Enable Register */
-#define AT91_SDRAMC_IDR		(AT91_SDRAMC + 0x18)	/* SDRAM Controller Interrupt Disable Register */
-#define AT91_SDRAMC_IMR		(AT91_SDRAMC + 0x1C)	/* SDRAM Controller Interrupt Mask Register */
-#define AT91_SDRAMC_ISR		(AT91_SDRAMC + 0x20)	/* SDRAM Controller Interrupt Status Register */
+#define AT91_SDRAMC_IER		0x14	/* SDRAM Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR		0x18	/* SDRAM Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR		0x1C	/* SDRAM Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR		0x20	/* SDRAM Controller Interrupt Status Register */
 #define		AT91_SDRAMC_RES		(1 << 0)		/* Refresh Error Status */
 
-#define AT91_SDRAMC_MDR		(AT91_SDRAMC + 0x24)	/* SDRAM Memory Device Register */
+#define AT91_SDRAMC_MDR		0x24	/* SDRAM Memory Device Register */
 #define		AT91_SDRAMC_MD		(3 << 0)		/* Memory Device Type */
 #define			AT91_SDRAMC_MD_SDRAM		0
 #define			AT91_SDRAMC_MD_LOW_POWER_SDRAM	1
 
 #ifndef __ASSEMBLY__
 #include <mach/io.h>
-static inline u32 at91_get_sdram_size(void)
+static inline u32 at91_get_sdram_size(void *base)
 {
 	u32 val;
 	u32 size;
 
-	val = at91_sys_read(AT91_SDRAMC_CR);
+	val = __raw_readl(base + AT91_SDRAMC_CR);
 
 	/* Formula:
 	 * size = bank << (col + row + 1);
@@ -111,10 +111,92 @@ static inline u32 at91_get_sdram_size(void)
 	return size;
 }
 
-static inline bool at91_is_low_power_sdram(void)
+
+static inline bool at91_is_low_power_sdram(void *base)
+{
+	return __raw_readl(base + AT91_SDRAMC_MDR) & AT91_SDRAMC_MD_LOW_POWER_SDRAM;
+}
+
+#ifdef CONFIG_SOC_AT91SAM9260
+static inline u32 at91sam9260_get_sdram_size(void)
+{
+	return at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC));
+}
+
+static inline bool at91sam9260_is_low_power_sdram(void)
+{
+	return at91_is_low_power_sdram(IOMEM(AT91SAM9260_BASE_SDRAMC));
+}
+#else
+static inline u32 at91sam9260_get_sdram_size(void)
+{
+	return 0;
+}
+
+static inline bool at91sam9260_is_low_power_sdram(void)
+{
+	return false;
+}
+#endif
+
+#ifdef CONFIG_SOC_AT91SAM9261
+static inline u32 at91sam9261_get_sdram_size(void)
+{
+	return at91_get_sdram_size(IOMEM(AT91SAM9261_BASE_SDRAMC));
+}
+
+static inline bool at91sam9261_is_low_power_sdram(void)
 {
-	return at91_sys_read(AT91_SDRAMC_MDR) & AT91_SDRAMC_MD_LOW_POWER_SDRAM;
+	return at91_is_low_power_sdram(IOMEM(AT91SAM9261_BASE_SDRAMC));
 }
+#else
+static inline u32 at91sam9261_get_sdram_size(void)
+{
+	return 0;
+}
+
+static inline bool at91sam9261_is_low_power_sdram(void)
+{
+	return false;
+}
+#endif
+
+#ifdef CONFIG_SOC_AT91SAM9263
+static inline u32 at91sam9263_get_sdram_size(int bank)
+{
+	switch (bank) {
+	case 0:
+		return at91_get_sdram_size(IOMEM(AT91SAM9263_BASE_SDRAMC0));
+	case 1:
+		return at91_get_sdram_size(IOMEM(AT91SAM9263_BASE_SDRAMC1));
+	default:
+		return 0;
+	}
+}
+
+static inline bool at91sam9263_is_low_power_sdram(int bank)
+{
+	switch (bank) {
+	case 0:
+		return at91_is_low_power_sdram(IOMEM(AT91SAM9263_BASE_SDRAMC0));
+	case 1:
+		return at91_is_low_power_sdram(IOMEM(AT91SAM9263_BASE_SDRAMC1));
+	default:
+		return false;
+	}
+}
+#else
+static inline u32 at91sam9263_get_sdram_size(int bank)
+{
+	return 0;
+}
+
+static inline bool at91sam9263_is_low_power_sdram(void)
+{
+	return false;
+}
+#endif
+
 #endif
 
 #endif
-- 
1.7.10.4


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Re: [PATCH 1/5] usb-a926x: only provide the resource if the driver is enable

[Jean-Christophe PLAGNIOL-VILLARD]

On 16:24 Sun 03 Feb     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> usefull for bootstrap
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> ---
ingore this patch

Best Regards,
J.
>  arch/arm/boards/usb-a926x/init.c |    9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm/boards/usb-a926x/init.c b/arch/arm/boards/usb-a926x/init.c
> index 0383280..e2da8ea 100644
> --- a/arch/arm/boards/usb-a926x/init.c
> +++ b/arch/arm/boards/usb-a926x/init.c
> @@ -246,6 +246,15 @@ static struct at91_udc_data __initdata ek_udc_data = {
>  	.pullup_pin	= -EINVAL,		/* pull-up driven by UDC */
>  };
>  
> +static void usb_a9260_add_device_usb(void)
> +{
> +	at91_add_device_usbh_ohci(&ek_usbh_data);
> +}
> +#else
> +static void usb_a9260_add_device_usb(void) {}
> +#endif
> +
> +#ifdef CONFIG_USB_GADGET_DRIVER_AT91
>  static void __init ek_add_device_udc(void)
>  {
>  	if (machine_is_usb_a9260() || machine_is_usb_a9g20())
> -- 
> 1.7.10.4
> 

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Re: [PATCH 0/5] at91sam926x: drop AT91_BASE_SYS for sdram controller + gpio cleanup

[Jean-Christophe PLAGNIOL-VILLARD]

HI,

	can we ahve this one on master

	this is the a cleanup done with the new arm-entry

Best Regards,
J.
On 16:22 Sun 03 Feb     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> Hi,
> 
> The following changes since commit cd5f8e8aaf808ae19e7c1d2890f90f7de809a2c5:
> 
>   ARM pbl: inline decompress function (2013-02-03 08:27:59 +0800)
> 
> are available in the git repository at:
> 
>   git://git.jcrosoft.org/barebox.git delivery/at91sam926x_lowlevel_arm-entry
> 
> for you to fetch changes up to 453bfddd34c1c0babcd8389d63fd34b1bc764a34:
> 
>   at91sam9: drop AT91_BASE_SYS for sdram controller (2013-02-03 08:49:16 +0800)
> 
> ----------------------------------------------------------------
> Jean-Christophe PLAGNIOL-VILLARD (5):
>       usb-a926x: only provide the resource if the driver is enable
>       at91: gpio: split accessor so we can use them for early init
>       at91sam926x_lowlevel_init: use pio macro
>       at91sam926x_lowlevel_init: use struct to pass soc config
>       at91sam9: drop AT91_BASE_SYS for sdram controller
> 
>  arch/arm/boards/tny-a926x/init.c                     |    2 +-
>  arch/arm/boards/usb-a926x/init.c                     |   11 ++++++++-
>  arch/arm/mach-at91/at91sam9260_devices.c             |    2 +-
>  arch/arm/mach-at91/at91sam9260_lowlevel_init.c       |   19 +++++++++++----
>  arch/arm/mach-at91/at91sam9261_devices.c             |    2 +-
>  arch/arm/mach-at91/at91sam9261_lowlevel_init.c       |   19 +++++++++++----
>  arch/arm/mach-at91/at91sam9263_devices.c             |    2 +-
>  arch/arm/mach-at91/at91sam9263_lowlevel_init.c       |   19 +++++++++++----
>  arch/arm/mach-at91/at91sam926x_lowlevel_init.c       |  152 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----------------------------------------------------
>  arch/arm/mach-at91/at91sam9_reset.S                  |    4 ++--
>  arch/arm/mach-at91/gpio.c                            |  131 +++++----------------------------------------------------------------------------------------------
>  arch/arm/mach-at91/gpio.h                            |  148 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  arch/arm/mach-at91/include/mach/at91_lowlevel_init.h |   11 +++++++--
>  arch/arm/mach-at91/include/mach/at91sam9_sdramc.h    |  108 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----------
>  14 files changed, 402 insertions(+), 228 deletions(-)
>  create mode 100644 arch/arm/mach-at91/gpio.h
> 
> Best Regards,
> J.
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox

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