[PATCH 1/5] trivial: doc: fix typos in mach-arm.dox

[PATCH 1/5] trivial: doc: fix typos in mach-arm.dox

[Josh Cartwright]

Signed-off-by: Josh Cartwright <joshc@eso.teric.us>
---
 arch/arm/mach-arm.dox | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-arm.dox b/arch/arm/mach-arm.dox
index 758df3f..03e39ea 100644
--- a/arch/arm/mach-arm.dox
+++ b/arch/arm/mach-arm.dox
@@ -12,7 +12,7 @@ FIXME
       to: "runtime address != link address". You should only use branches and
       do not refer to fixed data. This implies the use of assembler code only.
 
-The ARM CPU starts at lable \<reset\> in one of the corresponding start-*.S
+The ARM CPU starts at label \<reset\> in one of the corresponding start-*.S
 files. After some basic hardware setup it can call a function
 \<arch_init_lowlevel\> if not disabled. This call is intended to give all
 developers a chance to use a standard reset vector file, but also do some
@@ -47,7 +47,7 @@ Lets call the new MACH new_cpu.
  - add /arch/arm/mach-new_cpu/Makfile
  - add other CPU specific code into /arch/arm/mach-new_cpu/
  - modify /arch/arm/Kconfig
- - modify /arch/arm/Makfile
+ - modify /arch/arm/Makefile
 
 @section mach_arm_architecures Architectures using ARM processors
 For details on specific architectures:
-- 
1.8.1.2



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[PATCH 2/5] defaultenv: fixed mismatched braces in bin/boot

[Josh Cartwright]

Commit 91b563613e5c831998210a2c500ec4d2492a650b ("dhcp: switch to global var
support") introduced global dhcp variables, but there was a typo in the
boot script, with a forgotten open brace.  Fix it.

Signed-off-by: Josh Cartwright <joshc@eso.teric.us>
---
 defaultenv/bin/boot | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/defaultenv/bin/boot b/defaultenv/bin/boot
index c17ccdb..746d30c 100644
--- a/defaultenv/bin/boot
+++ b/defaultenv/bin/boot
@@ -50,7 +50,7 @@ if [ x$ip = xdhcp -o x$ip = "xdhcp-barebox" ]; then
 		if [ x${global.dhcp.bootfile} != x ]; then
 			kernelimage=${global.dhcp.bootfile}
 		fi
-		if [ x$global.dhcp.oftree_file} != x ]; then
+		if [ x${global.dhcp.oftree_file} != x ]; then
 			oftreeimage=${global.dhcp.oftree_file}
 		fi
 	fi
-- 
1.8.1.2



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[PATCH 3/5] ARM: zynq: add driver for Zynq uarts

[Josh Cartwright]

Simple UART driver for Zynq SoCs, based loosely on the u-boot driver.

Signed-off-by: Josh Cartwright <joshc@eso.teric.us>
---
 drivers/serial/Kconfig       |   6 ++
 drivers/serial/Makefile      |   1 +
 drivers/serial/serial_zynq.c | 144 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 151 insertions(+)
 create mode 100644 drivers/serial/serial_zynq.c

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index f61d670..608b616 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -113,4 +113,10 @@ config DRIVER_SERIAL_OMAP4_USBBOOT
 	help
 	  Enable this to get console support over the usb bus used to boot an OMAP4
 
+config DRIVER_SERIAL_ZYNQ
+	bool "driver for Zynq uarts"
+	default n
+	help
+	  Say Y here to get console out support with the Zynq uarts
+
 endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 893e282..883394f 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_DRIVER_SERIAL_ALTERA)		+= serial_altera.o
 obj-$(CONFIG_DRIVER_SERIAL_ALTERA_JTAG)		+= serial_altera_jtag.o
 obj-$(CONFIG_DRIVER_SERIAL_PXA)			+= serial_pxa.o
 obj-$(CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT)	+= serial_omap4_usbboot.o
+obj-$(CONFIG_DRIVER_SERIAL_ZYNQ)		+= serial_zynq.o
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
new file mode 100644
index 0000000..ec93b58
--- /dev/null
+++ b/drivers/serial/serial_zynq.c
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2013 Josh Cartwright
+ *
+ * Based very loosely on u-boot drivers/serial/serial_zynq.c.
+ *
+ * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <io.h>
+#include <init.h>
+#include <driver.h>
+#include <xfuncs.h>
+#include <console.h>
+#include <malloc.h>
+
+#include <linux/clk.h>
+
+#define UART_CR		0x00000000
+#define UART_CR_TXEN	(1<<4)
+#define UART_CR_RXEN	(1<<2)
+#define UART_CR_TXRST	(1<<1)
+#define UART_CR_RXRST	(1<<0)
+
+#define UART_SR		0x0000002C
+#define UART_SR_TXFULL	(1<<4)
+#define UART_SR_TXEMPTY	(1<<3)
+#define UART_SR_RXFULL	(1<<2)
+#define UART_SR_RXEMPTY	(1<<1)
+
+#define UART_FIFO	0x00000030
+
+struct zynq_serial_device {
+	struct console_device cdev;
+	struct clk *clk;
+	void __iomem *regs;
+};
+
+#define to_zynq_device(p) container_of(p, struct zynq_serial_device, cdev)
+
+static void zynq_serial_init_device(struct zynq_serial_device *dev)
+{
+	writel(UART_CR_TXEN | UART_CR_RXEN | UART_CR_TXEN | UART_CR_RXEN,
+	       dev->regs + UART_CR);
+}
+
+static int zynq_serial_tstc(struct console_device *cdev)
+{
+	struct zynq_serial_device *zynq = to_zynq_device(cdev);
+
+	return !(readl(zynq->regs + UART_SR) & UART_SR_RXEMPTY);
+}
+
+static void zynq_serial_putc(struct console_device *cdev, char c)
+{
+	struct zynq_serial_device *zynq = to_zynq_device(cdev);
+
+	while (readl(zynq->regs + UART_SR) & UART_SR_TXFULL);
+
+	writel(c, zynq->regs + UART_FIFO);
+}
+
+static int zynq_serial_getc(struct console_device *cdev)
+{
+	struct zynq_serial_device *zynq = to_zynq_device(cdev);
+
+	return readl(zynq->regs + UART_FIFO);
+}
+
+static void zynq_serial_flush(struct console_device *cdev)
+{
+	struct zynq_serial_device *zynq = to_zynq_device(cdev);
+
+	while (!(readl(zynq->regs + UART_SR) & UART_SR_TXEMPTY));
+}
+
+static int zynq_serial_probe(struct device_d *dev)
+{
+	struct zynq_serial_device *priv;
+	struct console_device *cdev;
+	int err;
+
+	priv = xzalloc(sizeof(*priv));
+	cdev = &priv->cdev;
+
+	priv->regs	= dev_request_mem_region(dev, 0);
+	cdev->dev	= dev;
+	cdev->f_caps	= CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
+	cdev->tstc	= zynq_serial_tstc;
+	cdev->putc	= zynq_serial_putc;
+	cdev->getc	= zynq_serial_getc;
+	cdev->flush	= zynq_serial_flush;
+
+	priv->clk = clk_get(dev, NULL);
+
+	err = clk_enable(priv->clk);
+	if (err) {
+		free(priv);
+		return err;
+	}
+
+	zynq_serial_init_device(priv);
+
+	dev->priv = priv;
+
+	return console_register(cdev);
+}
+
+static void zynq_serial_remove(struct device_d *dev)
+{
+	struct zynq_serial_device *zynq = dev->priv;
+	clk_disable(zynq->clk);
+	free(zynq);
+}
+
+static struct driver_d zynq_serial_driver = {
+	.name	= "zynq_serial",
+	.probe	= zynq_serial_probe,
+	.remove = zynq_serial_remove,
+};
+
+static int zynq_serial_init(void)
+{
+	return platform_driver_register(&zynq_serial_driver);
+}
+console_initcall(zynq_serial_init);
-- 
1.8.1.2



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[PATCH 4/5] ARM: zynq: add support for Zynq 7000 SoC

[Josh Cartwright]

Signed-off-by: Josh Cartwright <joshc@eso.teric.us>
---
 arch/arm/Kconfig                           |   9 +
 arch/arm/mach-zynq/Kconfig                 |   3 +
 arch/arm/mach-zynq/Makefile                |   1 +
 arch/arm/mach-zynq/clocks.c                | 341 +++++++++++++++++++++++++++++
 arch/arm/mach-zynq/include/mach/clkdev.h   |   7 +
 arch/arm/mach-zynq/include/mach/debug_ll.h |  21 ++
 arch/arm/mach-zynq/include/mach/slcr.h     |  26 +++
 arch/arm/mach-zynq/reset.c                 |  28 +++
 8 files changed, 436 insertions(+)
 create mode 100644 arch/arm/mach-zynq/Kconfig
 create mode 100644 arch/arm/mach-zynq/Makefile
 create mode 100644 arch/arm/mach-zynq/clocks.c
 create mode 100644 arch/arm/mach-zynq/include/mach/clkdev.h
 create mode 100644 arch/arm/mach-zynq/include/mach/debug_ll.h
 create mode 100644 arch/arm/mach-zynq/include/mach/slcr.h
 create mode 100644 arch/arm/mach-zynq/reset.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 28332ec..37b7de0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -110,6 +110,14 @@ config ARCH_TEGRA
 	select CPU_ARM926T
 	select HAS_DEBUG_LL
 
+config ARCH_ZYNQ
+	bool "Xilinx Zynq-based boards"
+	select CPU_V7
+	select HAS_DEBUG_LL
+	select CLKDEV_LOOKUP
+	select COMMON_CLK
+	select ARM_SMP_TWD
+
 endchoice
 
 source arch/arm/cpu/Kconfig
@@ -126,6 +134,7 @@ source arch/arm/mach-pxa/Kconfig
 source arch/arm/mach-samsung/Kconfig
 source arch/arm/mach-versatile/Kconfig
 source arch/arm/mach-tegra/Kconfig
+source arch/arm/mach-zynq/Kconfig
 
 config ARM_ASM_UNIFIED
 	bool
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
new file mode 100644
index 0000000..90b17f3
--- /dev/null
+++ b/arch/arm/mach-zynq/Kconfig
@@ -0,0 +1,3 @@
+if ARCH_ZYNQ
+
+endif
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
new file mode 100644
index 0000000..58c62a9
--- /dev/null
+++ b/arch/arm/mach-zynq/Makefile
@@ -0,0 +1 @@
+obj-y	+= reset.o clocks.o
diff --git a/arch/arm/mach-zynq/clocks.c b/arch/arm/mach-zynq/clocks.c
new file mode 100644
index 0000000..1e8ca5a
--- /dev/null
+++ b/arch/arm/mach-zynq/clocks.c
@@ -0,0 +1,341 @@
+/*
+ * Copyright (c) 2013 Josh Cartwright <joshc@eso.teric.us>
+ *
+ * Based on drivers/clk-zynq.c from Linux.
+ *
+ * Copyright (c) 2012 National Instruments
+ *
+ * Josh Cartwright <josh.cartwright@ni.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <common.h>
+#include <init.h>
+#include <malloc.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+
+#include <io.h>
+
+#define ZYNQ_SLCR_BASE	0xF8000000
+
+enum zynq_clks {
+	dummy, ps_clk, arm_pll, ddr_pll, io_pll, uart_clk, uart0, uart1,
+	cpu_clk, cpu_6x4x, cpu_3x2x, cpu_2x, cpu_1x, clks_max
+};
+
+static struct clk *clks[clks_max];
+
+struct zynq_pll_clk {
+	struct clk	clk;
+	void __iomem	*pll_ctrl;
+};
+
+#define to_zynq_pll_clk(c)	container_of(c, struct zynq_pll_clk, clk)
+
+#define PLL_CTRL_FDIV(x)	(((x) >> 12) & 0x7F)
+
+static unsigned long zynq_pll_recalc_rate(struct clk *clk,
+					  unsigned long parent_rate)
+{
+	struct zynq_pll_clk *pll = to_zynq_pll_clk(clk);
+	return parent_rate * PLL_CTRL_FDIV(readl(pll->pll_ctrl));
+}
+
+static struct clk_ops zynq_pll_clk_ops = {
+	.recalc_rate	= zynq_pll_recalc_rate,
+};
+
+static inline struct clk *zynq_pll_clk(const char *name, void __iomem *pll_ctrl)
+{
+	static const char *pll_parent = "ps_clk";
+	struct zynq_pll_clk *pll;
+	int ret;
+
+	pll = xzalloc(sizeof(*pll));
+
+	pll->pll_ctrl		= pll_ctrl;
+	pll->clk.ops		= &zynq_pll_clk_ops;
+	pll->clk.name		= name;
+	pll->clk.parent_names	= &pll_parent;
+	pll->clk.num_parents	= 1;
+
+	ret = clk_register(&pll->clk);
+	if (ret) {
+		free(pll);
+		return ERR_PTR(ret);
+	}
+
+	return &pll->clk;
+}
+
+struct zynq_periph_clk {
+	struct clk	clk;
+	void __iomem	*clk_ctrl;
+};
+
+#define to_zynq_periph_clk(c)	container_of(c, struct zynq_periph_clk, c)
+
+static const u8 periph_clk_parent_map[] = {
+	0, 0, 1, 2
+};
+#define PERIPH_CLK_CTRL_SRC(x)	(periph_clk_parent_map[((x) & 0x30) >> 4])
+#define PERIPH_CLK_CTRL_DIV(x)	(((x) & 0x3F00) >> 8)
+
+static unsigned long zynq_periph_recalc_rate(struct clk *clk,
+					     unsigned long parent_rate)
+{
+	struct zynq_periph_clk *periph = to_zynq_periph_clk(clk);
+	return parent_rate / PERIPH_CLK_CTRL_DIV(readl(periph->clk_ctrl));
+}
+
+static int zynq_periph_get_parent(struct clk *clk)
+{
+	struct zynq_periph_clk *periph = to_zynq_periph_clk(clk);
+	return PERIPH_CLK_CTRL_SRC(readl(periph->clk_ctrl));
+}
+
+static const struct clk_ops zynq_periph_clk_ops = {
+	.recalc_rate	= zynq_periph_recalc_rate,
+	.get_parent	= zynq_periph_get_parent,
+};
+
+static struct clk *zynq_periph_clk(const char *name, void __iomem *clk_ctrl)
+{
+	static const char *peripheral_parents[] = {
+		"io_pll",
+		"arm_pll",
+		"ddr_pll",
+	};
+	struct zynq_periph_clk *periph;
+	int ret;
+
+	periph = xzalloc(sizeof(*periph));
+
+	periph->clk_ctrl	= clk_ctrl;
+	periph->clk.name	= name;
+	periph->clk.ops		= &zynq_periph_clk_ops;
+
+	periph->clk.parent_names = peripheral_parents;
+	periph->clk.num_parents  = ARRAY_SIZE(peripheral_parents);
+
+	ret = clk_register(&periph->clk);
+	if (ret) {
+		free(periph);
+		return ERR_PTR(ret);
+	}
+
+	return &periph->clk;
+}
+
+/* CPU Clock domain is modelled as a mux with 4 children subclks, whose
+ * derivative rates depend on CLK_621_TRUE
+ */
+
+struct zynq_cpu_clk {
+	struct clk		clk;
+	void __iomem		*clk_ctrl;
+};
+
+#define to_zynq_cpu_clk(c)	container_of(c, struct zynq_cpu_clk, c)
+
+static const u8 zynq_cpu_clk_parent_map[] = {
+	1, 1, 2, 0
+};
+#define CPU_CLK_SRCSEL(x)	(zynq_cpu_clk_parent_map[(((x) & 0x30) >> 4)])
+#define CPU_CLK_CTRL_DIV(x)	(((x) & 0x3F00) >> 8)
+
+static unsigned long zynq_cpu_clk_recalc_rate(struct clk *clk,
+					      unsigned long parent_rate)
+{
+	struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(clk);
+	return parent_rate / CPU_CLK_CTRL_DIV(readl(cpuclk->clk_ctrl));
+}
+
+static int zynq_cpu_clk_get_parent(struct clk *clk)
+{
+	struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(clk);
+	return CPU_CLK_SRCSEL(readl(cpuclk->clk_ctrl));
+}
+
+static const struct clk_ops zynq_cpu_clk_ops = {
+	.get_parent	= zynq_cpu_clk_get_parent,
+	.recalc_rate	= zynq_cpu_clk_recalc_rate,
+};
+
+static struct clk *zynq_cpu_clk(const char *name, void __iomem *clk_ctrl)
+{
+	static const char *cpu_parents[] = {
+		"io_pll",
+		"arm_pll",
+		"ddr_pll",
+	};
+	struct zynq_cpu_clk *cpu;
+	int ret;
+
+	cpu = xzalloc(sizeof(*cpu));
+
+	cpu->clk_ctrl		= clk_ctrl;
+	cpu->clk.ops		= &zynq_cpu_clk_ops;
+	cpu->clk.name		= name;
+	cpu->clk.parent_names	= cpu_parents;
+	cpu->clk.num_parents	= ARRAY_SIZE(cpu_parents);
+
+	ret = clk_register(&cpu->clk);
+	if (ret) {
+		free(cpu);
+		return ERR_PTR(ret);
+	}
+
+	return &cpu->clk;
+}
+
+enum zynq_cpu_subclk_which {
+	CPU_SUBCLK_6X4X,
+	CPU_SUBCLK_3X2X,
+	CPU_SUBCLK_2X,
+	CPU_SUBCLK_1X,
+};
+
+struct zynq_cpu_subclk {
+	struct clk	clk;
+	void __iomem	*clk_ctrl;
+	void __iomem	*clk_621;
+	enum zynq_cpu_subclk_which which;
+};
+
+#define CLK_621_TRUE(x)	((x) & 1)
+
+#define to_zynq_cpu_subclk(c)	container_of(c, struct zynq_cpu_subclk, c);
+
+static unsigned long zynq_cpu_subclk_recalc_rate(struct clk *clk,
+						 unsigned long parent_rate)
+{
+	unsigned long uninitialized_var(rate);
+	struct zynq_cpu_subclk *subclk;
+	bool is_621;
+
+	subclk = to_zynq_cpu_subclk(clk)
+	is_621 = CLK_621_TRUE(readl(subclk->clk_621));
+
+	switch (subclk->which) {
+	case CPU_SUBCLK_6X4X:
+		rate = parent_rate;
+		break;
+	case CPU_SUBCLK_3X2X:
+		rate = parent_rate / 2;
+		break;
+	case CPU_SUBCLK_2X:
+		rate = parent_rate / (is_621 ? 3 : 2);
+		break;
+	case CPU_SUBCLK_1X:
+		rate = parent_rate / (is_621 ? 6 : 4);
+		break;
+	};
+
+	return rate;
+}
+
+static int zynq_cpu_subclk_enable(struct clk *clk)
+{
+	struct zynq_cpu_subclk *subclk;
+	u32 tmp;
+
+	subclk = to_zynq_cpu_subclk(clk);
+
+	tmp = readl(subclk->clk_ctrl);
+	tmp |= 1 << (24 + subclk->which);
+	writel(tmp, subclk->clk_ctrl);
+
+	return 0;
+}
+
+static void zynq_cpu_subclk_disable(struct clk *clk)
+{
+	struct zynq_cpu_subclk *subclk;
+	u32 tmp;
+
+	subclk = to_zynq_cpu_subclk(clk);
+
+	tmp = readl(subclk->clk_ctrl);
+	tmp &= ~(1 << (24 + subclk->which));
+	writel(tmp, subclk->clk_ctrl);
+}
+
+static const struct clk_ops zynq_cpu_subclk_ops = {
+	.enable		= zynq_cpu_subclk_enable,
+	.disable	= zynq_cpu_subclk_disable,
+	.recalc_rate	= zynq_cpu_subclk_recalc_rate,
+};
+
+static struct clk *zynq_cpu_subclk(const char *name,
+				   enum zynq_cpu_subclk_which which,
+				   void __iomem *clk_ctrl,
+				   void __iomem *clk_621)
+{
+	static const char *subclk_parent = "cpu_clk";
+	struct zynq_cpu_subclk *subclk;
+	int ret;
+
+	subclk = xzalloc(sizeof(*subclk));
+
+	subclk->clk_ctrl	= clk_ctrl;
+	subclk->clk_621		= clk_621;
+	subclk->which		= which;
+	subclk->clk.name	= name;
+	subclk->clk.ops		= &zynq_cpu_subclk_ops;
+
+	subclk->clk.parent_names	= &subclk_parent;
+	subclk->clk.num_parents		= 1;
+
+	ret = clk_register(&subclk->clk);
+	if (ret) {
+		free(subclk);
+		return ERR_PTR(ret);
+	}
+
+	return &subclk->clk;
+}
+
+static int zynq_init_clks(void)
+{
+	void __iomem *slcr_base = (void __iomem *) ZYNQ_SLCR_BASE;
+
+	request_iomem_region("zynq_slcr", ZYNQ_SLCR_BASE,
+			     ZYNQ_SLCR_BASE + 0x1000);
+
+	clks[ps_clk]  = clk_fixed("ps_clk", CONFIG_ZYNQ_PS_CLK_FREQ);
+
+	clks[arm_pll] = zynq_pll_clk("arm_pll", slcr_base + 0x100);
+	clks[ddr_pll] = zynq_pll_clk("ddr_pll", slcr_base + 0x104);
+	clks[ io_pll] = zynq_pll_clk( "io_pll", slcr_base + 0x108);
+
+	clks[uart_clk] = zynq_periph_clk("uart_clk", slcr_base + 0x154);
+
+	clks[uart0] = clk_gate("uart0", "uart_clk", slcr_base + 0x154, 0);
+	clks[uart1] = clk_gate("uart1", "uart_clk", slcr_base + 0x154, 1);
+
+	clks[cpu_clk] = zynq_cpu_clk("cpu_clk", slcr_base + 0x120);
+
+	clks[cpu_6x4x] = zynq_cpu_subclk("cpu_6x4x", CPU_SUBCLK_6X4X, slcr_base + 0x120, slcr_base + 0x1C4);
+	clks[cpu_3x2x] = zynq_cpu_subclk("cpu_3x2x", CPU_SUBCLK_3X2X, slcr_base + 0x120, slcr_base + 0x1C4);
+	clks[  cpu_2x] = zynq_cpu_subclk(  "cpu_2x",   CPU_SUBCLK_2X, slcr_base + 0x120, slcr_base + 0x1C4);
+	clks[  cpu_1x] = zynq_cpu_subclk(  "cpu_1x",   CPU_SUBCLK_1X, slcr_base + 0x120, slcr_base + 0x1C4);
+
+	clk_register_clkdev(clks[cpu_3x2x], NULL, "smp_twd0");
+	clk_register_clkdev(clks[uart0], NULL, "zynq_serial0");
+	clk_register_clkdev(clks[uart1], NULL, "zynq_serial1");
+	return 0;
+}
+core_initcall(zynq_init_clks);
diff --git a/arch/arm/mach-zynq/include/mach/clkdev.h b/arch/arm/mach-zynq/include/mach/clkdev.h
new file mode 100644
index 0000000..04b37a8
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-zynq/include/mach/debug_ll.h b/arch/arm/mach-zynq/include/mach/debug_ll.h
new file mode 100644
index 0000000..bb180a6
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/debug_ll.h
@@ -0,0 +1,21 @@
+#ifndef __MACH_DEBUG_LL_H__
+#define __MACH_DEBUG_LL_H__
+
+#include <io.h>
+
+#define UART_BASE	0xE0001000
+#define UART_SR		0x0000002C
+#define UART_FIFO	0x00000030
+
+#define UART_SR_TXEMPTY	(1<<3)
+
+static inline void PUTC_LL(char c)
+{
+	void __iomem *base = (void __iomem *) UART_BASE;
+
+	writel(c, base + UART_FIFO);
+
+	while (!(readl(base + UART_SR) & UART_SR_TXEMPTY));
+}
+
+#endif
diff --git a/arch/arm/mach-zynq/include/mach/slcr.h b/arch/arm/mach-zynq/include/mach/slcr.h
new file mode 100644
index 0000000..eada153
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/slcr.h
@@ -0,0 +1,26 @@
+#ifndef __MACH_SLCR_H__
+#define __MACH_SLCR_H__
+
+#include <io.h>
+
+#define SLCR_BASE		0xF8000000
+#define SLCR_LOCK		0x00000004
+#define SLCR_UNLOCK		0x00000008
+#define SLCR_PSS_RST_CTRL	0x00000200
+
+static inline void slcr_write(unsigned long val, unsigned long reg)
+{
+	writel(val, SLCR_BASE + reg);
+}
+
+static inline void slcr_unlock(void)
+{
+	slcr_write(0xDF0D, SLCR_UNLOCK);
+}
+
+static inline void slcr_lock(void)
+{
+	slcr_write(0x767B, SLCR_LOCK);
+}
+
+#endif
diff --git a/arch/arm/mach-zynq/reset.c b/arch/arm/mach-zynq/reset.c
new file mode 100644
index 0000000..8554eca
--- /dev/null
+++ b/arch/arm/mach-zynq/reset.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2013 Josh Cartwright <joshc@eso.teric.us>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <mach/slcr.h>
+
+void __noreturn reset_cpu(unsigned long addr)
+{
+	slcr_unlock();
+	slcr_write(1, SLCR_PSS_RST_CTRL);
+
+	while (1);
+}
-- 
1.8.1.2



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[PATCH 5/5] ARM: zynq: add support for zc702 development board

[Josh Cartwright]

Signed-off-by: Josh Cartwright <joshc@eso.teric.us>
---
 arch/arm/Makefile                     |  2 +
 arch/arm/boards/zynq-zc702/Makefile   |  1 +
 arch/arm/boards/zynq-zc702/config.h   |  0
 arch/arm/boards/zynq-zc702/devices.c  | 70 +++++++++++++++++++++++++++++++++++
 arch/arm/boards/zynq-zc702/lowlevel.c | 28 ++++++++++++++
 arch/arm/mach-zynq/Kconfig            | 19 ++++++++++
 6 files changed, 120 insertions(+)
 create mode 100644 arch/arm/boards/zynq-zc702/Makefile
 create mode 100644 arch/arm/boards/zynq-zc702/config.h
 create mode 100644 arch/arm/boards/zynq-zc702/devices.c
 create mode 100644 arch/arm/boards/zynq-zc702/lowlevel.c

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index fcb2969..9073a55 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -64,6 +64,7 @@ machine-$(CONFIG_ARCH_PXA)		:= pxa
 machine-$(CONFIG_ARCH_SAMSUNG)		:= samsung
 machine-$(CONFIG_ARCH_VERSATILE)	:= versatile
 machine-$(CONFIG_ARCH_TEGRA)		:= tegra
+machine-$(CONFIG_ARCH_ZYNQ)		:= zynq
 
 # Board directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
@@ -157,6 +158,7 @@ board-$(CONFIG_MACH_SABRELITE)			:= freescale-mx6-sabrelite
 board-$(CONFIG_MACH_TX53)			:= karo-tx53
 board-$(CONFIG_MACH_GUF_VINCELL)		:= guf-vincell
 board-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK)		:= efika-mx-smartbook
+board-$(CONFIG_MACH_ZYNQ_ZC702)			:= zynq-zc702
 
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 
diff --git a/arch/arm/boards/zynq-zc702/Makefile b/arch/arm/boards/zynq-zc702/Makefile
new file mode 100644
index 0000000..385bd9f
--- /dev/null
+++ b/arch/arm/boards/zynq-zc702/Makefile
@@ -0,0 +1 @@
+obj-y += lowlevel.o devices.o
diff --git a/arch/arm/boards/zynq-zc702/config.h b/arch/arm/boards/zynq-zc702/config.h
new file mode 100644
index 0000000..e69de29
diff --git a/arch/arm/boards/zynq-zc702/devices.c b/arch/arm/boards/zynq-zc702/devices.c
new file mode 100644
index 0000000..b9ec9f3
--- /dev/null
+++ b/arch/arm/boards/zynq-zc702/devices.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2013 Josh Cartwright <joshc@eso.teric.us>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <common.h>
+#include <driver.h>
+#include <init.h>
+#include <sizes.h>
+
+#include <asm/memory.h>
+
+static struct resource smp_twd_resource = {
+	.name	= "smp_twd_base",
+	.start	= 0xF8F00600,
+	.end	= 0xF8F00610,
+	.flags	= IORESOURCE_MEM,
+};
+
+static struct device_d zynq_smp_twd = {
+	.id		= DEVICE_ID_DYNAMIC,
+	.name		= "smp_twd",
+	.num_resources	= 1,
+	.resource	= &smp_twd_resource,
+};
+
+static struct resource zynq_serial_resource = {
+	.name	= "zynq_serial_base",
+	.start	= 0xE0001000,
+	.end	= 0xE0001048,
+	.flags	= IORESOURCE_MEM,
+};
+
+static struct device_d zynq_serial = {
+	.id		= DEVICE_ID_DYNAMIC,
+	.name		= "zynq_serial",
+	.num_resources	= 1,
+	.resource	= &zynq_serial_resource,
+};
+
+static int zc702_console_init(void)
+{
+	platform_device_register(&zynq_serial);
+	return 0;
+}
+console_initcall(zc702_console_init);
+
+static int zc702_mem_init(void)
+{
+	arm_add_mem_device("ram0", 0, SZ_128M);
+	return 0;
+}
+mem_initcall(zc702_mem_init);
+
+static int zc702_twd_init(void)
+{
+	platform_device_register(&zynq_smp_twd);
+	return 0;
+}
+coredevice_initcall(zc702_twd_init);
diff --git a/arch/arm/boards/zynq-zc702/lowlevel.c b/arch/arm/boards/zynq-zc702/lowlevel.c
new file mode 100644
index 0000000..662d969
--- /dev/null
+++ b/arch/arm/boards/zynq-zc702/lowlevel.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2013 Josh Cartwright <joshc@eso.teric.us>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <common.h>
+#include <init.h>
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+
+#include <mach/slcr.h>
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	slcr_unlock();
+	arm_cpu_lowlevel_init();
+	barebox_arm_entry(0x8000, SZ_128M, 0);
+}
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 90b17f3..992a485 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -1,3 +1,22 @@
 if ARCH_ZYNQ
 
+config ARCH_TEXT_BASE
+	hex
+	default 0x04000000 if MACH_ZYNQ_ZC702
+
+config ZYNQ_PS_CLK_FREQ
+	int
+	default 33333330 if MACH_ZYNQ_ZC702
+
+config BOARDINFO
+	default "Xilinx Zynq zc702 dev board" if MACH_ZYNQ_ZC702
+
+choice
+	prompt "Xilinx Zynq zc702 dev board"
+
+config MACH_ZYNQ_ZC702
+	bool "zc702 development board"
+
+endchoice
+
 endif
-- 
1.8.1.2


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[PATCH 0/5] Zynq support for barebox

[Josh Cartwright]

In San Francisco a couple weeks ago (ELC2013), Thomas Petazzoni
informally mentioned barebox in passing, so I decided to toy with it a
bit...

This patchset adds basic support for the Zynq SoC to barebox.  So far,
it's only been tested as a 'secondary' bootloader (after u-boot).  Also
added is support for the zc702 development board.

The first two patches are simple typos I found getting acclimated to the
barebox source.

Josh Cartwright (5):
  trivial: doc: fix typos in mach-arm.dox
  defaultenv: fixed mismatched braces in bin/boot
  ARM: zynq: add driver for Zynq uarts
  ARM: zynq: add support for Zynq 7000 SoC
  ARM: zynq: add support for zc702 development board

 arch/arm/Kconfig                           |   9 +
 arch/arm/Makefile                          |   2 +
 arch/arm/boards/zynq-zc702/Makefile        |   1 +
 arch/arm/boards/zynq-zc702/config.h        |   0
 arch/arm/boards/zynq-zc702/devices.c       |  70 ++++++
 arch/arm/boards/zynq-zc702/lowlevel.c      |  28 +++
 arch/arm/mach-arm.dox                      |   4 +-
 arch/arm/mach-zynq/Kconfig                 |  22 ++
 arch/arm/mach-zynq/Makefile                |   1 +
 arch/arm/mach-zynq/clocks.c                | 341 +++++++++++++++++++++++++++++
 arch/arm/mach-zynq/include/mach/clkdev.h   |   7 +
 arch/arm/mach-zynq/include/mach/debug_ll.h |  21 ++
 arch/arm/mach-zynq/include/mach/slcr.h     |  26 +++
 arch/arm/mach-zynq/reset.c                 |  28 +++
 defaultenv/bin/boot                        |   2 +-
 drivers/serial/Kconfig                     |   6 +
 drivers/serial/Makefile                    |   1 +
 drivers/serial/serial_zynq.c               | 144 ++++++++++++
 18 files changed, 710 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/boards/zynq-zc702/Makefile
 create mode 100644 arch/arm/boards/zynq-zc702/config.h
 create mode 100644 arch/arm/boards/zynq-zc702/devices.c
 create mode 100644 arch/arm/boards/zynq-zc702/lowlevel.c
 create mode 100644 arch/arm/mach-zynq/Kconfig
 create mode 100644 arch/arm/mach-zynq/Makefile
 create mode 100644 arch/arm/mach-zynq/clocks.c
 create mode 100644 arch/arm/mach-zynq/include/mach/clkdev.h
 create mode 100644 arch/arm/mach-zynq/include/mach/debug_ll.h
 create mode 100644 arch/arm/mach-zynq/include/mach/slcr.h
 create mode 100644 arch/arm/mach-zynq/reset.c
 create mode 100644 drivers/serial/serial_zynq.c

-- 
1.8.1.2


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Re: [PATCH 3/5] ARM: zynq: add driver for Zynq uarts

[Antony Pavlov]

On 3 March 2013 04:48, Josh Cartwright <joshc@eso.teric.us> wrote:
> Simple UART driver for Zynq SoCs, based loosely on the u-boot driver.
>
> Signed-off-by: Josh Cartwright <joshc@eso.teric.us>
> ---
>  drivers/serial/Kconfig       |   6 ++
>  drivers/serial/Makefile      |   1 +
>  drivers/serial/serial_zynq.c | 144 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 151 insertions(+)
>  create mode 100644 drivers/serial/serial_zynq.c
>
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index f61d670..608b616 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -113,4 +113,10 @@ config DRIVER_SERIAL_OMAP4_USBBOOT
>         help
>           Enable this to get console support over the usb bus used to boot an OMAP4
>
> +config DRIVER_SERIAL_ZYNQ
> +       bool "driver for Zynq uarts"
> +       default n
> +       help
> +         Say Y here to get console out support with the Zynq uarts
> +
>  endmenu
> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
> index 893e282..883394f 100644
> --- a/drivers/serial/Makefile
> +++ b/drivers/serial/Makefile
> @@ -21,3 +21,4 @@ obj-$(CONFIG_DRIVER_SERIAL_ALTERA)            += serial_altera.o
>  obj-$(CONFIG_DRIVER_SERIAL_ALTERA_JTAG)                += serial_altera_jtag.o
>  obj-$(CONFIG_DRIVER_SERIAL_PXA)                        += serial_pxa.o
>  obj-$(CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT)      += serial_omap4_usbboot.o
> +obj-$(CONFIG_DRIVER_SERIAL_ZYNQ)               += serial_zynq.o
> diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
> new file mode 100644
> index 0000000..ec93b58
> --- /dev/null
> +++ b/drivers/serial/serial_zynq.c
> @@ -0,0 +1,144 @@
> +/*
> + * (C) Copyright 2013 Josh Cartwright
> + *
> + * Based very loosely on u-boot drivers/serial/serial_zynq.c.
> + *
> + * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
> + * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include <common.h>
> +#include <io.h>
> +#include <init.h>
> +#include <driver.h>
> +#include <xfuncs.h>
> +#include <console.h>
> +#include <malloc.h>
> +
> +#include <linux/clk.h>
> +
> +#define UART_CR                0x00000000
> +#define UART_CR_TXEN   (1<<4)
> +#define UART_CR_RXEN   (1<<2)
> +#define UART_CR_TXRST  (1<<1)
> +#define UART_CR_RXRST  (1<<0)
> +
> +#define UART_SR                0x0000002C
> +#define UART_SR_TXFULL (1<<4)
> +#define UART_SR_TXEMPTY        (1<<3)
> +#define UART_SR_RXFULL (1<<2)
> +#define UART_SR_RXEMPTY        (1<<1)
> +
> +#define UART_FIFO      0x00000030
> +
> +struct zynq_serial_device {
> +       struct console_device cdev;
> +       struct clk *clk;
> +       void __iomem *regs;
> +};
> +
> +#define to_zynq_device(p) container_of(p, struct zynq_serial_device, cdev)
> +
> +static void zynq_serial_init_device(struct zynq_serial_device *dev)
> +{
> +       writel(UART_CR_TXEN | UART_CR_RXEN | UART_CR_TXEN | UART_CR_RXEN,


IMHO there are too many 'UART_CR_TXEN' and 'UART_CR_RXEN' here.


> +              dev->regs + UART_CR);
> +}
> +
> +static int zynq_serial_tstc(struct console_device *cdev)
> +{
> +       struct zynq_serial_device *zynq = to_zynq_device(cdev);
> +
> +       return !(readl(zynq->regs + UART_SR) & UART_SR_RXEMPTY);
> +}
> +
> +static void zynq_serial_putc(struct console_device *cdev, char c)
> +{
> +       struct zynq_serial_device *zynq = to_zynq_device(cdev);
> +
> +       while (readl(zynq->regs + UART_SR) & UART_SR_TXFULL);
> +
> +       writel(c, zynq->regs + UART_FIFO);
> +}
> +
> +static int zynq_serial_getc(struct console_device *cdev)
> +{
> +       struct zynq_serial_device *zynq = to_zynq_device(cdev);
> +
> +       return readl(zynq->regs + UART_FIFO);
> +}
> +
> +static void zynq_serial_flush(struct console_device *cdev)
> +{
> +       struct zynq_serial_device *zynq = to_zynq_device(cdev);
> +
> +       while (!(readl(zynq->regs + UART_SR) & UART_SR_TXEMPTY));
> +}
> +
> +static int zynq_serial_probe(struct device_d *dev)
> +{
> +       struct zynq_serial_device *priv;
> +       struct console_device *cdev;
> +       int err;
> +
> +       priv = xzalloc(sizeof(*priv));
> +       cdev = &priv->cdev;
> +
> +       priv->regs      = dev_request_mem_region(dev, 0);
> +       cdev->dev       = dev;
> +       cdev->f_caps    = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
> +       cdev->tstc      = zynq_serial_tstc;
> +       cdev->putc      = zynq_serial_putc;
> +       cdev->getc      = zynq_serial_getc;
> +       cdev->flush     = zynq_serial_flush;
> +
> +       priv->clk = clk_get(dev, NULL);
> +
> +       err = clk_enable(priv->clk);
> +       if (err) {
> +               free(priv);
> +               return err;
> +       }
> +
> +       zynq_serial_init_device(priv);
> +
> +       dev->priv = priv;
> +
> +       return console_register(cdev);
> +}
> +
> +static void zynq_serial_remove(struct device_d *dev)
> +{
> +       struct zynq_serial_device *zynq = dev->priv;
> +       clk_disable(zynq->clk);
> +       free(zynq);
> +}
> +
> +static struct driver_d zynq_serial_driver = {
> +       .name   = "zynq_serial",
> +       .probe  = zynq_serial_probe,
> +       .remove = zynq_serial_remove,
> +};
> +
> +static int zynq_serial_init(void)
> +{
> +       return platform_driver_register(&zynq_serial_driver);
> +}
> +console_initcall(zynq_serial_init);
> --
> 1.8.1.2
>
>
>
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-- 
Best regards,
  Antony Pavlov

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Re: [PATCH 4/5] ARM: zynq: add support for Zynq 7000 SoC

[Antony Pavlov]

On 3 March 2013 04:48, Josh Cartwright <joshc@eso.teric.us> wrote:
> Signed-off-by: Josh Cartwright <joshc@eso.teric.us>
> ---
>  arch/arm/Kconfig                           |   9 +
>  arch/arm/mach-zynq/Kconfig                 |   3 +
>  arch/arm/mach-zynq/Makefile                |   1 +
>  arch/arm/mach-zynq/clocks.c                | 341 +++++++++++++++++++++++++++++
>  arch/arm/mach-zynq/include/mach/clkdev.h   |   7 +
>  arch/arm/mach-zynq/include/mach/debug_ll.h |  21 ++
>  arch/arm/mach-zynq/include/mach/slcr.h     |  26 +++
>  arch/arm/mach-zynq/reset.c                 |  28 +++
>  8 files changed, 436 insertions(+)
>  create mode 100644 arch/arm/mach-zynq/Kconfig
>  create mode 100644 arch/arm/mach-zynq/Makefile
>  create mode 100644 arch/arm/mach-zynq/clocks.c
>  create mode 100644 arch/arm/mach-zynq/include/mach/clkdev.h
>  create mode 100644 arch/arm/mach-zynq/include/mach/debug_ll.h
>  create mode 100644 arch/arm/mach-zynq/include/mach/slcr.h
>  create mode 100644 arch/arm/mach-zynq/reset.c
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 28332ec..37b7de0 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -110,6 +110,14 @@ config ARCH_TEGRA
>         select CPU_ARM926T
>         select HAS_DEBUG_LL
>
> +config ARCH_ZYNQ
> +       bool "Xilinx Zynq-based boards"
> +       select CPU_V7
> +       select HAS_DEBUG_LL
> +       select CLKDEV_LOOKUP
> +       select COMMON_CLK
> +       select ARM_SMP_TWD
> +
>  endchoice
>
>  source arch/arm/cpu/Kconfig
> @@ -126,6 +134,7 @@ source arch/arm/mach-pxa/Kconfig
>  source arch/arm/mach-samsung/Kconfig
>  source arch/arm/mach-versatile/Kconfig
>  source arch/arm/mach-tegra/Kconfig
> +source arch/arm/mach-zynq/Kconfig
>
>  config ARM_ASM_UNIFIED
>         bool
> diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
> new file mode 100644
> index 0000000..90b17f3
> --- /dev/null
> +++ b/arch/arm/mach-zynq/Kconfig
> @@ -0,0 +1,3 @@
> +if ARCH_ZYNQ
> +
> +endif
> diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
> new file mode 100644
> index 0000000..58c62a9
> --- /dev/null
> +++ b/arch/arm/mach-zynq/Makefile
> @@ -0,0 +1 @@
> +obj-y  += reset.o clocks.o
> diff --git a/arch/arm/mach-zynq/clocks.c b/arch/arm/mach-zynq/clocks.c
> new file mode 100644
> index 0000000..1e8ca5a
> --- /dev/null
> +++ b/arch/arm/mach-zynq/clocks.c
> @@ -0,0 +1,341 @@
> +/*
> + * Copyright (c) 2013 Josh Cartwright <joshc@eso.teric.us>
> + *
> + * Based on drivers/clk-zynq.c from Linux.
> + *
> + * Copyright (c) 2012 National Instruments
> + *
> + * Josh Cartwright <josh.cartwright@ni.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include <common.h>
> +#include <init.h>
> +#include <malloc.h>
> +#include <linux/clk.h>
> +#include <linux/clkdev.h>
> +#include <linux/err.h>
> +
> +#include <io.h>
> +
> +#define ZYNQ_SLCR_BASE 0xF8000000
> +
> +enum zynq_clks {
> +       dummy, ps_clk, arm_pll, ddr_pll, io_pll, uart_clk, uart0, uart1,
> +       cpu_clk, cpu_6x4x, cpu_3x2x, cpu_2x, cpu_1x, clks_max
> +};
> +
> +static struct clk *clks[clks_max];
> +
> +struct zynq_pll_clk {
> +       struct clk      clk;
> +       void __iomem    *pll_ctrl;
> +};
> +
> +#define to_zynq_pll_clk(c)     container_of(c, struct zynq_pll_clk, clk)
> +
> +#define PLL_CTRL_FDIV(x)       (((x) >> 12) & 0x7F)
> +
> +static unsigned long zynq_pll_recalc_rate(struct clk *clk,
> +                                         unsigned long parent_rate)
> +{
> +       struct zynq_pll_clk *pll = to_zynq_pll_clk(clk);
> +       return parent_rate * PLL_CTRL_FDIV(readl(pll->pll_ctrl));
> +}
> +
> +static struct clk_ops zynq_pll_clk_ops = {
> +       .recalc_rate    = zynq_pll_recalc_rate,
> +};
> +
> +static inline struct clk *zynq_pll_clk(const char *name, void __iomem *pll_ctrl)
> +{
> +       static const char *pll_parent = "ps_clk";
> +       struct zynq_pll_clk *pll;
> +       int ret;
> +
> +       pll = xzalloc(sizeof(*pll));
> +
> +       pll->pll_ctrl           = pll_ctrl;
> +       pll->clk.ops            = &zynq_pll_clk_ops;
> +       pll->clk.name           = name;
> +       pll->clk.parent_names   = &pll_parent;
> +       pll->clk.num_parents    = 1;
> +
> +       ret = clk_register(&pll->clk);
> +       if (ret) {
> +               free(pll);
> +               return ERR_PTR(ret);
> +       }
> +
> +       return &pll->clk;
> +}
> +
> +struct zynq_periph_clk {
> +       struct clk      clk;
> +       void __iomem    *clk_ctrl;
> +};
> +
> +#define to_zynq_periph_clk(c)  container_of(c, struct zynq_periph_clk, c)
> +
> +static const u8 periph_clk_parent_map[] = {
> +       0, 0, 1, 2
> +};
> +#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x) & 0x30) >> 4])
> +#define PERIPH_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8)
> +
> +static unsigned long zynq_periph_recalc_rate(struct clk *clk,
> +                                            unsigned long parent_rate)
> +{
> +       struct zynq_periph_clk *periph = to_zynq_periph_clk(clk);
> +       return parent_rate / PERIPH_CLK_CTRL_DIV(readl(periph->clk_ctrl));
> +}
> +
> +static int zynq_periph_get_parent(struct clk *clk)
> +{
> +       struct zynq_periph_clk *periph = to_zynq_periph_clk(clk);
> +       return PERIPH_CLK_CTRL_SRC(readl(periph->clk_ctrl));
> +}
> +
> +static const struct clk_ops zynq_periph_clk_ops = {
> +       .recalc_rate    = zynq_periph_recalc_rate,
> +       .get_parent     = zynq_periph_get_parent,
> +};
> +
> +static struct clk *zynq_periph_clk(const char *name, void __iomem *clk_ctrl)
> +{
> +       static const char *peripheral_parents[] = {
> +               "io_pll",
> +               "arm_pll",
> +               "ddr_pll",
> +       };
> +       struct zynq_periph_clk *periph;
> +       int ret;
> +
> +       periph = xzalloc(sizeof(*periph));
> +
> +       periph->clk_ctrl        = clk_ctrl;
> +       periph->clk.name        = name;
> +       periph->clk.ops         = &zynq_periph_clk_ops;
> +
> +       periph->clk.parent_names = peripheral_parents;
> +       periph->clk.num_parents  = ARRAY_SIZE(peripheral_parents);
> +
> +       ret = clk_register(&periph->clk);
> +       if (ret) {
> +               free(periph);
> +               return ERR_PTR(ret);
> +       }
> +
> +       return &periph->clk;
> +}
> +
> +/* CPU Clock domain is modelled as a mux with 4 children subclks, whose
> + * derivative rates depend on CLK_621_TRUE
> + */
> +
> +struct zynq_cpu_clk {
> +       struct clk              clk;
> +       void __iomem            *clk_ctrl;
> +};
> +
> +#define to_zynq_cpu_clk(c)     container_of(c, struct zynq_cpu_clk, c)
> +
> +static const u8 zynq_cpu_clk_parent_map[] = {
> +       1, 1, 2, 0
> +};
> +#define CPU_CLK_SRCSEL(x)      (zynq_cpu_clk_parent_map[(((x) & 0x30) >> 4)])
> +#define CPU_CLK_CTRL_DIV(x)    (((x) & 0x3F00) >> 8)
> +
> +static unsigned long zynq_cpu_clk_recalc_rate(struct clk *clk,
> +                                             unsigned long parent_rate)
> +{
> +       struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(clk);
> +       return parent_rate / CPU_CLK_CTRL_DIV(readl(cpuclk->clk_ctrl));
> +}
> +
> +static int zynq_cpu_clk_get_parent(struct clk *clk)
> +{
> +       struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(clk);
> +       return CPU_CLK_SRCSEL(readl(cpuclk->clk_ctrl));
> +}
> +
> +static const struct clk_ops zynq_cpu_clk_ops = {
> +       .get_parent     = zynq_cpu_clk_get_parent,
> +       .recalc_rate    = zynq_cpu_clk_recalc_rate,
> +};
> +
> +static struct clk *zynq_cpu_clk(const char *name, void __iomem *clk_ctrl)
> +{
> +       static const char *cpu_parents[] = {
> +               "io_pll",
> +               "arm_pll",
> +               "ddr_pll",
> +       };
> +       struct zynq_cpu_clk *cpu;
> +       int ret;
> +
> +       cpu = xzalloc(sizeof(*cpu));
> +
> +       cpu->clk_ctrl           = clk_ctrl;
> +       cpu->clk.ops            = &zynq_cpu_clk_ops;
> +       cpu->clk.name           = name;
> +       cpu->clk.parent_names   = cpu_parents;
> +       cpu->clk.num_parents    = ARRAY_SIZE(cpu_parents);
> +
> +       ret = clk_register(&cpu->clk);
> +       if (ret) {
> +               free(cpu);
> +               return ERR_PTR(ret);
> +       }
> +
> +       return &cpu->clk;
> +}
> +
> +enum zynq_cpu_subclk_which {
> +       CPU_SUBCLK_6X4X,
> +       CPU_SUBCLK_3X2X,
> +       CPU_SUBCLK_2X,
> +       CPU_SUBCLK_1X,
> +};
> +
> +struct zynq_cpu_subclk {
> +       struct clk      clk;
> +       void __iomem    *clk_ctrl;
> +       void __iomem    *clk_621;
> +       enum zynq_cpu_subclk_which which;
> +};
> +
> +#define CLK_621_TRUE(x)        ((x) & 1)
> +
> +#define to_zynq_cpu_subclk(c)  container_of(c, struct zynq_cpu_subclk, c);
> +
> +static unsigned long zynq_cpu_subclk_recalc_rate(struct clk *clk,
> +                                                unsigned long parent_rate)
> +{
> +       unsigned long uninitialized_var(rate);
> +       struct zynq_cpu_subclk *subclk;
> +       bool is_621;
> +
> +       subclk = to_zynq_cpu_subclk(clk)
> +       is_621 = CLK_621_TRUE(readl(subclk->clk_621));
> +
> +       switch (subclk->which) {
> +       case CPU_SUBCLK_6X4X:
> +               rate = parent_rate;
> +               break;
> +       case CPU_SUBCLK_3X2X:
> +               rate = parent_rate / 2;
> +               break;
> +       case CPU_SUBCLK_2X:
> +               rate = parent_rate / (is_621 ? 3 : 2);
> +               break;
> +       case CPU_SUBCLK_1X:
> +               rate = parent_rate / (is_621 ? 6 : 4);
> +               break;
> +       };
> +
> +       return rate;
> +}
> +
> +static int zynq_cpu_subclk_enable(struct clk *clk)
> +{
> +       struct zynq_cpu_subclk *subclk;
> +       u32 tmp;
> +
> +       subclk = to_zynq_cpu_subclk(clk);
> +
> +       tmp = readl(subclk->clk_ctrl);
> +       tmp |= 1 << (24 + subclk->which);
> +       writel(tmp, subclk->clk_ctrl);
> +
> +       return 0;
> +}
> +
> +static void zynq_cpu_subclk_disable(struct clk *clk)
> +{
> +       struct zynq_cpu_subclk *subclk;
> +       u32 tmp;
> +
> +       subclk = to_zynq_cpu_subclk(clk);
> +
> +       tmp = readl(subclk->clk_ctrl);
> +       tmp &= ~(1 << (24 + subclk->which));
> +       writel(tmp, subclk->clk_ctrl);
> +}
> +
> +static const struct clk_ops zynq_cpu_subclk_ops = {
> +       .enable         = zynq_cpu_subclk_enable,
> +       .disable        = zynq_cpu_subclk_disable,
> +       .recalc_rate    = zynq_cpu_subclk_recalc_rate,
> +};
> +
> +static struct clk *zynq_cpu_subclk(const char *name,
> +                                  enum zynq_cpu_subclk_which which,
> +                                  void __iomem *clk_ctrl,
> +                                  void __iomem *clk_621)
> +{
> +       static const char *subclk_parent = "cpu_clk";
> +       struct zynq_cpu_subclk *subclk;
> +       int ret;
> +
> +       subclk = xzalloc(sizeof(*subclk));
> +
> +       subclk->clk_ctrl        = clk_ctrl;
> +       subclk->clk_621         = clk_621;
> +       subclk->which           = which;
> +       subclk->clk.name        = name;
> +       subclk->clk.ops         = &zynq_cpu_subclk_ops;
> +
> +       subclk->clk.parent_names        = &subclk_parent;
> +       subclk->clk.num_parents         = 1;
> +
> +       ret = clk_register(&subclk->clk);
> +       if (ret) {
> +               free(subclk);
> +               return ERR_PTR(ret);
> +       }
> +
> +       return &subclk->clk;
> +}
> +
> +static int zynq_init_clks(void)
> +{
> +       void __iomem *slcr_base = (void __iomem *) ZYNQ_SLCR_BASE;
> +
> +       request_iomem_region("zynq_slcr", ZYNQ_SLCR_BASE,
> +                            ZYNQ_SLCR_BASE + 0x1000);
> +
> +       clks[ps_clk]  = clk_fixed("ps_clk", CONFIG_ZYNQ_PS_CLK_FREQ);
> +
> +       clks[arm_pll] = zynq_pll_clk("arm_pll", slcr_base + 0x100);
> +       clks[ddr_pll] = zynq_pll_clk("ddr_pll", slcr_base + 0x104);
> +       clks[ io_pll] = zynq_pll_clk( "io_pll", slcr_base + 0x108);
> +
> +       clks[uart_clk] = zynq_periph_clk("uart_clk", slcr_base + 0x154);
> +
> +       clks[uart0] = clk_gate("uart0", "uart_clk", slcr_base + 0x154, 0);
> +       clks[uart1] = clk_gate("uart1", "uart_clk", slcr_base + 0x154, 1);
> +
> +       clks[cpu_clk] = zynq_cpu_clk("cpu_clk", slcr_base + 0x120);
> +
> +       clks[cpu_6x4x] = zynq_cpu_subclk("cpu_6x4x", CPU_SUBCLK_6X4X, slcr_base + 0x120, slcr_base + 0x1C4);
> +       clks[cpu_3x2x] = zynq_cpu_subclk("cpu_3x2x", CPU_SUBCLK_3X2X, slcr_base + 0x120, slcr_base + 0x1C4);
> +       clks[  cpu_2x] = zynq_cpu_subclk(  "cpu_2x",   CPU_SUBCLK_2X, slcr_base + 0x120, slcr_base + 0x1C4);
> +       clks[  cpu_1x] = zynq_cpu_subclk(  "cpu_1x",   CPU_SUBCLK_1X, slcr_base + 0x120, slcr_base + 0x1C4);
> +
> +       clk_register_clkdev(clks[cpu_3x2x], NULL, "smp_twd0");
> +       clk_register_clkdev(clks[uart0], NULL, "zynq_serial0");
> +       clk_register_clkdev(clks[uart1], NULL, "zynq_serial1");
> +       return 0;
> +}
> +core_initcall(zynq_init_clks);
> diff --git a/arch/arm/mach-zynq/include/mach/clkdev.h b/arch/arm/mach-zynq/include/mach/clkdev.h
> new file mode 100644
> index 0000000..04b37a8
> --- /dev/null
> +++ b/arch/arm/mach-zynq/include/mach/clkdev.h
> @@ -0,0 +1,7 @@
> +#ifndef __ASM_MACH_CLKDEV_H
> +#define __ASM_MACH_CLKDEV_H
> +
> +#define __clk_get(clk) ({ 1; })
> +#define __clk_put(clk) do { } while (0)
> +
> +#endif
> diff --git a/arch/arm/mach-zynq/include/mach/debug_ll.h b/arch/arm/mach-zynq/include/mach/debug_ll.h
> new file mode 100644
> index 0000000..bb180a6
> --- /dev/null
> +++ b/arch/arm/mach-zynq/include/mach/debug_ll.h
> @@ -0,0 +1,21 @@
> +#ifndef __MACH_DEBUG_LL_H__
> +#define __MACH_DEBUG_LL_H__
> +
> +#include <io.h>
> +
> +#define UART_BASE      0xE0001000
> +#define UART_SR                0x0000002C
> +#define UART_FIFO      0x00000030
> +
> +#define UART_SR_TXEMPTY        (1<<3)
> +
> +static inline void PUTC_LL(char c)
> +{
> +       void __iomem *base = (void __iomem *) UART_BASE;
> +
> +       writel(c, base + UART_FIFO);
> +
> +       while (!(readl(base + UART_SR) & UART_SR_TXEMPTY));
> +}
> +
> +#endif
> diff --git a/arch/arm/mach-zynq/include/mach/slcr.h b/arch/arm/mach-zynq/include/mach/slcr.h
> new file mode 100644
> index 0000000..eada153
> --- /dev/null
> +++ b/arch/arm/mach-zynq/include/mach/slcr.h
> @@ -0,0 +1,26 @@
> +#ifndef __MACH_SLCR_H__
> +#define __MACH_SLCR_H__
> +
> +#include <io.h>
> +
> +#define SLCR_BASE              0xF8000000
> +#define SLCR_LOCK              0x00000004
> +#define SLCR_UNLOCK            0x00000008
> +#define SLCR_PSS_RST_CTRL      0x00000200
> +
> +static inline void slcr_write(unsigned long val, unsigned long reg)
> +{
> +       writel(val, SLCR_BASE + reg);
> +}
> +
> +static inline void slcr_unlock(void)
> +{
> +       slcr_write(0xDF0D, SLCR_UNLOCK);
> +}
> +
> +static inline void slcr_lock(void)
> +{
> +       slcr_write(0x767B, SLCR_LOCK);
> +}
> +
> +#endif
> diff --git a/arch/arm/mach-zynq/reset.c b/arch/arm/mach-zynq/reset.c
> new file mode 100644
> index 0000000..8554eca
> --- /dev/null
> +++ b/arch/arm/mach-zynq/reset.c
> @@ -0,0 +1,28 @@
> +/*
> + * Copyright (C) 2013 Josh Cartwright <joshc@eso.teric.us>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA

Please drop the address of the FSF.

See this

commit 77322aa896895f4f68501a071086e432e575dcc2
Author: Sascha Hauer <s.hauer@pengutronix.de>
Date:   Tue Jul 31 09:51:20 2012 +0200

    Treewide: remove address of the Free Software Foundation

    The FSF address has changed in the past. Instead of updating it
    each time the address changes, just drop it completely treewide.


> + */
> +#include <common.h>
> +#include <mach/slcr.h>
> +
> +void __noreturn reset_cpu(unsigned long addr)
> +{
> +       slcr_unlock();
> +       slcr_write(1, SLCR_PSS_RST_CTRL);
> +
> +       while (1);
> +}
> --
> 1.8.1.2
>
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox



-- 
Best regards,
  Antony Pavlov

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Re: [PATCH 3/5] ARM: zynq: add driver for Zynq uarts

[Jean-Christophe PLAGNIOL-VILLARD]

On 18:48 Sat 02 Mar     , Josh Cartwright wrote:
> 
> Simple UART driver for Zynq SoCs, based loosely on the u-boot driver.
> 
> Signed-off-by: Josh Cartwright <joshc@eso.teric.us>
> ---
>  drivers/serial/Kconfig       |   6 ++
>  drivers/serial/Makefile      |   1 +
>  drivers/serial/serial_zynq.c | 144 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 151 insertions(+)
>  create mode 100644 drivers/serial/serial_zynq.c
> 
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index f61d670..608b616 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -113,4 +113,10 @@ config DRIVER_SERIAL_OMAP4_USBBOOT
>  	help
>  	  Enable this to get console support over the usb bus used to boot an OMAP4
>  
> +config DRIVER_SERIAL_ZYNQ
> +	bool "driver for Zynq uarts"
> +	default n
> +	help
> +	  Say Y here to get console out support with the Zynq uarts
> +
>  endmenu
> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
> index 893e282..883394f 100644
> --- a/drivers/serial/Makefile
> +++ b/drivers/serial/Makefile
> @@ -21,3 +21,4 @@ obj-$(CONFIG_DRIVER_SERIAL_ALTERA)		+= serial_altera.o
>  obj-$(CONFIG_DRIVER_SERIAL_ALTERA_JTAG)		+= serial_altera_jtag.o
>  obj-$(CONFIG_DRIVER_SERIAL_PXA)			+= serial_pxa.o
>  obj-$(CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT)	+= serial_omap4_usbboot.o
> +obj-$(CONFIG_DRIVER_SERIAL_ZYNQ)		+= serial_zynq.o
> diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
> new file mode 100644
> index 0000000..ec93b58
> --- /dev/null
> +++ b/drivers/serial/serial_zynq.c
> @@ -0,0 +1,144 @@
> +/*
> + * (C) Copyright 2013 Josh Cartwright
> + *
> + * Based very loosely on u-boot drivers/serial/serial_zynq.c.
> + *
> + * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
> + * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include <common.h>
> +#include <io.h>
> +#include <init.h>
> +#include <driver.h>
> +#include <xfuncs.h>
> +#include <console.h>
> +#include <malloc.h>
> +
> +#include <linux/clk.h>
> +
> +#define UART_CR		0x00000000
> +#define UART_CR_TXEN	(1<<4)
> +#define UART_CR_RXEN	(1<<2)
> +#define UART_CR_TXRST	(1<<1)
> +#define UART_CR_RXRST	(1<<0)
> +
> +#define UART_SR		0x0000002C
> +#define UART_SR_TXFULL	(1<<4)
> +#define UART_SR_TXEMPTY	(1<<3)
> +#define UART_SR_RXFULL	(1<<2)
> +#define UART_SR_RXEMPTY	(1<<1)
> +
> +#define UART_FIFO	0x00000030
> +
> +struct zynq_serial_device {
> +	struct console_device cdev;
> +	struct clk *clk;
> +	void __iomem *regs;
> +};
> +
> +#define to_zynq_device(p) container_of(p, struct zynq_serial_device, cdev)
> +
> +static void zynq_serial_init_device(struct zynq_serial_device *dev)
> +{
> +	writel(UART_CR_TXEN | UART_CR_RXEN | UART_CR_TXEN | UART_CR_RXEN,
> +	       dev->regs + UART_CR);
> +}
> +
> +static int zynq_serial_tstc(struct console_device *cdev)
> +{
> +	struct zynq_serial_device *zynq = to_zynq_device(cdev);
> +
> +	return !(readl(zynq->regs + UART_SR) & UART_SR_RXEMPTY);
> +}
> +
> +static void zynq_serial_putc(struct console_device *cdev, char c)
> +{
> +	struct zynq_serial_device *zynq = to_zynq_device(cdev);
> +
> +	while (readl(zynq->regs + UART_SR) & UART_SR_TXFULL);
> +
> +	writel(c, zynq->regs + UART_FIFO);
> +}
> +
> +static int zynq_serial_getc(struct console_device *cdev)
> +{
> +	struct zynq_serial_device *zynq = to_zynq_device(cdev);
> +
> +	return readl(zynq->regs + UART_FIFO);
> +}
> +
> +static void zynq_serial_flush(struct console_device *cdev)
> +{
> +	struct zynq_serial_device *zynq = to_zynq_device(cdev);
> +
> +	while (!(readl(zynq->regs + UART_SR) & UART_SR_TXEMPTY));
> +}
> +
> +static int zynq_serial_probe(struct device_d *dev)
> +{
> +	struct zynq_serial_device *priv;
> +	struct console_device *cdev;
> +	int err;
> +
> +	priv = xzalloc(sizeof(*priv));
> +	cdev = &priv->cdev;
> +
> +	priv->regs	= dev_request_mem_region(dev, 0);
> +	cdev->dev	= dev;
> +	cdev->f_caps	= CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
> +	cdev->tstc	= zynq_serial_tstc;
> +	cdev->putc	= zynq_serial_putc;
> +	cdev->getc	= zynq_serial_getc;
> +	cdev->flush	= zynq_serial_flush;
> +
> +	priv->clk = clk_get(dev, NULL);
you need to check here too
> +
> +	err = clk_enable(priv->clk);
> +	if (err) {
> +		free(priv);
> +		return err;
> +	}
> +
> +	zynq_serial_init_device(priv);
> +
> +	dev->priv = priv;
> +
> +	return console_register(cdev);
> +}
> +
> +static void zynq_serial_remove(struct device_d *dev)
> +{
> +	struct zynq_serial_device *zynq = dev->priv;
> +	clk_disable(zynq->clk);
> +	free(zynq);
> +}
> +
> +static struct driver_d zynq_serial_driver = {
> +	.name	= "zynq_serial",
> +	.probe	= zynq_serial_probe,
> +	.remove = zynq_serial_remove,
> +};
> +
> +static int zynq_serial_init(void)
> +{
> +	return platform_driver_register(&zynq_serial_driver);
> +}
> +console_initcall(zynq_serial_init);
> -- 
> 1.8.1.2
> 
> 
> 
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Re: [PATCH 3/5] ARM: zynq: add driver for Zynq uarts

[Jean-Christophe PLAGNIOL-VILLARD]

On 18:48 Sat 02 Mar     , Josh Cartwright wrote:
> 
> Simple UART driver for Zynq SoCs, based loosely on the u-boot driver.
> 
> Signed-off-by: Josh Cartwright <joshc@eso.teric.us>
> ---
>  drivers/serial/Kconfig       |   6 ++
>  drivers/serial/Makefile      |   1 +
>  drivers/serial/serial_zynq.c | 144 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 151 insertions(+)
>  create mode 100644 drivers/serial/serial_zynq.c
> 
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index f61d670..608b616 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -113,4 +113,10 @@ config DRIVER_SERIAL_OMAP4_USBBOOT
>  	help
>  	  Enable this to get console support over the usb bus used to boot an OMAP4
>  
> +config DRIVER_SERIAL_ZYNQ
> +	bool "driver for Zynq uarts"
> +	default n
> +	help
> +	  Say Y here to get console out support with the Zynq uarts
> +
>  endmenu
> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
> index 893e282..883394f 100644
> --- a/drivers/serial/Makefile
> +++ b/drivers/serial/Makefile
> @@ -21,3 +21,4 @@ obj-$(CONFIG_DRIVER_SERIAL_ALTERA)		+= serial_altera.o
>  obj-$(CONFIG_DRIVER_SERIAL_ALTERA_JTAG)		+= serial_altera_jtag.o
>  obj-$(CONFIG_DRIVER_SERIAL_PXA)			+= serial_pxa.o
>  obj-$(CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT)	+= serial_omap4_usbboot.o
> +obj-$(CONFIG_DRIVER_SERIAL_ZYNQ)		+= serial_zynq.o
> diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
> new file mode 100644
> index 0000000..ec93b58
> --- /dev/null
> +++ b/drivers/serial/serial_zynq.c
> @@ -0,0 +1,144 @@
> +/*
> + * (C) Copyright 2013 Josh Cartwright
> + *
> + * Based very loosely on u-boot drivers/serial/serial_zynq.c.
> + *
> + * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
> + * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include <common.h>
> +#include <io.h>
> +#include <init.h>
> +#include <driver.h>
> +#include <xfuncs.h>
> +#include <console.h>
> +#include <malloc.h>
> +
> +#include <linux/clk.h>
> +
> +#define UART_CR		0x00000000
> +#define UART_CR_TXEN	(1<<4)
> +#define UART_CR_RXEN	(1<<2)
> +#define UART_CR_TXRST	(1<<1)
> +#define UART_CR_RXRST	(1<<0)
> +
> +#define UART_SR		0x0000002C
> +#define UART_SR_TXFULL	(1<<4)
> +#define UART_SR_TXEMPTY	(1<<3)
> +#define UART_SR_RXFULL	(1<<2)
> +#define UART_SR_RXEMPTY	(1<<1)
> +
> +#define UART_FIFO	0x00000030
> +
> +struct zynq_serial_device {
> +	struct console_device cdev;
> +	struct clk *clk;
> +	void __iomem *regs;
> +};
> +
> +#define to_zynq_device(p) container_of(p, struct zynq_serial_device, cdev)
> +
> +static void zynq_serial_init_device(struct zynq_serial_device *dev)
> +{
> +	writel(UART_CR_TXEN | UART_CR_RXEN | UART_CR_TXEN | UART_CR_RXEN,
> +	       dev->regs + UART_CR);
> +}
> +
> +static int zynq_serial_tstc(struct console_device *cdev)
> +{
> +	struct zynq_serial_device *zynq = to_zynq_device(cdev);
> +
> +	return !(readl(zynq->regs + UART_SR) & UART_SR_RXEMPTY);
> +}
> +
> +static void zynq_serial_putc(struct console_device *cdev, char c)
> +{
> +	struct zynq_serial_device *zynq = to_zynq_device(cdev);
> +
> +	while (readl(zynq->regs + UART_SR) & UART_SR_TXFULL);
> +
> +	writel(c, zynq->regs + UART_FIFO);
> +}
> +
> +static int zynq_serial_getc(struct console_device *cdev)
> +{
> +	struct zynq_serial_device *zynq = to_zynq_device(cdev);
> +
> +	return readl(zynq->regs + UART_FIFO);
> +}
> +
> +static void zynq_serial_flush(struct console_device *cdev)
> +{
> +	struct zynq_serial_device *zynq = to_zynq_device(cdev);
> +
> +	while (!(readl(zynq->regs + UART_SR) & UART_SR_TXEMPTY));
> +}
> +
> +static int zynq_serial_probe(struct device_d *dev)
> +{
> +	struct zynq_serial_device *priv;
> +	struct console_device *cdev;
> +	int err;
> +
> +	priv = xzalloc(sizeof(*priv));
> +	cdev = &priv->cdev;
> +
> +	priv->regs	= dev_request_mem_region(dev, 0);
> +	cdev->dev	= dev;
> +	cdev->f_caps	= CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
> +	cdev->tstc	= zynq_serial_tstc;
> +	cdev->putc	= zynq_serial_putc;
> +	cdev->getc	= zynq_serial_getc;
> +	cdev->flush	= zynq_serial_flush;
> +
> +	priv->clk = clk_get(dev, NULL);
> +
> +	err = clk_enable(priv->clk);
> +	if (err) {
> +		free(priv);
> +		return err;
> +	}
> +
> +	zynq_serial_init_device(priv);
> +
> +	dev->priv = priv;
> +
> +	return console_register(cdev);
> +}
> +
> +static void zynq_serial_remove(struct device_d *dev)
> +{
> +	struct zynq_serial_device *zynq = dev->priv;
> +	clk_disable(zynq->clk);
> +	free(zynq);
do;nt do so otherwise the kernel will have no uart for decompress and
earlyprintk
> +}
> +
> +static struct driver_d zynq_serial_driver = {
> +	.name	= "zynq_serial",
> +	.probe	= zynq_serial_probe,
> +	.remove = zynq_serial_remove,
> +};
> +
> +static int zynq_serial_init(void)
> +{
> +	return platform_driver_register(&zynq_serial_driver);
> +}
> +console_initcall(zynq_serial_init);
> -- 
> 1.8.1.2
> 
> 
> 
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Re: [PATCH 5/5] ARM: zynq: add support for zc702 development board

[Jean-Christophe PLAGNIOL-VILLARD]

On 18:48 Sat 02 Mar     , Josh Cartwright wrote:
> 
> Signed-off-by: Josh Cartwright <joshc@eso.teric.us>
> ---
>  arch/arm/Makefile                     |  2 +
>  arch/arm/boards/zynq-zc702/Makefile   |  1 +
>  arch/arm/boards/zynq-zc702/config.h   |  0
>  arch/arm/boards/zynq-zc702/devices.c  | 70 +++++++++++++++++++++++++++++++++++
>  arch/arm/boards/zynq-zc702/lowlevel.c | 28 ++++++++++++++
>  arch/arm/mach-zynq/Kconfig            | 19 ++++++++++
>  6 files changed, 120 insertions(+)
>  create mode 100644 arch/arm/boards/zynq-zc702/Makefile
>  create mode 100644 arch/arm/boards/zynq-zc702/config.h
>  create mode 100644 arch/arm/boards/zynq-zc702/devices.c
>  create mode 100644 arch/arm/boards/zynq-zc702/lowlevel.c
> 
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index fcb2969..9073a55 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -64,6 +64,7 @@ machine-$(CONFIG_ARCH_PXA)		:= pxa
>  machine-$(CONFIG_ARCH_SAMSUNG)		:= samsung
>  machine-$(CONFIG_ARCH_VERSATILE)	:= versatile
>  machine-$(CONFIG_ARCH_TEGRA)		:= tegra
> +machine-$(CONFIG_ARCH_ZYNQ)		:= zynq
>  
>  # Board directory name.  This list is sorted alphanumerically
>  # by CONFIG_* macro name.
> @@ -157,6 +158,7 @@ board-$(CONFIG_MACH_SABRELITE)			:= freescale-mx6-sabrelite
>  board-$(CONFIG_MACH_TX53)			:= karo-tx53
>  board-$(CONFIG_MACH_GUF_VINCELL)		:= guf-vincell
>  board-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK)		:= efika-mx-smartbook
> +board-$(CONFIG_MACH_ZYNQ_ZC702)			:= zynq-zc702
>  
>  machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
>  
> diff --git a/arch/arm/boards/zynq-zc702/Makefile b/arch/arm/boards/zynq-zc702/Makefile
> new file mode 100644
> index 0000000..385bd9f
> --- /dev/null
> +++ b/arch/arm/boards/zynq-zc702/Makefile
> @@ -0,0 +1 @@
> +obj-y += lowlevel.o devices.o
> diff --git a/arch/arm/boards/zynq-zc702/config.h b/arch/arm/boards/zynq-zc702/config.h
> new file mode 100644
> index 0000000..e69de29
> diff --git a/arch/arm/boards/zynq-zc702/devices.c b/arch/arm/boards/zynq-zc702/devices.c
> new file mode 100644
> index 0000000..b9ec9f3
> --- /dev/null
> +++ b/arch/arm/boards/zynq-zc702/devices.c
> @@ -0,0 +1,70 @@
> +/*
> + * Copyright (c) 2013 Josh Cartwright <joshc@eso.teric.us>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include <common.h>
> +#include <driver.h>
> +#include <init.h>
> +#include <sizes.h>
> +
> +#include <asm/memory.h>
> +
> +static struct resource smp_twd_resource = {
> +	.name	= "smp_twd_base",
> +	.start	= 0xF8F00600,
> +	.end	= 0xF8F00610,
> +	.flags	= IORESOURCE_MEM,
> +};
> +
> +static struct device_d zynq_smp_twd = {
> +	.id		= DEVICE_ID_DYNAMIC,
> +	.name		= "smp_twd",
> +	.num_resources	= 1,
> +	.resource	= &smp_twd_resource,
> +};
> +
> +static struct resource zynq_serial_resource = {
> +	.name	= "zynq_serial_base",
> +	.start	= 0xE0001000,
> +	.end	= 0xE0001048,
> +	.flags	= IORESOURCE_MEM,
> +};
> +
> +static struct device_d zynq_serial = {
> +	.id		= DEVICE_ID_DYNAMIC,
> +	.name		= "zynq_serial",
> +	.num_resources	= 1,
> +	.resource	= &zynq_serial_resource,
> +};

use generic code to register the devices
> +
> +static int zc702_console_init(void)
> +{
> +	platform_device_register(&zynq_serial);
> +	return 0;
> +}
> +console_initcall(zc702_console_init);
> +
> +static int zc702_mem_init(void)
> +{
> +	arm_add_mem_device("ram0", 0, SZ_128M);
> +	return 0;
> +}
> +mem_initcall(zc702_mem_init);
> +
> +static int zc702_twd_init(void)
> +{
> +	platform_device_register(&zynq_smp_twd);
> +	return 0;
> +}
> +coredevice_initcall(zc702_twd_init);
> diff --git a/arch/arm/boards/zynq-zc702/lowlevel.c b/arch/arm/boards/zynq-zc702/lowlevel.c
> new file mode 100644
> index 0000000..662d969
> --- /dev/null
> +++ b/arch/arm/boards/zynq-zc702/lowlevel.c
> @@ -0,0 +1,28 @@
> +/*
> + * Copyright (c) 2013 Josh Cartwright <joshc@eso.teric.us>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include <common.h>
> +#include <init.h>
> +#include <asm/barebox-arm.h>
> +#include <asm/barebox-arm-head.h>
> +
> +#include <mach/slcr.h>
> +
> +void __naked __bare_init barebox_arm_reset_vector(void)
> +{
> +	slcr_unlock();
> +	arm_cpu_lowlevel_init();
> +	barebox_arm_entry(0x8000, SZ_128M, 0);
can you detect the ddr size
> +}
> diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
> index 90b17f3..992a485 100644
> --- a/arch/arm/mach-zynq/Kconfig
> +++ b/arch/arm/mach-zynq/Kconfig
> @@ -1,3 +1,22 @@
>  if ARCH_ZYNQ
>  
> +config ARCH_TEXT_BASE
> +	hex
> +	default 0x04000000 if MACH_ZYNQ_ZC702
> +
> +config ZYNQ_PS_CLK_FREQ
> +	int
> +	default 33333330 if MACH_ZYNQ_ZC702
move it to C
> +
> +config BOARDINFO
> +	default "Xilinx Zynq zc702 dev board" if MACH_ZYNQ_ZC702
> +
> +choice
> +	prompt "Xilinx Zynq zc702 dev board"
> +
> +config MACH_ZYNQ_ZC702
> +	bool "zc702 development board"
> +
> +endchoice
> +
>  endif
> -- 
> 1.8.1.2
> 
> 
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Re: [PATCH 3/5] ARM: zynq: add driver for Zynq uarts

[Josh Cartwright]

On Sun, Mar 03, 2013 at 11:16:49AM +0400, Antony Pavlov wrote:
> On 3 March 2013 04:48, Josh Cartwright <joshc@eso.teric.us> wrote:
> > Simple UART driver for Zynq SoCs, based loosely on the u-boot driver.
> >
> > Signed-off-by: Josh Cartwright <joshc@eso.teric.us>
> > ---
> >  drivers/serial/Kconfig       |   6 ++
> >  drivers/serial/Makefile      |   1 +
> >  drivers/serial/serial_zynq.c | 144 +++++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 151 insertions(+)
> >  create mode 100644 drivers/serial/serial_zynq.c
> >
> > diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> > index f61d670..608b616 100644
> > --- a/drivers/serial/Kconfig
> > +++ b/drivers/serial/Kconfig
> > @@ -113,4 +113,10 @@ config DRIVER_SERIAL_OMAP4_USBBOOT
> >         help
> >           Enable this to get console support over the usb bus used to boot an OMAP4
> >
> > +config DRIVER_SERIAL_ZYNQ
> > +       bool "driver for Zynq uarts"
> > +       default n
> > +       help
> > +         Say Y here to get console out support with the Zynq uarts
> > +
> >  endmenu
> > diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
> > index 893e282..883394f 100644
> > --- a/drivers/serial/Makefile
> > +++ b/drivers/serial/Makefile
> > @@ -21,3 +21,4 @@ obj-$(CONFIG_DRIVER_SERIAL_ALTERA)            += serial_altera.o
> >  obj-$(CONFIG_DRIVER_SERIAL_ALTERA_JTAG)                += serial_altera_jtag.o
> >  obj-$(CONFIG_DRIVER_SERIAL_PXA)                        += serial_pxa.o
> >  obj-$(CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT)      += serial_omap4_usbboot.o
> > +obj-$(CONFIG_DRIVER_SERIAL_ZYNQ)               += serial_zynq.o
> > diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
> > new file mode 100644
> > index 0000000..ec93b58
> > --- /dev/null
> > +++ b/drivers/serial/serial_zynq.c
> > @@ -0,0 +1,144 @@
> > +/*
> > + * (C) Copyright 2013 Josh Cartwright
> > + *
> > + * Based very loosely on u-boot drivers/serial/serial_zynq.c.
> > + *
> > + * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
> > + * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +#include <common.h>
> > +#include <io.h>
> > +#include <init.h>
> > +#include <driver.h>
> > +#include <xfuncs.h>
> > +#include <console.h>
> > +#include <malloc.h>
> > +
> > +#include <linux/clk.h>
> > +
> > +#define UART_CR                0x00000000
> > +#define UART_CR_TXEN   (1<<4)
> > +#define UART_CR_RXEN   (1<<2)
> > +#define UART_CR_TXRST  (1<<1)
> > +#define UART_CR_RXRST  (1<<0)
> > +
> > +#define UART_SR                0x0000002C
> > +#define UART_SR_TXFULL (1<<4)
> > +#define UART_SR_TXEMPTY        (1<<3)
> > +#define UART_SR_RXFULL (1<<2)
> > +#define UART_SR_RXEMPTY        (1<<1)
> > +
> > +#define UART_FIFO      0x00000030
> > +
> > +struct zynq_serial_device {
> > +       struct console_device cdev;
> > +       struct clk *clk;
> > +       void __iomem *regs;
> > +};
> > +
> > +#define to_zynq_device(p) container_of(p, struct zynq_serial_device, cdev)
> > +
> > +static void zynq_serial_init_device(struct zynq_serial_device *dev)
> > +{
> > +       writel(UART_CR_TXEN | UART_CR_RXEN | UART_CR_TXEN | UART_CR_RXEN,
> 
> 
> IMHO there are too many 'UART_CR_TXEN' and 'UART_CR_RXEN' here.

Yes indeed, thanks.

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Re: [PATCH 0/5] Zynq support for barebox

[Steffen Trumtrar]

Hi!

On Sat, Mar 02, 2013 at 07:20:12PM -0600, Josh Cartwright wrote:
> In San Francisco a couple weeks ago (ELC2013), Thomas Petazzoni
> informally mentioned barebox in passing, so I decided to toy with it a
> bit...
> 
> This patchset adds basic support for the Zynq SoC to barebox.  So far,
> it's only been tested as a 'secondary' bootloader (after u-boot).  Also
> added is support for the zc702 development board.
> 

I have some patches laying around, that have support for booting first stage
from a SD-Card on a ZedBoard. I didn't send them as of yet, because I'm not
completely satisfied with them in one or two places. (The clocksource seems to
be inverse to what barebox expects, which would be a quick fix, and barebox boots
uuultra slow, if I do everything according to the TRM)
At the moment, I do not have access to the board though. But I hope I can get a
hand on it in the next days.
What I do not have atm is the clkdev stuff, that you already have.

Regards,
Steffen

> The first two patches are simple typos I found getting acclimated to the
> barebox source.
> 
> Josh Cartwright (5):
>   trivial: doc: fix typos in mach-arm.dox
>   defaultenv: fixed mismatched braces in bin/boot
>   ARM: zynq: add driver for Zynq uarts
>   ARM: zynq: add support for Zynq 7000 SoC
>   ARM: zynq: add support for zc702 development board
> 
>  arch/arm/Kconfig                           |   9 +
>  arch/arm/Makefile                          |   2 +
>  arch/arm/boards/zynq-zc702/Makefile        |   1 +
>  arch/arm/boards/zynq-zc702/config.h        |   0
>  arch/arm/boards/zynq-zc702/devices.c       |  70 ++++++
>  arch/arm/boards/zynq-zc702/lowlevel.c      |  28 +++
>  arch/arm/mach-arm.dox                      |   4 +-
>  arch/arm/mach-zynq/Kconfig                 |  22 ++
>  arch/arm/mach-zynq/Makefile                |   1 +
>  arch/arm/mach-zynq/clocks.c                | 341 +++++++++++++++++++++++++++++
>  arch/arm/mach-zynq/include/mach/clkdev.h   |   7 +
>  arch/arm/mach-zynq/include/mach/debug_ll.h |  21 ++
>  arch/arm/mach-zynq/include/mach/slcr.h     |  26 +++
>  arch/arm/mach-zynq/reset.c                 |  28 +++
>  defaultenv/bin/boot                        |   2 +-
>  drivers/serial/Kconfig                     |   6 +
>  drivers/serial/Makefile                    |   1 +
>  drivers/serial/serial_zynq.c               | 144 ++++++++++++
>  18 files changed, 710 insertions(+), 3 deletions(-)
>  create mode 100644 arch/arm/boards/zynq-zc702/Makefile
>  create mode 100644 arch/arm/boards/zynq-zc702/config.h
>  create mode 100644 arch/arm/boards/zynq-zc702/devices.c
>  create mode 100644 arch/arm/boards/zynq-zc702/lowlevel.c
>  create mode 100644 arch/arm/mach-zynq/Kconfig
>  create mode 100644 arch/arm/mach-zynq/Makefile
>  create mode 100644 arch/arm/mach-zynq/clocks.c
>  create mode 100644 arch/arm/mach-zynq/include/mach/clkdev.h
>  create mode 100644 arch/arm/mach-zynq/include/mach/debug_ll.h
>  create mode 100644 arch/arm/mach-zynq/include/mach/slcr.h
>  create mode 100644 arch/arm/mach-zynq/reset.c
>  create mode 100644 drivers/serial/serial_zynq.c
> 
> -- 
> 1.8.1.2
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

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Re: [PATCH 0/5] Zynq support for barebox

[Josh Cartwright]

On Sun, Mar 03, 2013 at 03:58:10PM +0100, Steffen Trumtrar wrote:
> Hi!
> 
> On Sat, Mar 02, 2013 at 07:20:12PM -0600, Josh Cartwright wrote:
> > In San Francisco a couple weeks ago (ELC2013), Thomas Petazzoni
> > informally mentioned barebox in passing, so I decided to toy with it a
> > bit...
> > 
> > This patchset adds basic support for the Zynq SoC to barebox.  So far,
> > it's only been tested as a 'secondary' bootloader (after u-boot).  Also
> > added is support for the zc702 development board.
> > 
> 
> I have some patches laying around, that have support for booting first stage
> from a SD-Card on a ZedBoard. I didn't send them as of yet, because I'm not
> completely satisfied with them in one or two places. (The clocksource seems to
> be inverse to what barebox expects, which would be a quick fix, and barebox boots
> uuultra slow, if I do everything according to the TRM)
> At the moment, I do not have access to the board though. But I hope I can get a
> hand on it in the next days.

If you have a chance to send out what you have, I'd be curious to see
it.  Fortunately I have several Zynq boards to play with.

   Josh

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Re: [PATCH 5/5] ARM: zynq: add support for zc702 development board

[Josh Cartwright]

Thanks for the review!

On Sun, Mar 03, 2013 at 11:39:18AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 18:48 Sat 02 Mar     , Josh Cartwright wrote:
[..]
> > index 0000000..b9ec9f3
> > --- /dev/null
> > +++ b/arch/arm/boards/zynq-zc702/devices.c
> > @@ -0,0 +1,70 @@
> > +/*
> > + * Copyright (c) 2013 Josh Cartwright <joshc@eso.teric.us>
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms and conditions of the GNU General Public License,
> > + * version 2, as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope it will be useful, but WITHOUT
> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> > + * more details.
> > + *
> > + * You should have received a copy of the GNU General Public License along with
> > + * this program.  If not, see <http://www.gnu.org/licenses/>.
> > + */
> > +#include <common.h>
> > +#include <driver.h>
> > +#include <init.h>
> > +#include <sizes.h>
> > +
> > +#include <asm/memory.h>
> > +
> > +static struct resource smp_twd_resource = {
> > +	.name	= "smp_twd_base",
> > +	.start	= 0xF8F00600,
> > +	.end	= 0xF8F00610,
> > +	.flags	= IORESOURCE_MEM,
> > +};
> > +
> > +static struct device_d zynq_smp_twd = {
> > +	.id		= DEVICE_ID_DYNAMIC,
> > +	.name		= "smp_twd",
> > +	.num_resources	= 1,
> > +	.resource	= &smp_twd_resource,
> > +};
> > +
> > +static struct resource zynq_serial_resource = {
> > +	.name	= "zynq_serial_base",
> > +	.start	= 0xE0001000,
> > +	.end	= 0xE0001048,
> > +	.flags	= IORESOURCE_MEM,
> > +};
> > +
> > +static struct device_d zynq_serial = {
> > +	.id		= DEVICE_ID_DYNAMIC,
> > +	.name		= "zynq_serial",
> > +	.num_resources	= 1,
> > +	.resource	= &zynq_serial_resource,
> > +};
> 
> use generic code to register the devices

I'm assuming you're referring to add_generic_device() and friends.  I'll
look into it.

[..]
> > +++ b/arch/arm/boards/zynq-zc702/lowlevel.c
> > @@ -0,0 +1,28 @@
> > +/*
> > + * Copyright (c) 2013 Josh Cartwright <joshc@eso.teric.us>
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms and conditions of the GNU General Public License,
> > + * version 2, as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope it will be useful, but WITHOUT
> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> > + * more details.
> > + *
> > + * You should have received a copy of the GNU General Public License along with
> > + * this program.  If not, see <http://www.gnu.org/licenses/>.
> > + */
> > +#include <common.h>
> > +#include <init.h>
> > +#include <asm/barebox-arm.h>
> > +#include <asm/barebox-arm-head.h>
> > +
> > +#include <mach/slcr.h>
> > +
> > +void __naked __bare_init barebox_arm_reset_vector(void)
> > +{
> > +	slcr_unlock();
> > +	arm_cpu_lowlevel_init();
> > +	barebox_arm_entry(0x8000, SZ_128M, 0);
> can you detect the ddr size

I don't think this is possible, but I'll look a bit more.
> > +}
> > diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
> > index 90b17f3..992a485 100644
> > --- a/arch/arm/mach-zynq/Kconfig
> > +++ b/arch/arm/mach-zynq/Kconfig
> > @@ -1,3 +1,22 @@
> >  if ARCH_ZYNQ
> >  
> > +config ARCH_TEXT_BASE
> > +	hex
> > +	default 0x04000000 if MACH_ZYNQ_ZC702
> > +
> > +config ZYNQ_PS_CLK_FREQ
> > +	int
> > +	default 33333330 if MACH_ZYNQ_ZC702
> move it to C

Will-do.

Thanks again,

   Josh

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Re: [PATCH 4/5] ARM: zynq: add support for Zynq 7000 SoC

[Josh Cartwright]

On Sun, Mar 03, 2013 at 11:24:53AM +0400, Antony Pavlov wrote:
> On 3 March 2013 04:48, Josh Cartwright <joshc@eso.teric.us> wrote:
> > Signed-off-by: Josh Cartwright <joshc@eso.teric.us>
[..]
> > --- /dev/null
> > +++ b/arch/arm/mach-zynq/reset.c
> > @@ -0,0 +1,28 @@
> > +/*
> > + * Copyright (C) 2013 Josh Cartwright <joshc@eso.teric.us>
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> 
> Please drop the address of the FSF.

Okay, will-do.  It's also included in the notice in the serial driver,
but I'm a little weary about it's removal there since it's taken
verbatim from the copyright notice in the u-boot driver.

   Josh

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Re: [PATCH 5/5] ARM: zynq: add support for zc702 development board

[Jean-Christophe PLAGNIOL-VILLARD]

On 11:16 Tue 05 Mar     , Josh Cartwright wrote:
> Thanks for the review!
> 
> On Sun, Mar 03, 2013 at 11:39:18AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 18:48 Sat 02 Mar     , Josh Cartwright wrote:
> [..]
> > > index 0000000..b9ec9f3
> > > --- /dev/null
> > > +++ b/arch/arm/boards/zynq-zc702/devices.c
> > > @@ -0,0 +1,70 @@
> > > +/*
> > > + * Copyright (c) 2013 Josh Cartwright <joshc@eso.teric.us>
> > > + *
> > > + * This program is free software; you can redistribute it and/or modify it
> > > + * under the terms and conditions of the GNU General Public License,
> > > + * version 2, as published by the Free Software Foundation.
> > > + *
> > > + * This program is distributed in the hope it will be useful, but WITHOUT
> > > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > > + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> > > + * more details.
> > > + *
> > > + * You should have received a copy of the GNU General Public License along with
> > > + * this program.  If not, see <http://www.gnu.org/licenses/>.
> > > + */
> > > +#include <common.h>
> > > +#include <driver.h>
> > > +#include <init.h>
> > > +#include <sizes.h>
> > > +
> > > +#include <asm/memory.h>
> > > +
> > > +static struct resource smp_twd_resource = {
> > > +	.name	= "smp_twd_base",
> > > +	.start	= 0xF8F00600,
> > > +	.end	= 0xF8F00610,
> > > +	.flags	= IORESOURCE_MEM,
> > > +};
> > > +
> > > +static struct device_d zynq_smp_twd = {
> > > +	.id		= DEVICE_ID_DYNAMIC,
> > > +	.name		= "smp_twd",
> > > +	.num_resources	= 1,
> > > +	.resource	= &smp_twd_resource,
> > > +};
> > > +
> > > +static struct resource zynq_serial_resource = {
> > > +	.name	= "zynq_serial_base",
> > > +	.start	= 0xE0001000,
> > > +	.end	= 0xE0001048,
> > > +	.flags	= IORESOURCE_MEM,
> > > +};
> > > +
> > > +static struct device_d zynq_serial = {
> > > +	.id		= DEVICE_ID_DYNAMIC,
> > > +	.name		= "zynq_serial",
> > > +	.num_resources	= 1,
> > > +	.resource	= &zynq_serial_resource,
> > > +};
> > 
> > use generic code to register the devices
> 
> I'm assuming you're referring to add_generic_device() and friends.  I'll
> look into it.
yes as we plan the add a platform_device and driver struct in the feature
so use add_generic_device will simplify the switch

as now you need to use a specific bus for all the device as example etc...
> 
> [..]
> > > +++ b/arch/arm/boards/zynq-zc702/lowlevel.c
> > > @@ -0,0 +1,28 @@
> > > +/*
> > > + * Copyright (c) 2013 Josh Cartwright <joshc@eso.teric.us>
> > > + *
> > > + * This program is free software; you can redistribute it and/or modify it
> > > + * under the terms and conditions of the GNU General Public License,
> > > + * version 2, as published by the Free Software Foundation.
> > > + *
> > > + * This program is distributed in the hope it will be useful, but WITHOUT
> > > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > > + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> > > + * more details.
> > > + *
> > > + * You should have received a copy of the GNU General Public License along with
> > > + * this program.  If not, see <http://www.gnu.org/licenses/>.
> > > + */
> > > +#include <common.h>
> > > +#include <init.h>
> > > +#include <asm/barebox-arm.h>
> > > +#include <asm/barebox-arm-head.h>
> > > +
> > > +#include <mach/slcr.h>
> > > +
> > > +void __naked __bare_init barebox_arm_reset_vector(void)
> > > +{
> > > +	slcr_unlock();
> > > +	arm_cpu_lowlevel_init();
> > > +	barebox_arm_entry(0x8000, SZ_128M, 0);
> > can you detect the ddr size
> 
> I don't think this is possible, but I'll look a bit more.
you do not have a ddr controller?

or a i2c controller to read the eeprom?
> > > +}
> > > diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
> > > index 90b17f3..992a485 100644
> > > --- a/arch/arm/mach-zynq/Kconfig
> > > +++ b/arch/arm/mach-zynq/Kconfig
> > > @@ -1,3 +1,22 @@
> > >  if ARCH_ZYNQ
> > >  
> > > +config ARCH_TEXT_BASE
> > > +	hex
> > > +	default 0x04000000 if MACH_ZYNQ_ZC702
> > > +
> > > +config ZYNQ_PS_CLK_FREQ
> > > +	int
> > > +	default 33333330 if MACH_ZYNQ_ZC702
> > move it to C
> 
> Will-do.
> 
> Thanks again,
> 
>    Josh

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Re: [PATCH 4/5] ARM: zynq: add support for Zynq 7000 SoC

[Sascha Hauer]

On Tue, Mar 05, 2013 at 11:22:00AM -0600, Josh Cartwright wrote:
> On Sun, Mar 03, 2013 at 11:24:53AM +0400, Antony Pavlov wrote:
> > On 3 March 2013 04:48, Josh Cartwright <joshc@eso.teric.us> wrote:
> > > Signed-off-by: Josh Cartwright <joshc@eso.teric.us>
> [..]
> > > --- /dev/null
> > > +++ b/arch/arm/mach-zynq/reset.c
> > > @@ -0,0 +1,28 @@
> > > +/*
> > > + * Copyright (C) 2013 Josh Cartwright <joshc@eso.teric.us>
> > > + *
> > > + * This program is free software; you can redistribute it and/or
> > > + * modify it under the terms of the GNU General Public License as
> > > + * published by the Free Software Foundation; either version 2 of
> > > + * the License, or (at your option) any later version.
> > > + *
> > > + * This program is distributed in the hope that it will be useful,
> > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > > + * GNU General Public License for more details.
> > > + *
> > > + * You should have received a copy of the GNU General Public License
> > > + * along with this program; if not, write to the Free Software
> > > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > > + * MA 02111-1307 USA
> > 
> > Please drop the address of the FSF.
> 
> Okay, will-do.  It's also included in the notice in the serial driver,
> but I'm a little weary about it's removal there since it's taken
> verbatim from the copyright notice in the u-boot driver.

It's fine to remove it. The address is wrong anyway. You should leave a
note though where the code comes from, either in the commit log or in
the header.

Sascha

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Re: [PATCH 0/5] Zynq support for barebox

[Steffen Trumtrar]

On Tue, Mar 05, 2013 at 11:09:29AM -0600, Josh Cartwright wrote:
> On Sun, Mar 03, 2013 at 03:58:10PM +0100, Steffen Trumtrar wrote:
> > Hi!
> > 
> > On Sat, Mar 02, 2013 at 07:20:12PM -0600, Josh Cartwright wrote:
> > > In San Francisco a couple weeks ago (ELC2013), Thomas Petazzoni
> > > informally mentioned barebox in passing, so I decided to toy with it a
> > > bit...
> > > 
> > > This patchset adds basic support for the Zynq SoC to barebox.  So far,
> > > it's only been tested as a 'secondary' bootloader (after u-boot).  Also
> > > added is support for the zc702 development board.
> > > 
> > 
> > I have some patches laying around, that have support for booting first stage
> > from a SD-Card on a ZedBoard. I didn't send them as of yet, because I'm not
> > completely satisfied with them in one or two places. (The clocksource seems to
> > be inverse to what barebox expects, which would be a quick fix, and barebox boots
> > uuultra slow, if I do everything according to the TRM)
> > At the moment, I do not have access to the board though. But I hope I can get a
> > hand on it in the next days.
> 
> If you have a chance to send out what you have, I'd be curious to see
> it.  Fortunately I have several Zynq boards to play with.
> 

Hi!

Have a look at
http://git.pengutronix.de/?p=str/barebox.git;a=summary

I "stole" your clk driver and added it to my patch stack :-)
Current state for ZedBoard:
	- boot first stage from SD-Card
		- barebox.bin needs to be processed with
		./scripts/zynq_checksum barebox.bin BOOT.bin
		to have the checksum in the BootROM header
	- clocksource is arm_smp_tmd at seems accurate
	- the BootROM needs about 4-5 seconds to copy barebox from
	  SD to the OCM. I guess, I need to mess with the SD setup
	  in the BootROM somehow
	- just enough clkdev to use the timer
	- all pinctrl, clk setup etc happens in the lowlevel init

Regards,
Steffen

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH 0/5] Zynq support for barebox

[Josh Cartwright]

On Wed, Mar 06, 2013 at 06:28:50PM +0100, Steffen Trumtrar wrote:
> On Tue, Mar 05, 2013 at 11:09:29AM -0600, Josh Cartwright wrote:
[..]
> > > I have some patches laying around, that have support for booting first stage
> > > from a SD-Card on a ZedBoard. I didn't send them as of yet, because I'm not
> > > completely satisfied with them in one or two places. (The clocksource seems to
> > > be inverse to what barebox expects, which would be a quick fix, and barebox boots
> > > uuultra slow, if I do everything according to the TRM)
> > > At the moment, I do not have access to the board though. But I hope I can get a
> > > hand on it in the next days.
> > 
> > If you have a chance to send out what you have, I'd be curious to see
> > it.  Fortunately I have several Zynq boards to play with.
> > 
> 
> Hi!
> 
> Have a look at
> http://git.pengutronix.de/?p=str/barebox.git;a=summary
> 
> I "stole" your clk driver and added it to my patch stack :-)
> Current state for ZedBoard:
> 	- boot first stage from SD-Card
> 		- barebox.bin needs to be processed with
> 		./scripts/zynq_checksum barebox.bin BOOT.bin
> 		to have the checksum in the BootROM header
> 	- clocksource is arm_smp_tmd at seems accurate
> 	- the BootROM needs about 4-5 seconds to copy barebox from
> 	  SD to the OCM. I guess, I need to mess with the SD setup
> 	  in the BootROM somehow
> 	- just enough clkdev to use the timer
> 	- all pinctrl, clk setup etc happens in the lowlevel init

Hey Steffen-

Thanks for sharing this! I'll be looking to get board support for the
zc702 on top of your work this weekend (I have several Zynq boards, but
none of them are ZedBoards).  I'm also in the process of porting the
uboot zynq_gem driver.

Do you have plans for submitting this to the list?

Thanks again,

   Josh

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Re: [PATCH 0/5] Zynq support for barebox

[Steffen Trumtrar]

On Thu, Mar 07, 2013 at 04:46:25PM -0600, Josh Cartwright wrote:
> On Wed, Mar 06, 2013 at 06:28:50PM +0100, Steffen Trumtrar wrote:
> > On Tue, Mar 05, 2013 at 11:09:29AM -0600, Josh Cartwright wrote:
> [..]
> > > > I have some patches laying around, that have support for booting first stage
> > > > from a SD-Card on a ZedBoard. I didn't send them as of yet, because I'm not
> > > > completely satisfied with them in one or two places. (The clocksource seems to
> > > > be inverse to what barebox expects, which would be a quick fix, and barebox boots
> > > > uuultra slow, if I do everything according to the TRM)
> > > > At the moment, I do not have access to the board though. But I hope I can get a
> > > > hand on it in the next days.
> > > 
> > > If you have a chance to send out what you have, I'd be curious to see
> > > it.  Fortunately I have several Zynq boards to play with.
> > > 
> > 
> > Hi!
> > 
> > Have a look at
> > http://git.pengutronix.de/?p=str/barebox.git;a=summary
> > 
> > I "stole" your clk driver and added it to my patch stack :-)
> > Current state for ZedBoard:
> > 	- boot first stage from SD-Card
> > 		- barebox.bin needs to be processed with
> > 		./scripts/zynq_checksum barebox.bin BOOT.bin
> > 		to have the checksum in the BootROM header
> > 	- clocksource is arm_smp_tmd at seems accurate
> > 	- the BootROM needs about 4-5 seconds to copy barebox from
> > 	  SD to the OCM. I guess, I need to mess with the SD setup
> > 	  in the BootROM somehow
> > 	- just enough clkdev to use the timer
> > 	- all pinctrl, clk setup etc happens in the lowlevel init

Hi Josh!

> 
> Hey Steffen-
> 
> Thanks for sharing this! I'll be looking to get board support for the
> zc702 on top of your work this weekend (I have several Zynq boards, but
> none of them are ZedBoards).  I'm also in the process of porting the
> uboot zynq_gem driver.

First, \o/. I don't know how the two differ. But I would guess, that
you can pretty much copy the lowlevel stuff et al.
Only the DDR timing stuff may make problems.

Second: No! Don't! I'm trying to get drivers/net/macb.c running on Zynq.
As far as I can tell at the moment, this is a driver for a
Cadence IP gem. And the zynq uses exactly that IP core.
Alas, I have problems with the dma_alloc_coherent call in its
probe function.

The same goes for the UART driver and other cores. We should not start
developing Xilinx drivers for everything, if in reality we have IP cores
from other providers.

The same goes for Linux. I haven't managed to boot mainline linux yet,
but I saw that there are multiple bindings and drivers for Xilinx.
And the TRM clearly states, that WDT, GEM, SPI, UART and TTC are all
Cadence IP cores.

> Do you have plans for submitting this to the list?

Yes, definitely! I need to cleanup the patches a little and want to
be sure that I didn't do anything stupidly wrong. The problem with
dma_alloc is at least a hint, that I maybe did.

Regards,
Steffen

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH 0/5] Zynq support for barebox

[Michal Simek]

Hi,

2013/3/8 Steffen Trumtrar <s.trumtrar@pengutronix.de>:
> On Thu, Mar 07, 2013 at 04:46:25PM -0600, Josh Cartwright wrote:
>> On Wed, Mar 06, 2013 at 06:28:50PM +0100, Steffen Trumtrar wrote:
>> > On Tue, Mar 05, 2013 at 11:09:29AM -0600, Josh Cartwright wrote:
>> [..]
>> > > > I have some patches laying around, that have support for booting first stage
>> > > > from a SD-Card on a ZedBoard. I didn't send them as of yet, because I'm not
>> > > > completely satisfied with them in one or two places. (The clocksource seems to
>> > > > be inverse to what barebox expects, which would be a quick fix, and barebox boots
>> > > > uuultra slow, if I do everything according to the TRM)
>> > > > At the moment, I do not have access to the board though. But I hope I can get a
>> > > > hand on it in the next days.
>> > >
>> > > If you have a chance to send out what you have, I'd be curious to see
>> > > it.  Fortunately I have several Zynq boards to play with.
>> > >
>> >
>> > Hi!
>> >
>> > Have a look at
>> > http://git.pengutronix.de/?p=str/barebox.git;a=summary
>> >
>> > I "stole" your clk driver and added it to my patch stack :-)
>> > Current state for ZedBoard:
>> >     - boot first stage from SD-Card
>> >             - barebox.bin needs to be processed with
>> >             ./scripts/zynq_checksum barebox.bin BOOT.bin
>> >             to have the checksum in the BootROM header
>> >     - clocksource is arm_smp_tmd at seems accurate
>> >     - the BootROM needs about 4-5 seconds to copy barebox from
>> >       SD to the OCM. I guess, I need to mess with the SD setup
>> >       in the BootROM somehow
>> >     - just enough clkdev to use the timer
>> >     - all pinctrl, clk setup etc happens in the lowlevel init

Nice. What's the difference between this barebox and u-boot?
I remember that discussion on u-boot mailing list.
Is it just that Kconfig stuff and driver initialization?

What about DT support? Initialized u-boot from device tree?
Is it there?


>> Thanks for sharing this! I'll be looking to get board support for the
>> zc702 on top of your work this weekend (I have several Zynq boards, but
>> none of them are ZedBoards).  I'm also in the process of porting the
>> uboot zynq_gem driver.
>
> First, \o/. I don't know how the two differ. But I would guess, that
> you can pretty much copy the lowlevel stuff et al.
> Only the DDR timing stuff may make problems.

Difference is only in connection out of chip. How barebox handle this?
Serial IP selections, ddr size, mmc, etc.


> Second: No! Don't! I'm trying to get drivers/net/macb.c running on Zynq.
> As far as I can tell at the moment, this is a driver for a
> Cadence IP gem. And the zynq uses exactly that IP core.
> Alas, I have problems with the dma_alloc_coherent call in its
> probe function.

Nice. I will look forward on input from this. We need to use this IP
in linux kernel too.

>
> The same goes for the UART driver and other cores. We should not start
> developing Xilinx drivers for everything, if in reality we have IP cores
> from other providers.

definitely.

> The same goes for Linux. I haven't managed to boot mainline linux yet,
> but I saw that there are multiple bindings and drivers for Xilinx.
> And the TRM clearly states, that WDT, GEM, SPI, UART and TTC are all
> Cadence IP cores.

yep, pl330, cadence gem, spi not sure, wdt also not sure, xilinx uart
is in the mainline
and none reports that there is cadence serial driver too.
TTC is also news for me.
If you can point me to them, that will be great.


>> Do you have plans for submitting this to the list?
>
> Yes, definitely! I need to cleanup the patches a little and want to
> be sure that I didn't do anything stupidly wrong. The problem with
> dma_alloc is at least a hint, that I maybe did.

Nice discussion. Would like to look at it with you but

Hopefully next next week I will have more time to look at your patches
and try it.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform

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Re: [PATCH 0/5] Zynq support for barebox

[Josh Cartwright]

On Fri, Mar 08, 2013 at 07:39:18AM +0100, Steffen Trumtrar wrote:
> On Thu, Mar 07, 2013 at 04:46:25PM -0600, Josh Cartwright wrote:
> > On Wed, Mar 06, 2013 at 06:28:50PM +0100, Steffen Trumtrar wrote:
> > > On Tue, Mar 05, 2013 at 11:09:29AM -0600, Josh Cartwright wrote:
> > [..]
> > > > > I have some patches laying around, that have support for booting first stage
> > > > > from a SD-Card on a ZedBoard. I didn't send them as of yet, because I'm not
> > > > > completely satisfied with them in one or two places. (The clocksource seems to
> > > > > be inverse to what barebox expects, which would be a quick fix, and barebox boots
> > > > > uuultra slow, if I do everything according to the TRM)
> > > > > At the moment, I do not have access to the board though. But I hope I can get a
> > > > > hand on it in the next days.
> > > > 
> > > > If you have a chance to send out what you have, I'd be curious to see
> > > > it.  Fortunately I have several Zynq boards to play with.
> > > > 
> > > 
> > > Hi!
> > > 
> > > Have a look at
> > > http://git.pengutronix.de/?p=str/barebox.git;a=summary
> > > 
> > > I "stole" your clk driver and added it to my patch stack :-)
> > > Current state for ZedBoard:
> > > 	- boot first stage from SD-Card
> > > 		- barebox.bin needs to be processed with
> > > 		./scripts/zynq_checksum barebox.bin BOOT.bin
> > > 		to have the checksum in the BootROM header
> > > 	- clocksource is arm_smp_tmd at seems accurate
> > > 	- the BootROM needs about 4-5 seconds to copy barebox from
> > > 	  SD to the OCM. I guess, I need to mess with the SD setup
> > > 	  in the BootROM somehow
> > > 	- just enough clkdev to use the timer
> > > 	- all pinctrl, clk setup etc happens in the lowlevel init
> 
> Hi Josh!
> 
> > Hey Steffen-
> > 
> > Thanks for sharing this! I'll be looking to get board support for the
> > zc702 on top of your work this weekend (I have several Zynq boards, but
> > none of them are ZedBoards).  I'm also in the process of porting the
> > uboot zynq_gem driver.
> 
> First, \o/. I don't know how the two differ. But I would guess, that
> you can pretty much copy the lowlevel stuff et al.
> Only the DDR timing stuff may make problems.
> 
> Second: No! Don't! I'm trying to get drivers/net/macb.c running on Zynq.
> As far as I can tell at the moment, this is a driver for a
> Cadence IP gem. And the zynq uses exactly that IP core.
> Alas, I have problems with the dma_alloc_coherent call in its
> probe function.

Doh!  I certainly did not want to duplicate a driver unnecessarily.
I'll keep this in mind going forward.

> The same goes for the UART driver and other cores. We should not start
> developing Xilinx drivers for everything, if in reality we have IP cores
> from other providers.

Absolutely.

Thanks,

   Josh

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Re: [PATCH 0/5] Zynq support for barebox

[Jean-Christophe PLAGNIOL-VILLARD]

On 07:39 Fri 08 Mar     , Steffen Trumtrar wrote:
> On Thu, Mar 07, 2013 at 04:46:25PM -0600, Josh Cartwright wrote:
> > On Wed, Mar 06, 2013 at 06:28:50PM +0100, Steffen Trumtrar wrote:
> > > On Tue, Mar 05, 2013 at 11:09:29AM -0600, Josh Cartwright wrote:
> > [..]
> > > > > I have some patches laying around, that have support for booting first stage
> > > > > from a SD-Card on a ZedBoard. I didn't send them as of yet, because I'm not
> > > > > completely satisfied with them in one or two places. (The clocksource seems to
> > > > > be inverse to what barebox expects, which would be a quick fix, and barebox boots
> > > > > uuultra slow, if I do everything according to the TRM)
> > > > > At the moment, I do not have access to the board though. But I hope I can get a
> > > > > hand on it in the next days.
> > > > 
> > > > If you have a chance to send out what you have, I'd be curious to see
> > > > it.  Fortunately I have several Zynq boards to play with.
> > > > 
> > > 
> > > Hi!
> > > 
> > > Have a look at
> > > http://git.pengutronix.de/?p=str/barebox.git;a=summary
> > > 
> > > I "stole" your clk driver and added it to my patch stack :-)
> > > Current state for ZedBoard:
> > > 	- boot first stage from SD-Card
> > > 		- barebox.bin needs to be processed with
> > > 		./scripts/zynq_checksum barebox.bin BOOT.bin
> > > 		to have the checksum in the BootROM header
> > > 	- clocksource is arm_smp_tmd at seems accurate
> > > 	- the BootROM needs about 4-5 seconds to copy barebox from
> > > 	  SD to the OCM. I guess, I need to mess with the SD setup
> > > 	  in the BootROM somehow
> > > 	- just enough clkdev to use the timer
> > > 	- all pinctrl, clk setup etc happens in the lowlevel init
> 
> Hi Josh!
> 
> > 
> > Hey Steffen-
> > 
> > Thanks for sharing this! I'll be looking to get board support for the
> > zc702 on top of your work this weekend (I have several Zynq boards, but
> > none of them are ZedBoards).  I'm also in the process of porting the
> > uboot zynq_gem driver.
> 
> First, \o/. I don't know how the two differ. But I would guess, that
> you can pretty much copy the lowlevel stuff et al.
> Only the DDR timing stuff may make problems.
> 
> Second: No! Don't! I'm trying to get drivers/net/macb.c running on Zynq.
> As far as I can tell at the moment, this is a driver for a
> Cadence IP gem. And the zynq uses exactly that IP core.
> Alas, I have problems with the dma_alloc_coherent call in its
> probe function.
this should not give you any trouble execpt if you do not able the l2cache
correctly

I did the port and test that drivers on Cortex-A5
and Nicolas and I work on it to share the code with the kernel

U-Boot does not implement it correctly anyway

Best Regards,
J.
> 
> The same goes for the UART driver and other cores. We should not start
> developing Xilinx drivers for everything, if in reality we have IP cores
> from other providers.
> 
> The same goes for Linux. I haven't managed to boot mainline linux yet,
> but I saw that there are multiple bindings and drivers for Xilinx.
> And the TRM clearly states, that WDT, GEM, SPI, UART and TTC are all
> Cadence IP cores.
> 
> > Do you have plans for submitting this to the list?
> 
> Yes, definitely! I need to cleanup the patches a little and want to
> be sure that I didn't do anything stupidly wrong. The problem with
> dma_alloc is at least a hint, that I maybe did.
> 
> Regards,
> Steffen
> 
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox

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Re: [PATCH 0/5] Zynq support for barebox

[Steffen Trumtrar]

On Fri, Mar 08, 2013 at 10:10:11AM -0600, Josh Cartwright wrote:
> On Fri, Mar 08, 2013 at 07:39:18AM +0100, Steffen Trumtrar wrote:
> > On Thu, Mar 07, 2013 at 04:46:25PM -0600, Josh Cartwright wrote:
> > > On Wed, Mar 06, 2013 at 06:28:50PM +0100, Steffen Trumtrar wrote:
> > > > On Tue, Mar 05, 2013 at 11:09:29AM -0600, Josh Cartwright wrote:
> > > [..]
> > > > > > I have some patches laying around, that have support for booting first stage
> > > > > > from a SD-Card on a ZedBoard. I didn't send them as of yet, because I'm not
> > > > > > completely satisfied with them in one or two places. (The clocksource seems to
> > > > > > be inverse to what barebox expects, which would be a quick fix, and barebox boots
> > > > > > uuultra slow, if I do everything according to the TRM)
> > > > > > At the moment, I do not have access to the board though. But I hope I can get a
> > > > > > hand on it in the next days.
> > > > > 
> > > > > If you have a chance to send out what you have, I'd be curious to see
> > > > > it.  Fortunately I have several Zynq boards to play with.
> > > > > 
> > > > 
> > > > Hi!
> > > > 
> > > > Have a look at
> > > > http://git.pengutronix.de/?p=str/barebox.git;a=summary
> > > > 
> > > > I "stole" your clk driver and added it to my patch stack :-)
> > > > Current state for ZedBoard:
> > > > 	- boot first stage from SD-Card
> > > > 		- barebox.bin needs to be processed with
> > > > 		./scripts/zynq_checksum barebox.bin BOOT.bin
> > > > 		to have the checksum in the BootROM header
> > > > 	- clocksource is arm_smp_tmd at seems accurate
> > > > 	- the BootROM needs about 4-5 seconds to copy barebox from
> > > > 	  SD to the OCM. I guess, I need to mess with the SD setup
> > > > 	  in the BootROM somehow
> > > > 	- just enough clkdev to use the timer
> > > > 	- all pinctrl, clk setup etc happens in the lowlevel init
> > 
> > Hi Josh!
> > 
> > > Hey Steffen-
> > > 
> > > Thanks for sharing this! I'll be looking to get board support for the
> > > zc702 on top of your work this weekend (I have several Zynq boards, but
> > > none of them are ZedBoards).  I'm also in the process of porting the
> > > uboot zynq_gem driver.
> > 
> > First, \o/. I don't know how the two differ. But I would guess, that
> > you can pretty much copy the lowlevel stuff et al.
> > Only the DDR timing stuff may make problems.
> > 
> > Second: No! Don't! I'm trying to get drivers/net/macb.c running on Zynq.
> > As far as I can tell at the moment, this is a driver for a
> > Cadence IP gem. And the zynq uses exactly that IP core.
> > Alas, I have problems with the dma_alloc_coherent call in its
> > probe function.
> 
> Doh!  I certainly did not want to duplicate a driver unnecessarily.
> I'll keep this in mind going forward.
>

Just a quick note: it seems that the macb can be used. I didn't manage to
get a connection yet. But I can talk to the phy, get a link etc.

So, the linux macb driver should work two.

Regards,
Steffen


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH 0/5] Zynq support for barebox

[Steffen Trumtrar]

Hi,

On Fri, Mar 08, 2013 at 01:20:47PM +0100, Michal Simek wrote:
> Hi,
> 
> 2013/3/8 Steffen Trumtrar <s.trumtrar@pengutronix.de>:
> > On Thu, Mar 07, 2013 at 04:46:25PM -0600, Josh Cartwright wrote:
> >> On Wed, Mar 06, 2013 at 06:28:50PM +0100, Steffen Trumtrar wrote:
> >> > On Tue, Mar 05, 2013 at 11:09:29AM -0600, Josh Cartwright wrote:
> >> [..]
> >> > > > I have some patches laying around, that have support for booting first stage
> >> > > > from a SD-Card on a ZedBoard. I didn't send them as of yet, because I'm not
> >> > > > completely satisfied with them in one or two places. (The clocksource seems to
> >> > > > be inverse to what barebox expects, which would be a quick fix, and barebox boots
> >> > > > uuultra slow, if I do everything according to the TRM)
> >> > > > At the moment, I do not have access to the board though. But I hope I can get a
> >> > > > hand on it in the next days.
> >> > >
> >> > > If you have a chance to send out what you have, I'd be curious to see
> >> > > it.  Fortunately I have several Zynq boards to play with.
> >> > >
> >> >
> >> > Hi!
> >> >
> >> > Have a look at
> >> > http://git.pengutronix.de/?p=str/barebox.git;a=summary
> >> >
> >> > I "stole" your clk driver and added it to my patch stack :-)
> >> > Current state for ZedBoard:
> >> >     - boot first stage from SD-Card
> >> >             - barebox.bin needs to be processed with
> >> >             ./scripts/zynq_checksum barebox.bin BOOT.bin
> >> >             to have the checksum in the BootROM header
> >> >     - clocksource is arm_smp_tmd at seems accurate
> >> >     - the BootROM needs about 4-5 seconds to copy barebox from
> >> >       SD to the OCM. I guess, I need to mess with the SD setup
> >> >       in the BootROM somehow
> >> >     - just enough clkdev to use the timer
> >> >     - all pinctrl, clk setup etc happens in the lowlevel init
> 
> Nice. What's the difference between this barebox and u-boot?
> I remember that discussion on u-boot mailing list.
> Is it just that Kconfig stuff and driver initialization?
> 
> What about DT support? Initialized u-boot from device tree?
> Is it there?
> 

Well, I don't actually know, what u-boot can do, as I do not follow it.
barebox uses Kconfig, the linux driver model, a lot less #ifdefs, has
support for a compressed bootloader, that extracts itself, the environment
system is IHMO way better than in u-boot, a menu, where you can select the
bootsource etc, you can boot images via tftp with "bootm /mnt/tftp/zImage",
you can boot zImage, uImage, ... with appended DT, with separate DT,
there is support for DT probing of devices.
What I like the most: if you know linux kernel and its structure, you know
barebox and its structure (well, mostly).

> 
> >> Thanks for sharing this! I'll be looking to get board support for the
> >> zc702 on top of your work this weekend (I have several Zynq boards, but
> >> none of them are ZedBoards).  I'm also in the process of porting the
> >> uboot zynq_gem driver.
> >
> > First, \o/. I don't know how the two differ. But I would guess, that
> > you can pretty much copy the lowlevel stuff et al.
> > Only the DDR timing stuff may make problems.
> 
> Difference is only in connection out of chip. How barebox handle this?

barebox has /arch/arm/boards/avnet-zedboard/board.c, here you can define
the boardspecific pincontrol etc. Well, like the platformcode in the kernel.
For the zynq there is no pinctrl driver though, as I have to write it first :-)

Clocks are handled like in linux. With clockdev and clocktree.

ATM this is all hardcoded in the lowlevel init.

> Serial IP selections, ddr size, mmc, etc.
> 
> 
> > Second: No! Don't! I'm trying to get drivers/net/macb.c running on Zynq.
> > As far as I can tell at the moment, this is a driver for a
> > Cadence IP gem. And the zynq uses exactly that IP core.
> > Alas, I have problems with the dma_alloc_coherent call in its
> > probe function.
> 
> Nice. I will look forward on input from this. We need to use this IP
> in linux kernel too.
> 
> >
> > The same goes for the UART driver and other cores. We should not start
> > developing Xilinx drivers for everything, if in reality we have IP cores
> > from other providers.
> 
> definitely.
> 
> > The same goes for Linux. I haven't managed to boot mainline linux yet,
> > but I saw that there are multiple bindings and drivers for Xilinx.
> > And the TRM clearly states, that WDT, GEM, SPI, UART and TTC are all
> > Cadence IP cores.
> 
> yep, pl330, cadence gem, spi not sure, wdt also not sure, xilinx uart
> is in the mainline
> and none reports that there is cadence serial driver too.
> TTC is also news for me.
> If you can point me to them, that will be great.
> 
Well, I don't know if there are drivers for all those IPs, but if there
aren't any, they should be called cadence-something with the according
bindings. Oh, and Arasan-something for the SD-Controller.

Well, maybe those IPs are even not really developed by Cadence and compatible
to other drivers, who knows.
For the Synopsys USB controller you might want to take a look at the ChipIdea
driver (ci13xxx-something). It is the same core ;-)

> 
> >> Do you have plans for submitting this to the list?
> >
> > Yes, definitely! I need to cleanup the patches a little and want to
> > be sure that I didn't do anything stupidly wrong. The problem with
> > dma_alloc is at least a hint, that I maybe did.
> 
> Nice discussion. Would like to look at it with you but
> 
> Hopefully next next week I will have more time to look at your patches
> and try it.
> 

Regards and nice weekend,
Steffen

-- 
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