Re: [PATCH 4/7] arm: initial support for Marvell Armada 370/XP SoCs

From: Sascha Hauer <s.hauer@pengutronix.de>
To: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Lior Amsalem <alior@marvell.com>,
	barebox@lists.infradead.org,
	Ezequiel Garcia <ezequiel.garcia@free-electrons.com>,
	Willy Tarreau <w@1wt.eu>
Subject: Re: [PATCH 4/7] arm: initial support for Marvell Armada 370/XP SoCs
Date: Mon, 6 May 2013 16:46:34 +0200	[thread overview]
Message-ID: <20130506144634.GH32299@pengutronix.de> (raw)
In-Reply-To: <20130506163424.4e398333@skate>

On Mon, May 06, 2013 at 04:34:24PM +0200, Thomas Petazzoni wrote:
> Dear Sascha Hauer,
> 
> On Mon, 6 May 2013 16:30:30 +0200, Sascha Hauer wrote:
> 
> > > ... and here, I'm directly poking at physical addresses, but it seems
> > > like Barebox can run with the MMU enabled. Should I be mapping those
> > > registers before accessing them?
> > 
> > We use the MMU, but we use a 1:1 mapping. The SDRAM is mapped cached and
> > the rest is mapped uncached. This means you can simply access all
> > registers without mapping them
> 
> Ok, thanks. So you're not overly chocked by those readl() poking
> directly at physical addresses, if I understand correctly.

Not at all, we do this everywhere. There is a tendency to turn units
into proper drivers though as drivers show up in the 'iomem' command and
with drivers it's generally easier to abstract between different SoCs.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox