[PATCH] mci i.MX esdhc: Fix clock divider calculation

* [PATCH] mci i.MX esdhc: Fix clock divider calculation
@ 2013-05-21 10:29 Steffen Trumtrar
  2013-05-21 19:27 ` Sascha Hauer
  0 siblings, 1 reply; 3+ messages in thread
From: Steffen Trumtrar @ 2013-05-21 10:29 UTC (permalink / raw)
  To: barebox; +Cc: Steffen Trumtrar

From: Sascha Hauer <s.hauer@pengutronix.de>

This updates the i.MX esdhc divider settings to FSLs U-Boot.
Current timings work fine for SD cards, but not for eMMC.
Although the calculation is fine according to the datasheet and reading from
eMMC works, writing is broken. Atleast on i.MX53/tqma53.
With this patch the result is the same, but uses different divider values to
achieve it.

While at it, replace the udelay with a busy-loop.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 drivers/mci/imx-esdhc.c | 46 +++++++++++++++++++++++++++-------------------
 drivers/mci/imx-esdhc.h |  1 +
 2 files changed, 28 insertions(+), 19 deletions(-)

diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index 8c2695c..6a9faf9 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -69,7 +69,6 @@ struct fsl_esdhc_host {
 	struct mci_host		mci;
 	struct fsl_esdhc __iomem	*regs;
 	u32			no_snoop;
-	unsigned long		cur_clock;
 	struct device_d		*dev;
 	struct clk		*clk;
 };
@@ -358,37 +357,46 @@ static void set_sysctl(struct mci_host *mci, u32 clock)
 	struct fsl_esdhc __iomem *regs = host->regs;
 	int sdhc_clk = clk_get_rate(host->clk);
 	u32 clk;
-
-	if (clock < mci->f_min)
-		clock = mci->f_min;
-
-	pre_div = 0;
-
-	for (pre_div = 1; pre_div < 256; pre_div <<= 1) {
-		if (sdhc_clk / pre_div < clock * 16)
+	unsigned long  cur_clock;
+
+	/*
+	 * With eMMC and imx53 (sdhc_clk=200MHz) a pre_div of 1 results in
+	 *	pre_div=1,div=4 (=50MHz)
+	 * which is valid and should work, but somehow doesn't.
+	 * Starting with pre_div=2 gives
+	 *	pre_div=2, div=2 (=50MHz)
+	 * and works fine.
+	 */
+	pre_div = 2;
+
+	if (sdhc_clk == clock)
+		pre_div = 1;
+	else if (sdhc_clk / 16 > clock)
+		for (; pre_div < 256; pre_div *= 2)
+			if ((sdhc_clk / pre_div) <= (clock * 16))
+				break;
+
+	for (div = 1; div <= 16; div++)
+		if ((sdhc_clk / (div * pre_div)) <= clock)
 			break;
-	};
-
-	div = sdhc_clk / pre_div / clock;
 
-	if (sdhc_clk / pre_div / div > clock)
-		div++;
+	cur_clock = sdhc_clk / pre_div / div;
 
-	host->cur_clock = sdhc_clk / pre_div / div;
+	dev_dbg(host->dev, "set clock: wanted: %d got: %ld\n", clock, cur_clock);
+	dev_dbg(host->dev, "pre_div: %d div: %d\n", pre_div, div);
 
+	/* the register values start with 0 */
 	div -= 1;
 	pre_div >>= 1;
 
-	dev_dbg(host->dev, "set clock: wanted: %d got: %ld\n", clock, host->cur_clock);
-	dev_dbg(host->dev, "pre_div: %d div: %d\n", pre_div, div);
-
 	clk = (pre_div << 8) | (div << 4);
 
 	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
 
 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
 
-	udelay(10000);
+	wait_on_timeout(10 * MSECOND,
+			!(esdhc_read32(&regs->prsstat) & PRSSTAT_SDSTB));
 
 	clk = SYSCTL_PEREN | SYSCTL_CKEN;
 
diff --git a/drivers/mci/imx-esdhc.h b/drivers/mci/imx-esdhc.h
index 2be63a5..e145bcb 100644
--- a/drivers/mci/imx-esdhc.h
+++ b/drivers/mci/imx-esdhc.h
@@ -86,6 +86,7 @@
 #define PRSSTAT_CINS		(0x00010000)
 #define PRSSTAT_BREN		(0x00000800)
 #define PRSSTAT_BWEN		(0x00000400)
+#define PRSSTAT_SDSTB		(0x00000008)
 #define PRSSTAT_DLA		(0x00000004)
 #define PRSSTAT_CICHB		(0x00000002)
 #define PRSSTAT_CIDHB		(0x00000001)
-- 
1.8.2.rc2


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