* [PATCH 01/22] ARM: Karo TX25: register external NAND boot update handler
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 15:03 ` [PATCH 02/22] ARM: phyCARD-i.MX27: increase barebox partition Sascha Hauer
` (20 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
To be able to update barebox with the barebox_update command.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/karo-tx25/board.c | 4 ++++
arch/arm/boards/karo-tx25/env/init/mtdparts-nand | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c
index 337ae01..7cdeecc 100644
--- a/arch/arm/boards/karo-tx25/board.c
+++ b/arch/arm/boards/karo-tx25/board.c
@@ -38,6 +38,7 @@
#include <mach/iim.h>
#include <linux/err.h>
#include <mach/devices-imx25.h>
+#include <mach/bbu.h>
#include <asm/mmu.h>
static struct fec_platform_data fec_info = {
@@ -115,6 +116,9 @@ static int tx25_devices_init(void)
armlinux_set_architecture(MACH_TYPE_TX25);
armlinux_set_serial(imx_uid());
+ imx_bbu_external_nand_register_handler("nand", "/dev/nand0.barebox",
+ BBU_HANDLER_FLAG_DEFAULT);
+
return 0;
}
diff --git a/arch/arm/boards/karo-tx25/env/init/mtdparts-nand b/arch/arm/boards/karo-tx25/env/init/mtdparts-nand
index 4fffefc..e2dcfab 100644
--- a/arch/arm/boards/karo-tx25/env/init/mtdparts-nand
+++ b/arch/arm/boards/karo-tx25/env/init/mtdparts-nand
@@ -5,7 +5,7 @@ if [ "$1" = menu ]; then
exit
fi
-mtdparts="512k(nand0.barebox)ro,512k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)"
+mtdparts="512k(nand0.barebox),512k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)"
kernelname="mxc_nand"
mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts}
--
1.8.5.2
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^ permalink raw reply [flat|nested] 35+ messages in thread* [PATCH 02/22] ARM: phyCARD-i.MX27: increase barebox partition
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
2014-01-17 15:03 ` [PATCH 01/22] ARM: Karo TX25: register external NAND boot update handler Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-18 19:16 ` Alexander Aring
2014-01-17 15:03 ` [PATCH 03/22] ARM: phyCARD-i.MX27: register barebox update handler Sascha Hauer
` (19 subsequent siblings)
21 siblings, 1 reply; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
More place for barebox.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/phycard-i.MX27/env/config | 2 +-
arch/arm/boards/phycard-i.MX27/pca100.c | 5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boards/phycard-i.MX27/env/config b/arch/arm/boards/phycard-i.MX27/env/config
index 9596311..9f10e7d 100644
--- a/arch/arm/boards/phycard-i.MX27/env/config
+++ b/arch/arm/boards/phycard-i.MX27/env/config
@@ -39,7 +39,7 @@ autoboot_timeout=3
bootargs="console=ttymxc0,115200"
-nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
+nand_parts="512k(barebox)ro,512k(bareboxenv),2M(kernel),-(root)"
rootfs_mtdblock_nand=7
# set a fancy prompt (if support is compiled in)
diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c
index 2ff1b79..7ac0bf6 100644
--- a/arch/arm/boards/phycard-i.MX27/pca100.c
+++ b/arch/arm/boards/phycard-i.MX27/pca100.c
@@ -21,6 +21,7 @@
#include <mach/imx27-regs.h>
#include <fec.h>
#include <gpio.h>
+#include <sizes.h>
#include <asm/armlinux.h>
#include <asm/sections.h>
#include <generated/mach-types.h>
@@ -287,10 +288,10 @@ static int pca100_devices_init(void)
#endif
nand = get_device_by_name("nand0");
- devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
armlinux_set_architecture(2149);
--
1.8.5.2
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 02/22] ARM: phyCARD-i.MX27: increase barebox partition
2014-01-17 15:03 ` [PATCH 02/22] ARM: phyCARD-i.MX27: increase barebox partition Sascha Hauer
@ 2014-01-18 19:16 ` Alexander Aring
2014-01-19 14:19 ` Alexander Aring
2014-01-20 9:28 ` Sascha Hauer
0 siblings, 2 replies; 35+ messages in thread
From: Alexander Aring @ 2014-01-18 19:16 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
Hi,
On Fri, Jan 17, 2014 at 04:03:12PM +0100, Sascha Hauer wrote:
> More place for barebox.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/boards/phycard-i.MX27/env/config | 2 +-
> arch/arm/boards/phycard-i.MX27/pca100.c | 5 +++--
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boards/phycard-i.MX27/env/config b/arch/arm/boards/phycard-i.MX27/env/config
> index 9596311..9f10e7d 100644
> --- a/arch/arm/boards/phycard-i.MX27/env/config
> +++ b/arch/arm/boards/phycard-i.MX27/env/config
> @@ -39,7 +39,7 @@ autoboot_timeout=3
>
> bootargs="console=ttymxc0,115200"
>
> -nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
> +nand_parts="512k(barebox)ro,512k(bareboxenv),2M(kernel),-(root)"
First I through "2 MB for kernel?", but then I see you change this to 4MB
in another patch which introduce the new barebox env, so thats pretty cool.
:-)
> rootfs_mtdblock_nand=7
>
> # set a fancy prompt (if support is compiled in)
> diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c
> index 2ff1b79..7ac0bf6 100644
> --- a/arch/arm/boards/phycard-i.MX27/pca100.c
> +++ b/arch/arm/boards/phycard-i.MX27/pca100.c
> @@ -21,6 +21,7 @@
> #include <mach/imx27-regs.h>
> #include <fec.h>
> #include <gpio.h>
> +#include <sizes.h>
> #include <asm/armlinux.h>
> #include <asm/sections.h>
> #include <generated/mach-types.h>
> @@ -287,10 +288,10 @@ static int pca100_devices_init(void)
> #endif
>
> nand = get_device_by_name("nand0");
I know, you don't make any change here but I though "What the hell do this
function here? Increase some reference count, because nand is never used
in this function?" Then I look a little bit deeper and it simple does
nothing... - Maybe we should remove this and the nand variable?
It's only a small hint which I detected.
- Alex
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 02/22] ARM: phyCARD-i.MX27: increase barebox partition
2014-01-18 19:16 ` Alexander Aring
@ 2014-01-19 14:19 ` Alexander Aring
2014-01-20 9:28 ` Sascha Hauer
1 sibling, 0 replies; 35+ messages in thread
From: Alexander Aring @ 2014-01-19 14:19 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On Sat, Jan 18, 2014 at 08:16:25PM +0100, Alexander Aring wrote:
> Hi,
>
> On Fri, Jan 17, 2014 at 04:03:12PM +0100, Sascha Hauer wrote:
> > More place for barebox.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> > arch/arm/boards/phycard-i.MX27/env/config | 2 +-
> > arch/arm/boards/phycard-i.MX27/pca100.c | 5 +++--
> > 2 files changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/boards/phycard-i.MX27/env/config b/arch/arm/boards/phycard-i.MX27/env/config
> > index 9596311..9f10e7d 100644
> > --- a/arch/arm/boards/phycard-i.MX27/env/config
> > +++ b/arch/arm/boards/phycard-i.MX27/env/config
> > @@ -39,7 +39,7 @@ autoboot_timeout=3
> >
> > bootargs="console=ttymxc0,115200"
> >
> > -nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
> > +nand_parts="512k(barebox)ro,512k(bareboxenv),2M(kernel),-(root)"
>
> First I through "2 MB for kernel?", but then I see you change this to 4MB
I meant "thought" here.
>
> > rootfs_mtdblock_nand=7
> >
> > # set a fancy prompt (if support is compiled in)
> > diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c
> > index 2ff1b79..7ac0bf6 100644
> > --- a/arch/arm/boards/phycard-i.MX27/pca100.c
> > +++ b/arch/arm/boards/phycard-i.MX27/pca100.c
> > @@ -21,6 +21,7 @@
> > #include <mach/imx27-regs.h>
> > #include <fec.h>
> > #include <gpio.h>
> > +#include <sizes.h>
> > #include <asm/armlinux.h>
> > #include <asm/sections.h>
> > #include <generated/mach-types.h>
> > @@ -287,10 +288,10 @@ static int pca100_devices_init(void)
> > #endif
> >
> > nand = get_device_by_name("nand0");
>
> I know, you don't make any change here but I though "What the hell do this
here too. sry...
- Alex
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 02/22] ARM: phyCARD-i.MX27: increase barebox partition
2014-01-18 19:16 ` Alexander Aring
2014-01-19 14:19 ` Alexander Aring
@ 2014-01-20 9:28 ` Sascha Hauer
1 sibling, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-20 9:28 UTC (permalink / raw)
To: Alexander Aring; +Cc: barebox
On Sat, Jan 18, 2014 at 08:16:27PM +0100, Alexander Aring wrote:
> Hi,
>
> On Fri, Jan 17, 2014 at 04:03:12PM +0100, Sascha Hauer wrote:
> > More place for barebox.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> > arch/arm/boards/phycard-i.MX27/env/config | 2 +-
> > arch/arm/boards/phycard-i.MX27/pca100.c | 5 +++--
> > 2 files changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/boards/phycard-i.MX27/env/config b/arch/arm/boards/phycard-i.MX27/env/config
> > index 9596311..9f10e7d 100644
> > --- a/arch/arm/boards/phycard-i.MX27/env/config
> > +++ b/arch/arm/boards/phycard-i.MX27/env/config
> > @@ -39,7 +39,7 @@ autoboot_timeout=3
> >
> > bootargs="console=ttymxc0,115200"
> >
> > -nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
> > +nand_parts="512k(barebox)ro,512k(bareboxenv),2M(kernel),-(root)"
>
> First I through "2 MB for kernel?", but then I see you change this to 4MB
> in another patch which introduce the new barebox env, so thats pretty cool.
I changed this patch to increase both partitions now. It makes no sense
to wreck the partition layout twice in a single series.
> > nand = get_device_by_name("nand0");
>
> I know, you don't make any change here but I though "What the hell do this
> function here? Increase some reference count, because nand is never used
> in this function?" Then I look a little bit deeper and it simple does
> nothing... - Maybe we should remove this and the nand variable?
Added a patch to remove the unused variable. Thanks for spotting this.
Sascha
----------------8<--------------------
From a25dd5cd482c80e1c3be75568ee0a16df3b3d78d Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Mon, 20 Jan 2014 10:18:48 +0100
Subject: [PATCH 02/23] ARM: phyCARD-i.MX27: remove unused variable
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
reported-by: Alexander Aring <alex.aring@gmail.com>
---
arch/arm/boards/phycard-i.MX27/pca100.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c
index 2ff1b79..613a2ee 100644
--- a/arch/arm/boards/phycard-i.MX27/pca100.c
+++ b/arch/arm/boards/phycard-i.MX27/pca100.c
@@ -178,7 +178,6 @@ static void pca100_usb_init(void)
static int pca100_devices_init(void)
{
int i;
- struct device_d *nand;
unsigned int mode[] = {
PD0_AIN_FEC_TXD0,
@@ -286,7 +285,6 @@ static int pca100_devices_init(void)
pca100_usb_register();
#endif
- nand = get_device_by_name("nand0");
devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
---------------------8<----------------
From 955ac6de78aa8f09015f1d7829d66f7e982ecbf4 Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Fri, 17 Jan 2014 08:48:54 +0100
Subject: [PATCH 03/23] ARM: phyCARD-i.MX27: increase barebox and kernel
partition
More place for barebox and the kernel as both have the tendency to
get bigger.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/phycard-i.MX27/env/config | 2 +-
arch/arm/boards/phycard-i.MX27/pca100.c | 5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boards/phycard-i.MX27/env/config b/arch/arm/boards/phycard-i.MX27/env/config
index 9596311..160cbe7 100644
--- a/arch/arm/boards/phycard-i.MX27/env/config
+++ b/arch/arm/boards/phycard-i.MX27/env/config
@@ -39,7 +39,7 @@ autoboot_timeout=3
bootargs="console=ttymxc0,115200"
-nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
+nand_parts="512k(barebox)ro,512k(bareboxenv),4M(kernel),-(root)"
rootfs_mtdblock_nand=7
# set a fancy prompt (if support is compiled in)
diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c
index 613a2ee..3c6b727 100644
--- a/arch/arm/boards/phycard-i.MX27/pca100.c
+++ b/arch/arm/boards/phycard-i.MX27/pca100.c
@@ -21,6 +21,7 @@
#include <mach/imx27-regs.h>
#include <fec.h>
#include <gpio.h>
+#include <sizes.h>
#include <asm/armlinux.h>
#include <asm/sections.h>
#include <generated/mach-types.h>
@@ -285,10 +286,10 @@ static int pca100_devices_init(void)
pca100_usb_register();
#endif
- devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
armlinux_set_architecture(2149);
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 03/22] ARM: phyCARD-i.MX27: register barebox update handler
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
2014-01-17 15:03 ` [PATCH 01/22] ARM: Karo TX25: register external NAND boot update handler Sascha Hauer
2014-01-17 15:03 ` [PATCH 02/22] ARM: phyCARD-i.MX27: increase barebox partition Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 15:03 ` [PATCH 04/22] ARM: phyCARD-i.MX27: switch to new environment Sascha Hauer
` (18 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
To update barebox with the barebox_update command.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/phycard-i.MX27/pca100.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c
index 7ac0bf6..69f9a3d 100644
--- a/arch/arm/boards/phycard-i.MX27/pca100.c
+++ b/arch/arm/boards/phycard-i.MX27/pca100.c
@@ -37,6 +37,7 @@
#include <gpio.h>
#include <asm/mmu.h>
#include <usb/ulpi.h>
+#include <mach/bbu.h>
#include <mach/iomux-mx27.h>
#include <mach/devices-imx27.h>
@@ -294,6 +295,9 @@ static int pca100_devices_init(void)
devfs_add_partition("nand0", SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
+ imx_bbu_external_nand_register_handler("nand", "/dev/nand0.barebox",
+ BBU_HANDLER_FLAG_DEFAULT);
+
armlinux_set_architecture(2149);
return 0;
--
1.8.5.2
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^ permalink raw reply [flat|nested] 35+ messages in thread* [PATCH 04/22] ARM: phyCARD-i.MX27: switch to new environment
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (2 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 03/22] ARM: phyCARD-i.MX27: register barebox update handler Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 15:03 ` [PATCH 05/22] ARM: phyCARD-i.MX27: convert lowlevel init to c code Sascha Hauer
` (17 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/phycard-i.MX27/env/config | 48 ----------------------
.../boards/phycard-i.MX27/env/init/mtdparts-nand | 11 +++++
arch/arm/mach-imx/Kconfig | 1 +
3 files changed, 12 insertions(+), 48 deletions(-)
delete mode 100644 arch/arm/boards/phycard-i.MX27/env/config
create mode 100644 arch/arm/boards/phycard-i.MX27/env/init/mtdparts-nand
diff --git a/arch/arm/boards/phycard-i.MX27/env/config b/arch/arm/boards/phycard-i.MX27/env/config
deleted file mode 100644
index 9f10e7d..0000000
--- a/arch/arm/boards/phycard-i.MX27/env/config
+++ /dev/null
@@ -1,48 +0,0 @@
-#!/bin/sh
-
-eth0.serverip=
-user=
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-# use 'none' if you want to skip kernel ip autoconfiguration
-ip=dhcp
-
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d
-#eth0.netmask=a.b.c.d
-#eth0.gateway=a.b.c.d
-#eth0.serverip=a.b.c.d
-
-# can be either 'nfs', 'tftp', 'nor' or 'nand'
-kernel_loc=tftp
-# can be either 'net', 'nor', 'nand' or 'initrd'
-rootfs_loc=net
-
-# can be either 'jffs2' or 'ubifs'
-rootfs_type=ubifs
-rootfsimage=root-${global.hostname}.$rootfs_type
-
-kernelimage=zImage-${global.hostname}
-#kernelimage=uImage-${global.hostname}
-#kernelimage=Image-${global.hostname}
-#kernelimage=Image-${global.hostname}.lzo
-
-if [ -n $user ]; then
- kernelimage="$user"-"$kernelimage"
- nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}"
- rootfsimage="$user"-"$rootfsimage"
-else
- nfsroot="$eth0.serverip:/path/to/nfs/root"
-fi
-
-autoboot_timeout=3
-
-bootargs="console=ttymxc0,115200"
-
-nand_parts="512k(barebox)ro,512k(bareboxenv),2M(kernel),-(root)"
-rootfs_mtdblock_nand=7
-
-# set a fancy prompt (if support is compiled in)
-PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
-
-
diff --git a/arch/arm/boards/phycard-i.MX27/env/init/mtdparts-nand b/arch/arm/boards/phycard-i.MX27/env/init/mtdparts-nand
new file mode 100644
index 0000000..e2dcfab
--- /dev/null
+++ b/arch/arm/boards/phycard-i.MX27/env/init/mtdparts-nand
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ init-menu-add-entry "$0" "NAND partitions"
+ exit
+fi
+
+mtdparts="512k(nand0.barebox),512k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)"
+kernelname="mxc_nand"
+
+mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts}
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3a1089f..1b34127 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -310,6 +310,7 @@ config MACH_IMX27ADS
config MACH_PCA100
bool "phyCard-i.MX27"
select ARCH_IMX27
+ select HAVE_DEFAULT_ENVIRONMENT_NEW
help
Say Y here if you are using Phytec's phyCard-i.MX27 (pca100) equipped
with a Freescale i.MX27 Processor
--
1.8.5.2
_______________________________________________
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 35+ messages in thread* [PATCH 05/22] ARM: phyCARD-i.MX27: convert lowlevel init to c code
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (3 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 04/22] ARM: phyCARD-i.MX27: switch to new environment Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 15:03 ` [PATCH 06/22] ARM: i.MX27: Add missing MPLL clock sources Sascha Hauer
` (16 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/phycard-i.MX27/Makefile | 2 +-
arch/arm/boards/phycard-i.MX27/lowlevel.c | 107 ++++++++++++++++++++++
arch/arm/boards/phycard-i.MX27/lowlevel_init.S | 119 -------------------------
3 files changed, 108 insertions(+), 120 deletions(-)
create mode 100644 arch/arm/boards/phycard-i.MX27/lowlevel.c
delete mode 100644 arch/arm/boards/phycard-i.MX27/lowlevel_init.S
diff --git a/arch/arm/boards/phycard-i.MX27/Makefile b/arch/arm/boards/phycard-i.MX27/Makefile
index bbff289..34492bb 100644
--- a/arch/arm/boards/phycard-i.MX27/Makefile
+++ b/arch/arm/boards/phycard-i.MX27/Makefile
@@ -1,3 +1,3 @@
-lwl-y += lowlevel_init.o
+lwl-y += lowlevel.o
obj-y += pca100.o
diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel.c b/arch/arm/boards/phycard-i.MX27/lowlevel.c
new file mode 100644
index 0000000..9f5dfff
--- /dev/null
+++ b/arch/arm/boards/phycard-i.MX27/lowlevel.c
@@ -0,0 +1,107 @@
+/*
+ * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
+ * Applications Processor Reference Manual, Rev. 0.2".
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <config.h>
+#include <asm/barebox-arm-head.h>
+#include <mach/imx27-regs.h>
+#include <mach/imx-pll.h>
+#include <mach/esdctl.h>
+#include <mach/imx-nand.h>
+
+#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
+
+static void sdram_init(void)
+{
+ int i;
+
+ /*
+ * DDR on CSD0
+ */
+ /* Enable DDR SDRAM operation */
+ writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
+
+ /* Set the driving strength */
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3));
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5));
+ writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6));
+ writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7));
+ writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8));
+
+ /* Initial reset */
+ writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
+ writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
+
+ /* precharge CSD0 all banks */
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
+ writel(0x00000000, 0xa0000f00); /* CSD0 precharge address (A10 = 1) */
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
+
+ for (i = 0; i < 8; i++)
+ writel(0, 0xa0000f00);
+
+ writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
+ writeb(0xda, 0xa0000033);
+ writeb(0xff, 0xa1000000);
+
+ writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
+ ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
+ MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
+}
+
+void __bare_init __naked barebox_arm_reset_vector(void)
+{
+ unsigned long r;
+
+ arm_cpu_lowlevel_init();
+
+ arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12);
+
+ /* ahb lite ip interface */
+ writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0);
+ writel(0xdffbfcfb, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1);
+ writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0);
+ writel(0xffffffff, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1);
+
+ /* Skip SDRAM initialization if we run from RAM */
+ r = get_pc();
+ if (r > 0xa0000000 && r < 0xc0000000)
+ imx27_barebox_entry(0);
+
+ /* 399 MHz */
+ writel(IMX_PLL_PD(0) |
+ IMX_PLL_MFD(51) |
+ IMX_PLL_MFI(7) |
+ IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0);
+
+ /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
+ writel(IMX_PLL_PD(1) |
+ IMX_PLL_MFD(12) |
+ IMX_PLL_MFI(9) |
+ IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0);
+
+ writel(MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART |
+ MX27_CSCR_ARM_SRC_MPLL | MX27_CSCR_MCU_SEL |
+ MX27_CSCR_SP_SEL | MX27_CSCR_FPM_EN |
+ MX27_CSCR_MPEN | MX27_CSCR_SPEN | MX27_CSCR_ARM_DIV(0) |
+ MX27_CSCR_AHB_DIV(1) | MX27_CSCR_USB_DIV(3) |
+ MX27_CSCR_SD_CNT(3) | MX27_CSCR_SSI2_SEL |
+ MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL |
+ MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR);
+
+ sdram_init();
+
+#ifdef CONFIG_NAND_IMX_BOOT
+ imx27_barebox_boot_nand_external();
+#else
+ imx27_barebox_entry(0);
+#endif
+}
diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
deleted file mode 100644
index 992fa82..0000000
--- a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
- * Applications Processor Reference Manual, Rev. 0.2".
- *
- */
-
-#include <config.h>
-#include <mach/imx27-regs.h>
-#include <mach/imx-pll.h>
-#include <mach/esdctl.h>
-#include <asm/barebox-arm-head.h>
-
-#define writel(val, reg) \
- ldr r0, =reg; \
- ldr r1, =val; \
- str r1, [r0];
-
-
-#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
-
-.macro sdram_init
- /*
- * DDR on CSD0
- */
- /* Enable DDR SDRAM operation */
- writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
-
- /* Set the driving strength */
- writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3))
- writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5))
- writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6))
- writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7))
- writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8))
-
- /* Initial reset */
- writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
- writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0)
-
- /* precharge CSD0 all banks */
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
- MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
- writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
- MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
-
- ldr r0, =0xa0000f00
- mov r1, #0
- mov r2, #8
-1:
- str r1, [r0]
- subs r2, #1
- bne 1b
-
- writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
- MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
- ldr r0, =0xA0000033
- mov r1, #0xda
- strb r1, [r0]
- ldr r0, =0xA1000000
- mov r1, #0xff
- strb r1, [r0]
- writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
- ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
- MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
-.endm
-
- .section ".text_bare_init","ax"
-
-.globl barebox_arm_reset_vector
-barebox_arm_reset_vector:
- bl arm_cpu_lowlevel_init
-
- /* ahb lite ip interface */
- writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0)
- writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1)
- writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0)
- writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1)
-
- /* skip sdram initialization if we run from ram */
- cmp pc, #0xa0000000
- bls 1f
- cmp pc, #0xc0000000
- bhi 1f
-
- b imx27_barebox_entry
-
-1:
- /* 399 MHz */
- writel(IMX_PLL_PD(0) |
- IMX_PLL_MFD(51) |
- IMX_PLL_MFI(7) |
- IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0)
-
- /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
- writel(IMX_PLL_PD(1) |
- IMX_PLL_MFD(12) |
- IMX_PLL_MFI(9) |
- IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0)
-
- writel(MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART |
- MX27_CSCR_ARM_SRC_MPLL | MX27_CSCR_MCU_SEL |
- MX27_CSCR_SP_SEL | MX27_CSCR_FPM_EN |
- MX27_CSCR_MPEN | MX27_CSCR_SPEN | MX27_CSCR_ARM_DIV(0) |
- MX27_CSCR_AHB_DIV(1) | MX27_CSCR_USB_DIV(3) |
- MX27_CSCR_SD_CNT(3) | MX27_CSCR_SSI2_SEL |
- MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL |
- MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR)
-
- sdram_init
-
-#ifdef CONFIG_NAND_IMX_BOOT
- ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM */
-
- b imx27_barebox_boot_nand_external
-#endif /* CONFIG_NAND_IMX_BOOT */
-
-ret:
- b imx27_barebox_entry
-
--
1.8.5.2
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^ permalink raw reply [flat|nested] 35+ messages in thread* [PATCH 06/22] ARM: i.MX27: Add missing MPLL clock sources
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (4 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 05/22] ARM: phyCARD-i.MX27: convert lowlevel init to c code Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 15:03 ` [PATCH 07/22] ARM: phyCARD-i.MX27: Update defconfig Sascha Hauer
` (15 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
The MPLL can be driven from the low frequency reference clock. This
is the reset default. Currently the clock code assumes this has been
changed from the lowlevel code. If that didn't happen we get wrong
clock rates. This adds the missing clocks so that we get correct
clock rates.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/clk-imx27.c | 44 ++++++++++++++++++++++++++++++++++++++-----
1 file changed, 39 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 6fd3cd6..c792261 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -92,8 +92,23 @@
enum mx27_clks {
dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
- per2_div, per3_div, per4_div, usb_div, cpu_sel, clko_sel, cpu_div, clko_div,
- clko_en, lcdc_per_gate, lcdc_ahb_gate, lcdc_ipg_gate, clk_max
+ per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel,
+ clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div,
+ clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate,
+ sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate,
+ rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate,
+ kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate,
+ gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate,
+ gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate,
+ emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate,
+ cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate,
+ vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate,
+ usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate,
+ vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate,
+ csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
+ uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
+ uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
+ mpll_sel, spll_gate, clk_max
};
static struct clk *clks[clk_max];
@@ -103,6 +118,16 @@ static const char *cpu_sel_clks[] = {
"mpll",
};
+static const char *mpll_sel_clks[] = {
+ "fpm",
+ "mpll_osc_sel",
+};
+
+static const char *mpll_osc_sel_clks[] = {
+ "ckih",
+ "ckih_div1p5",
+};
+
static const char *clko_sel_clks[] = {
"ckil",
NULL,
@@ -152,7 +177,16 @@ static int imx27_ccm_probe(struct device_d *dev)
clks[dummy] = clk_fixed("dummy", 0);
clks[ckih] = clk_fixed("ckih", 26000000);
clks[ckil] = clk_fixed("ckil", 32768);
- clks[mpll] = imx_clk_pllv1("mpll", "ckih", base + CCM_MPCTL0);
+ clks[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
+ clks[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3);
+
+ clks[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", base + CCM_CSCR, 4, 1,
+ mpll_osc_sel_clks,
+ ARRAY_SIZE(mpll_osc_sel_clks));
+ clks[mpll_sel] = imx_clk_mux("mpll_sel", base + CCM_CSCR, 16, 1, mpll_sel_clks,
+ ARRAY_SIZE(mpll_sel_clks));
+
+ clks[mpll] = imx_clk_pllv1("mpll", "mpll_sel", base + CCM_MPCTL0);
clks[spll] = imx_clk_pllv1("spll", "ckih", base + CCM_SPCTL0);
clks[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
@@ -179,7 +213,7 @@ static int imx27_ccm_probe(struct device_d *dev)
else
clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 13, 3);
clks[clko_div] = imx_clk_divider("clko_div", "clko_sel", base + CCM_PCDR0, 22, 3);
- clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per3_div", base + CCM_PCCR1, 8);
+ clks[per3_gate] = imx_clk_gate("per3_gate", "per3_div", base + CCM_PCCR1, 8);
clks[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", base + CCM_PCCR1, 15);
clks[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", base + CCM_PCCR0, 14);
@@ -203,7 +237,7 @@ static int imx27_ccm_probe(struct device_d *dev)
clkdev_add_physbase(clks[per2_div], MX27_SDHC1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per2_div], MX27_SDHC2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per2_div], MX27_SDHC3_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[lcdc_per_gate], MX27_LCDC_BASE_ADDR, NULL);
+ clkdev_add_physbase(clks[per3_gate], MX27_LCDC_BASE_ADDR, NULL);
clkdev_add_physbase(clks[lcdc_ahb_gate], MX27_LCDC_BASE_ADDR, "ahb");
clkdev_add_physbase(clks[lcdc_ipg_gate], MX27_LCDC_BASE_ADDR, "ipg");
clkdev_add_physbase(clks[ipg], MX27_FEC_BASE_ADDR, NULL);
--
1.8.5.2
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 35+ messages in thread* [PATCH 07/22] ARM: phyCARD-i.MX27: Update defconfig
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (5 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 06/22] ARM: i.MX27: Add missing MPLL clock sources Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 15:03 ` [PATCH 08/22] ARM: Fix image size calculation for CONFIG_PBL_RELOCATABLE Sascha Hauer
` (14 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
This enables a lot of new features in the defconfig:
- Image compression
- FAT support
- Ext4 support
- UBIFS support
- more commands
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/configs/pca100_defconfig | 43 ++++++++++++++++++++++++++-------------
1 file changed, 29 insertions(+), 14 deletions(-)
diff --git a/arch/arm/configs/pca100_defconfig b/arch/arm/configs/pca100_defconfig
index db2b164..12753cf 100644
--- a/arch/arm/configs/pca100_defconfig
+++ b/arch/arm/configs/pca100_defconfig
@@ -1,57 +1,64 @@
CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y
-CONFIG_ARCH_IMX27=y
CONFIG_MACH_PCA100=y
-CONFIG_IMX_CLKO=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
+CONFIG_PBL_IMAGE=y
CONFIG_MMU=y
CONFIG_MALLOC_SIZE=0x01000000
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
-CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
-CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_MENU=y
+CONFIG_BLSPEC=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phycard-i.MX27/env"
+CONFIG_RESET_SOURCE=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
+CONFIG_CMD_MSLEEP=y
CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_TFTP=y
+CONFIG_CMD_FILETYPE=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_IOMEM=y
-CONFIG_CMD_MTEST=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_MD5SUM=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
-CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_UIMAGE=y
-# CONFIG_CMD_BOOTZ is not set
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_BAREBOX_UPDATE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_MIITOOL=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_FS_TFTP=y
CONFIG_NET_NETCONSOLE=y
CONFIG_DRIVER_NET_FEC_IMX=y
CONFIG_NET_USB=y
@@ -62,9 +69,17 @@ CONFIG_NAND=y
# CONFIG_NAND_ECC_SOFT is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
CONFIG_NAND_IMX=y
-CONFIG_UBI=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_FASTMAP=y
CONFIG_USB=y
CONFIG_USB_EHCI=y
CONFIG_USB_ULPI=y
-CONFIG_ZLIB=y
-CONFIG_LZO_DECOMPRESS=y
+CONFIG_MCI=y
+CONFIG_MCI_IMX=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_FS_UBIFS=y
+CONFIG_FS_UBIFS_COMPRESSION_LZO=y
--
1.8.5.2
_______________________________________________
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 35+ messages in thread* [PATCH 08/22] ARM: Fix image size calculation for CONFIG_PBL_RELOCATABLE
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (6 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 07/22] ARM: phyCARD-i.MX27: Update defconfig Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 15:03 ` [PATCH 09/22] ARM: i.MX: external NAND boot: factor out a 2k pagesize detection function Sascha Hauer
` (13 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
TEXT_BASE - SZ_2M is only used for non relocable pbl images.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/lib/pbl.lds.S | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/arch/arm/lib/pbl.lds.S b/arch/arm/lib/pbl.lds.S
index 1eae829..0954c89 100644
--- a/arch/arm/lib/pbl.lds.S
+++ b/arch/arm/lib/pbl.lds.S
@@ -24,15 +24,17 @@
#include <asm-generic/barebox.lds.h>
#include <asm-generic/memory_layout.h>
+#ifdef CONFIG_PBL_RELOCATABLE
+#define BASE 0x0
+#else
+#define BASE (TEXT_BASE - SZ_2M)
+#endif
+
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SECTIONS
{
-#ifdef CONFIG_PBL_RELOCATABLE
- . = 0x0;
-#else
- . = TEXT_BASE - SZ_2M;
-#endif
+ . = BASE;
PRE_IMAGE
@@ -91,7 +93,6 @@ SECTIONS
KEEP(*(.image_end))
}
__image_end = .;
-
- _barebox_image_size = __image_end - (TEXT_BASE - SZ_2M);
- _barebox_pbl_size = __bss_start - (TEXT_BASE - SZ_2M);
+ _barebox_image_size = __image_end - BASE;
+ _barebox_pbl_size = __bss_start - BASE;
}
--
1.8.5.2
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^ permalink raw reply [flat|nested] 35+ messages in thread* [PATCH 09/22] ARM: i.MX: external NAND boot: factor out a 2k pagesize detection function
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (7 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 08/22] ARM: Fix image size calculation for CONFIG_PBL_RELOCATABLE Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 15:03 ` [PATCH 10/22] ARM: i.MX: external NAND boot: create function macro for different SoCs Sascha Hauer
` (12 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/external-nand-boot.c | 65 +++++++++++++++++++++++-----------
1 file changed, 45 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c
index 1af46b7..a1221c8 100644
--- a/arch/arm/mach-imx/external-nand-boot.c
+++ b/arch/arm/mach-imx/external-nand-boot.c
@@ -279,6 +279,46 @@ int __bare_init imx_barebox_boot_nand_external(unsigned long nfc_base)
return 1;
}
+static inline int imx21_pagesize_2k(void)
+{
+ if (readl(MX21_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5))
+ return 1;
+ else
+ return 0;
+}
+
+static inline int imx25_pagesize_2k(void)
+{
+ if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 8))
+ return 1;
+ else
+ return 0;
+}
+
+static inline int imx27_pagesize_2k(void)
+{
+ if (readl(MX27_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5))
+ return 1;
+ else
+ return 0;
+}
+
+static inline int imx31_pagesize_2k(void)
+{
+ if (readl(MX31_CCM_BASE_ADDR + MX31_CCM_RCSR) & MX31_RCSR_NFMS)
+ return 1;
+ else
+ return 0;
+}
+
+static inline int imx35_pagesize_2k(void)
+{
+ if (readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR) & (1 << 8))
+ return 1;
+ else
+ return 0;
+}
+
#define BARE_INIT_FUNCTION(name) \
void __noreturn __section(.text_bare_init_##name) \
name
@@ -298,10 +338,7 @@ BARE_INIT_FUNCTION(imx21_barebox_boot_nand_external)(void)
if (imx_barebox_boot_nand_external(nfc_base)) {
jump_sdram(nfc_base - ld_var(_text));
- if (readl(MX21_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5))
- pagesize_2k = 1;
- else
- pagesize_2k = 0;
+ pagesize_2k = imx21_pagesize_2k();
imx_nand_load_image((void *)ld_var(_text),
ld_var(barebox_image_size),
@@ -321,10 +358,7 @@ BARE_INIT_FUNCTION(imx25_barebox_boot_nand_external)(void)
if (imx_barebox_boot_nand_external(nfc_base)) {
jump_sdram(nfc_base - ld_var(_text));
- if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 8))
- pagesize_2k = 1;
- else
- pagesize_2k = 0;
+ pagesize_2k = imx25_pagesize_2k();
imx_nand_load_image((void *)ld_var(_text),
ld_var(_barebox_image_size),
@@ -342,10 +376,7 @@ BARE_INIT_FUNCTION(imx27_barebox_boot_nand_external)(void)
if (imx_barebox_boot_nand_external(nfc_base)) {
jump_sdram(nfc_base - ld_var(_text));
- if (readl(MX27_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5))
- pagesize_2k = 1;
- else
- pagesize_2k = 0;
+ pagesize_2k = imx27_pagesize_2k();
imx_nand_load_image((void *)ld_var(_text),
ld_var(_barebox_image_size),
@@ -363,10 +394,7 @@ BARE_INIT_FUNCTION(imx31_barebox_boot_nand_external)(void)
if (imx_barebox_boot_nand_external(nfc_base)) {
jump_sdram(nfc_base - ld_var(_text));
- if (readl(MX31_CCM_BASE_ADDR + MX31_CCM_RCSR) & MX31_RCSR_NFMS)
- pagesize_2k = 1;
- else
- pagesize_2k = 0;
+ pagesize_2k = imx31_pagesize_2k();
imx_nand_load_image((void *)ld_var(_text),
ld_var(_barebox_image_size),
@@ -384,10 +412,7 @@ BARE_INIT_FUNCTION(imx35_barebox_boot_nand_external)(void)
if (imx_barebox_boot_nand_external(nfc_base)) {
jump_sdram(nfc_base - ld_var(_text));
- if (readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR) & (1 << 8))
- pagesize_2k = 1;
- else
- pagesize_2k = 0;
+ pagesize_2k = imx35_pagesize_2k();
imx_nand_load_image((void *)ld_var(_text),
ld_var(_barebox_image_size),
--
1.8.5.2
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 35+ messages in thread* [PATCH 10/22] ARM: i.MX: external NAND boot: create function macro for different SoCs
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (8 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 09/22] ARM: i.MX: external NAND boot: factor out a 2k pagesize detection function Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 15:03 ` [PATCH 11/22] ARM: i.MX: external NAND boot: make it work with relocatable PBL Sascha Hauer
` (11 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/external-nand-boot.c | 112 +++++++--------------------------
1 file changed, 23 insertions(+), 89 deletions(-)
diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c
index a1221c8..4d86ab9 100644
--- a/arch/arm/mach-imx/external-nand-boot.c
+++ b/arch/arm/mach-imx/external-nand-boot.c
@@ -329,95 +329,29 @@ static inline int imx35_pagesize_2k(void)
* NAND. In this case the booting is continued without loading an image from
* NAND. This function needs a stack to be set up.
*/
-#ifdef BROKEN
-BARE_INIT_FUNCTION(imx21_barebox_boot_nand_external)(void)
-{
- unsigned long nfc_base = MX21_NFC_BASE_ADDR;
- int pagesize_2k;
-
- if (imx_barebox_boot_nand_external(nfc_base)) {
- jump_sdram(nfc_base - ld_var(_text));
-
- pagesize_2k = imx21_pagesize_2k();
-
- imx_nand_load_image((void *)ld_var(_text),
- ld_var(barebox_image_size),
- (void *)nfc_base, pagesize_2k);
- }
-
- /* This function doesn't exist yet */
- imx21_barebox_entry(0);
-}
-#endif
-
-BARE_INIT_FUNCTION(imx25_barebox_boot_nand_external)(void)
-{
- unsigned long nfc_base = MX25_NFC_BASE_ADDR;
- int pagesize_2k;
-
- if (imx_barebox_boot_nand_external(nfc_base)) {
- jump_sdram(nfc_base - ld_var(_text));
-
- pagesize_2k = imx25_pagesize_2k();
-
- imx_nand_load_image((void *)ld_var(_text),
- ld_var(_barebox_image_size),
- (void *)nfc_base, pagesize_2k);
- }
-
- imx25_barebox_entry(0);
-}
-
-BARE_INIT_FUNCTION(imx27_barebox_boot_nand_external)(void)
-{
- unsigned long nfc_base = MX27_NFC_BASE_ADDR;
- int pagesize_2k;
-
- if (imx_barebox_boot_nand_external(nfc_base)) {
- jump_sdram(nfc_base - ld_var(_text));
- pagesize_2k = imx27_pagesize_2k();
-
- imx_nand_load_image((void *)ld_var(_text),
- ld_var(_barebox_image_size),
- (void *)nfc_base, pagesize_2k);
- }
-
- imx27_barebox_entry(0);
-}
-
-BARE_INIT_FUNCTION(imx31_barebox_boot_nand_external)(void)
-{
- unsigned long nfc_base = MX31_NFC_BASE_ADDR;
- int pagesize_2k;
-
- if (imx_barebox_boot_nand_external(nfc_base)) {
- jump_sdram(nfc_base - ld_var(_text));
-
- pagesize_2k = imx31_pagesize_2k();
-
- imx_nand_load_image((void *)ld_var(_text),
- ld_var(_barebox_image_size),
- (void *)nfc_base, pagesize_2k);
- }
-
- imx31_barebox_entry(0);
+#define DEFINE_EXTERNAL_NAND_ENTRY(soc) \
+ \
+BARE_INIT_FUNCTION(imx##soc##_barebox_boot_nand_external)(void) \
+{ \
+ unsigned long nfc_base = MX##soc##_NFC_BASE_ADDR; \
+ \
+ if (imx_barebox_boot_nand_external(nfc_base)) { \
+ jump_sdram(nfc_base - ld_var(_text)); \
+ \
+ imx_nand_load_image((void *)ld_var(_text), \
+ ld_var(_barebox_image_size), \
+ (void *)nfc_base, \
+ imx##soc##_pagesize_2k()); \
+ } \
+ \
+ imx##soc##_barebox_entry(0); \
}
-BARE_INIT_FUNCTION(imx35_barebox_boot_nand_external)(void)
-{
- unsigned long nfc_base = MX35_NFC_BASE_ADDR;
- int pagesize_2k;
-
- if (imx_barebox_boot_nand_external(nfc_base)) {
- jump_sdram(nfc_base - ld_var(_text));
-
- pagesize_2k = imx35_pagesize_2k();
-
- imx_nand_load_image((void *)ld_var(_text),
- ld_var(_barebox_image_size),
- (void *)nfc_base, pagesize_2k);
- }
-
- imx35_barebox_entry(0);
-}
+#ifdef BROKEN
+DEFINE_EXTERNAL_NAND_ENTRY(21)
+#endif
+DEFINE_EXTERNAL_NAND_ENTRY(25)
+DEFINE_EXTERNAL_NAND_ENTRY(27)
+DEFINE_EXTERNAL_NAND_ENTRY(31)
+DEFINE_EXTERNAL_NAND_ENTRY(35)
--
1.8.5.2
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^ permalink raw reply [flat|nested] 35+ messages in thread* [PATCH 11/22] ARM: i.MX: external NAND boot: make it work with relocatable PBL
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (9 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 10/22] ARM: i.MX: external NAND boot: create function macro for different SoCs Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 15:03 ` [PATCH 12/22] ARM: dts: Add i.MX27 devicetree files Sascha Hauer
` (10 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
We used to copy the initial binary portion from NFC SRAM to TEXT_BASE
and jumped there. With relocatable PBL TEXT_BASE becomes 0, so this
doesn't work. This is changed to copy the initial binary portion
to the beginning of SDRAM instead.
Tested on Phytec phyCARD-i.MX27 and Karo TX25 with and without
relocatable pbl.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/external-nand-boot.c | 71 +++++++++++++++++++++-------------
1 file changed, 45 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c
index 4d86ab9..a1956f0 100644
--- a/arch/arm/mach-imx/external-nand-boot.c
+++ b/arch/arm/mach-imx/external-nand-boot.c
@@ -236,24 +236,6 @@ void __bare_init imx_nand_load_image(void *dest, int size, void __iomem *base,
}
/*
- * This function assumes the currently running binary has been
- * copied from its current position to an offset. It returns
- * to the calling function - offset.
- * NOTE: The calling function may not return itself since it still
- * works on the old content of the lr register. Only call this
- * from a __noreturn function.
- */
-static __bare_init __naked void jump_sdram(unsigned long offset)
-{
- flush_icache();
-
- __asm__ __volatile__ (
- "sub lr, lr, %0;"
- "mov pc, lr;" : : "r"(offset)
- );
-}
-
-/*
* Load and start barebox from NAND. This function also checks if we are really
* running inside the NFC address space. If not, barebox is started from the
* currently running address without loading anything from NAND.
@@ -332,20 +314,57 @@ static inline int imx35_pagesize_2k(void)
#define DEFINE_EXTERNAL_NAND_ENTRY(soc) \
\
+BARE_INIT_FUNCTION(imx##soc##_boot_nand_external_cont)(void) \
+{ \
+ unsigned long nfc_base = MX##soc##_NFC_BASE_ADDR; \
+ unsigned long sdram = MX##soc##_CSD0_BASE_ADDR; \
+ \
+ imx_nand_load_image((void *)sdram, \
+ ld_var(_barebox_image_size), \
+ (void *)nfc_base, \
+ imx##soc##_pagesize_2k()); \
+ \
+ imx##soc##_barebox_entry(0); \
+} \
+ \
BARE_INIT_FUNCTION(imx##soc##_barebox_boot_nand_external)(void) \
{ \
unsigned long nfc_base = MX##soc##_NFC_BASE_ADDR; \
+ unsigned long sdram = MX##soc##_CSD0_BASE_ADDR; \
+ unsigned long __fn; \
+ u32 r; \
+ u32 *src, *trg; \
+ int i; \
+ void __noreturn (*fn)(void); \
+ \
+ /* skip NAND boot if not running from NFC space */ \
+ r = get_pc(); \
+ if (r < nfc_base || r > nfc_base + 0x800) \
+ imx##soc##_barebox_entry(0); \
+ \
+ src = (unsigned int *)nfc_base; \
+ trg = (unsigned int *)sdram; \
+ \
+ /* \
+ * Copy initial binary portion from NFC SRAM to beginning of \
+ * SDRAM \
+ */ \
+ for (i = 0; i < 0x800 / sizeof(int); i++) \
+ *trg++ = *src++; \
\
- if (imx_barebox_boot_nand_external(nfc_base)) { \
- jump_sdram(nfc_base - ld_var(_text)); \
+ /* The next function we jump to */ \
+ __fn = (unsigned long)imx##soc##_boot_nand_external_cont; \
+ /* mask out TEXT_BASE */ \
+ __fn &= 0x7ff; \
+ /* \
+ * and add sdram base instead where we copied the initial \
+ * binary above \
+ */ \
+ __fn += sdram; \
\
- imx_nand_load_image((void *)ld_var(_text), \
- ld_var(_barebox_image_size), \
- (void *)nfc_base, \
- imx##soc##_pagesize_2k()); \
- } \
+ fn = (void *)__fn; \
\
- imx##soc##_barebox_entry(0); \
+ fn(); \
}
#ifdef BROKEN
--
1.8.5.2
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^ permalink raw reply [flat|nested] 35+ messages in thread* [PATCH 12/22] ARM: dts: Add i.MX27 devicetree files
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (10 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 11/22] ARM: i.MX: external NAND boot: make it work with relocatable PBL Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 16:35 ` Alexander Shiyan
2014-01-17 15:03 ` [PATCH 13/22] ARM: dts: Add Phytec phyCARD-i.MX27 " Sascha Hauer
` (9 subsequent siblings)
21 siblings, 1 reply; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/imx27-pinfunc.h | 526 +++++++++++++++++++++++++
arch/arm/dts/imx27-pingrp.h | 151 +++++++
arch/arm/dts/imx27.dtsi | 505 ++++++++++++++++++++++++
include/dt-bindings/interrupt-controller/irq.h | 19 +
4 files changed, 1201 insertions(+)
create mode 100644 arch/arm/dts/imx27-pinfunc.h
create mode 100644 arch/arm/dts/imx27-pingrp.h
create mode 100644 arch/arm/dts/imx27.dtsi
create mode 100644 include/dt-bindings/interrupt-controller/irq.h
diff --git a/arch/arm/dts/imx27-pinfunc.h b/arch/arm/dts/imx27-pinfunc.h
new file mode 100644
index 0000000..f5387b4
--- /dev/null
+++ b/arch/arm/dts/imx27-pinfunc.h
@@ -0,0 +1,526 @@
+/*
+ * Copyright 2013 Markus Pargmann <mpa@pengutronix.de>, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __DTS_IMX27_PINFUNC_H
+#define __DTS_IMX27_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <pin mux_id>
+ * mux_id consists of
+ * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
+ *
+ * function: 0 - Primary function
+ * 1 - Alternate function
+ * 2 - GPIO
+ * direction: 0 - Input
+ * 1 - Output
+ * gpio_oconf: 0 - A_IN
+ * 1 - B_IN
+ * 2 - C_IN
+ * 3 - Data Register
+ * gpio_iconfa/b: 0 - GPIO_IN
+ * 1 - Interrupt Status Register
+ * 2 - 0
+ * 3 - 1
+ *
+ * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
+ * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin
+ * number on the specific port (between 0 and 31).
+ */
+
+#define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000
+#define MX27_PAD_USBH2_CLK__GPIO1_0 0x00 0x032
+#define MX27_PAD_USBH2_DIR__USBH2_DIR 0x01 0x000
+#define MX27_PAD_USBH2_DIR__GPIO1_1 0x01 0x032
+#define MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x02 0x004
+#define MX27_PAD_USBH2_DATA7__GPIO1_2 0x02 0x032
+#define MX27_PAD_USBH2_NXT__USBH2_NXT 0x03 0x000
+#define MX27_PAD_USBH2_NXT__GPIO1_3 0x03 0x032
+#define MX27_PAD_USBH2_STP__USBH2_STP 0x04 0x004
+#define MX27_PAD_USBH2_STP__GPIO1_4 0x04 0x032
+#define MX27_PAD_LSCLK__LSCLK 0x05 0x004
+#define MX27_PAD_LSCLK__GPIO1_5 0x05 0x032
+#define MX27_PAD_LD0__LD0 0x06 0x004
+#define MX27_PAD_LD0__GPIO1_6 0x06 0x032
+#define MX27_PAD_LD1__LD1 0x07 0x004
+#define MX27_PAD_LD1__GPIO1_7 0x07 0x032
+#define MX27_PAD_LD2__LD2 0x08 0x004
+#define MX27_PAD_LD2__GPIO1_8 0x08 0x032
+#define MX27_PAD_LD3__LD3 0x09 0x004
+#define MX27_PAD_LD3__GPIO1_9 0x09 0x032
+#define MX27_PAD_LD4__LD4 0x0a 0x004
+#define MX27_PAD_LD4__GPIO1_10 0x0a 0x032
+#define MX27_PAD_LD5__LD5 0x0b 0x004
+#define MX27_PAD_LD5__GPIO1_11 0x0b 0x032
+#define MX27_PAD_LD6__LD6 0x0c 0x004
+#define MX27_PAD_LD6__GPIO1_12 0x0c 0x032
+#define MX27_PAD_LD7__LD7 0x0d 0x004
+#define MX27_PAD_LD7__GPIO1_13 0x0d 0x032
+#define MX27_PAD_LD8__LD8 0x0e 0x004
+#define MX27_PAD_LD8__GPIO1_14 0x0e 0x032
+#define MX27_PAD_LD9__LD9 0x0f 0x004
+#define MX27_PAD_LD9__GPIO1_15 0x0f 0x032
+#define MX27_PAD_LD10__LD10 0x10 0x004
+#define MX27_PAD_LD10__GPIO1_16 0x10 0x032
+#define MX27_PAD_LD11__LD11 0x11 0x004
+#define MX27_PAD_LD11__GPIO1_17 0x11 0x032
+#define MX27_PAD_LD12__LD12 0x12 0x004
+#define MX27_PAD_LD12__GPIO1_18 0x12 0x032
+#define MX27_PAD_LD13__LD13 0x13 0x004
+#define MX27_PAD_LD13__GPIO1_19 0x13 0x032
+#define MX27_PAD_LD14__LD14 0x14 0x004
+#define MX27_PAD_LD14__GPIO1_20 0x14 0x032
+#define MX27_PAD_LD15__LD15 0x15 0x004
+#define MX27_PAD_LD15__GPIO1_21 0x15 0x032
+#define MX27_PAD_LD16__LD16 0x16 0x004
+#define MX27_PAD_LD16__GPIO1_22 0x16 0x032
+#define MX27_PAD_LD17__LD17 0x17 0x004
+#define MX27_PAD_LD17__GPIO1_23 0x17 0x032
+#define MX27_PAD_REV__REV 0x18 0x004
+#define MX27_PAD_REV__GPIO1_24 0x18 0x032
+#define MX27_PAD_CLS__CLS 0x19 0x004
+#define MX27_PAD_CLS__GPIO1_25 0x19 0x032
+#define MX27_PAD_PS__PS 0x1a 0x004
+#define MX27_PAD_PS__GPIO1_26 0x1a 0x032
+#define MX27_PAD_SPL_SPR__SPL_SPR 0x1b 0x004
+#define MX27_PAD_SPL_SPR__GPIO1_27 0x1b 0x032
+#define MX27_PAD_HSYNC__HSYNC 0x1c 0x004
+#define MX27_PAD_HSYNC__GPIO1_28 0x1c 0x032
+#define MX27_PAD_VSYNC__VSYNC 0x1d 0x004
+#define MX27_PAD_VSYNC__GPIO1_29 0x1d 0x032
+#define MX27_PAD_CONTRAST__CONTRAST 0x1e 0x004
+#define MX27_PAD_CONTRAST__GPIO1_30 0x1e 0x032
+#define MX27_PAD_OE_ACD__OE_ACD 0x1f 0x004
+#define MX27_PAD_OE_ACD__GPIO1_31 0x1f 0x032
+#define MX27_PAD_UNUSED0__UNUSED0 0x20 0x004
+#define MX27_PAD_UNUSED0__GPIO2_0 0x20 0x032
+#define MX27_PAD_UNUSED1__UNUSED1 0x21 0x004
+#define MX27_PAD_UNUSED1__GPIO2_1 0x21 0x032
+#define MX27_PAD_UNUSED2__UNUSED2 0x22 0x004
+#define MX27_PAD_UNUSED2__GPIO2_2 0x22 0x032
+#define MX27_PAD_UNUSED3__UNUSED3 0x23 0x004
+#define MX27_PAD_UNUSED3__GPIO2_3 0x23 0x032
+#define MX27_PAD_SD2_D0__SD2_D0 0x24 0x004
+#define MX27_PAD_SD2_D0__MSHC_DATA0 0x24 0x005
+#define MX27_PAD_SD2_D0__GPIO2_4 0x24 0x032
+#define MX27_PAD_SD2_D1__SD2_D1 0x25 0x004
+#define MX27_PAD_SD2_D1__MSHC_DATA1 0x25 0x005
+#define MX27_PAD_SD2_D1__GPIO2_5 0x25 0x032
+#define MX27_PAD_SD2_D2__SD2_D2 0x26 0x004
+#define MX27_PAD_SD2_D2__MSHC_DATA2 0x26 0x005
+#define MX27_PAD_SD2_D2__GPIO2_6 0x26 0x032
+#define MX27_PAD_SD2_D3__SD2_D3 0x27 0x004
+#define MX27_PAD_SD2_D3__MSHC_DATA3 0x27 0x005
+#define MX27_PAD_SD2_D3__GPIO2_7 0x27 0x032
+#define MX27_PAD_SD2_CMD__SD2_CMD 0x28 0x004
+#define MX27_PAD_SD2_CMD__MSHC_BS 0x28 0x005
+#define MX27_PAD_SD2_CMD__GPIO2_8 0x28 0x032
+#define MX27_PAD_SD2_CLK__SD2_CLK 0x29 0x004
+#define MX27_PAD_SD2_CLK__MSHC_SCLK 0x29 0x005
+#define MX27_PAD_SD2_CLK__GPIO2_9 0x29 0x032
+#define MX27_PAD_CSI_D0__CSI_D0 0x2a 0x000
+#define MX27_PAD_CSI_D0__UART6_TXD 0x2a 0x005
+#define MX27_PAD_CSI_D0__GPIO2_10 0x2a 0x032
+#define MX27_PAD_CSI_D1__CSI_D1 0x2b 0x000
+#define MX27_PAD_CSI_D1__UART6_RXD 0x2b 0x001
+#define MX27_PAD_CSI_D1__GPIO2_11 0x2b 0x032
+#define MX27_PAD_CSI_D2__CSI_D2 0x2c 0x000
+#define MX27_PAD_CSI_D2__UART6_CTS 0x2c 0x005
+#define MX27_PAD_CSI_D2__GPIO2_12 0x2c 0x032
+#define MX27_PAD_CSI_D3__CSI_D3 0x2d 0x000
+#define MX27_PAD_CSI_D3__UART6_RTS 0x2d 0x001
+#define MX27_PAD_CSI_D3__GPIO2_13 0x2d 0x032
+#define MX27_PAD_CSI_D4__CSI_D4 0x2e 0x000
+#define MX27_PAD_CSI_D4__GPIO2_14 0x2e 0x032
+#define MX27_PAD_CSI_MCLK__CSI_MCLK 0x2f 0x004
+#define MX27_PAD_CSI_MCLK__GPIO2_15 0x2f 0x032
+#define MX27_PAD_CSI_PIXCLK__CSI_PIXCLK 0x30 0x000
+#define MX27_PAD_CSI_PIXCLK__GPIO2_16 0x30 0x032
+#define MX27_PAD_CSI_D5__CSI_D5 0x31 0x000
+#define MX27_PAD_CSI_D5__GPIO2_17 0x31 0x032
+#define MX27_PAD_CSI_D6__CSI_D6 0x32 0x000
+#define MX27_PAD_CSI_D6__UART5_TXD 0x32 0x005
+#define MX27_PAD_CSI_D6__GPIO2_18 0x32 0x032
+#define MX27_PAD_CSI_D7__CSI_D7 0x33 0x000
+#define MX27_PAD_CSI_D7__UART5_RXD 0x33 0x001
+#define MX27_PAD_CSI_D7__GPIO2_19 0x33 0x032
+#define MX27_PAD_CSI_VSYNC__CSI_VSYNC 0x34 0x000
+#define MX27_PAD_CSI_VSYNC__UART5_CTS 0x34 0x005
+#define MX27_PAD_CSI_VSYNC__GPIO2_20 0x34 0x032
+#define MX27_PAD_CSI_HSYNC__CSI_HSYNC 0x35 0x000
+#define MX27_PAD_CSI_HSYNC__UART5_RTS 0x35 0x001
+#define MX27_PAD_CSI_HSYNC__GPIO2_21 0x35 0x032
+#define MX27_PAD_USBH1_SUSP__USBH1_SUSP 0x36 0x004
+#define MX27_PAD_USBH1_SUSP__GPIO2_22 0x36 0x032
+#define MX27_PAD_USB_PWR__USB_PWR 0x37 0x004
+#define MX27_PAD_USB_PWR__GPIO2_23 0x37 0x032
+#define MX27_PAD_USB_OC_B__USB_OC_B 0x38 0x000
+#define MX27_PAD_USB_OC_B__GPIO2_24 0x38 0x032
+#define MX27_PAD_USBH1_RCV__USBH1_RCV 0x39 0x004
+#define MX27_PAD_USBH1_RCV__GPIO2_25 0x39 0x032
+#define MX27_PAD_USBH1_FS__USBH1_FS 0x3a 0x004
+#define MX27_PAD_USBH1_FS__UART4_RTS 0x3a 0x001
+#define MX27_PAD_USBH1_FS__GPIO2_26 0x3a 0x032
+#define MX27_PAD_USBH1_OE_B__USBH1_OE_B 0x3b 0x004
+#define MX27_PAD_USBH1_OE_B__GPIO2_27 0x3b 0x032
+#define MX27_PAD_USBH1_TXDM__USBH1_TXDM 0x3c 0x004
+#define MX27_PAD_USBH1_TXDM__UART4_TXD 0x3c 0x005
+#define MX27_PAD_USBH1_TXDM__GPIO2_28 0x3c 0x032
+#define MX27_PAD_USBH1_TXDP__USBH1_TXDP 0x3d 0x004
+#define MX27_PAD_USBH1_TXDP__UART4_CTS 0x3d 0x005
+#define MX27_PAD_USBH1_TXDP__GPIO2_29 0x3d 0x032
+#define MX27_PAD_USBH1_RXDM__USBH1_RXDM 0x3e 0x004
+#define MX27_PAD_USBH1_RXDM__GPIO2_30 0x3e 0x032
+#define MX27_PAD_USBH1_RXDP__USBH1_RXDP 0x3f 0x004
+#define MX27_PAD_USBH1_RXDP__UART4_RXD 0x3f 0x001
+#define MX27_PAD_USBH1_RXDP__GPIO2_31 0x3f 0x032
+#define MX27_PAD_UNUSED4__UNUSED4 0x40 0x004
+#define MX27_PAD_UNUSED4__GPIO3_0 0x40 0x032
+#define MX27_PAD_UNUSED5__UNUSED5 0x41 0x004
+#define MX27_PAD_UNUSED5__GPIO3_1 0x41 0x032
+#define MX27_PAD_UNUSED6__UNUSED6 0x42 0x004
+#define MX27_PAD_UNUSED6__GPIO3_2 0x42 0x032
+#define MX27_PAD_UNUSED7__UNUSED7 0x43 0x004
+#define MX27_PAD_UNUSED7__GPIO3_3 0x43 0x032
+#define MX27_PAD_UNUSED8__UNUSED8 0x44 0x004
+#define MX27_PAD_UNUSED8__GPIO3_4 0x44 0x032
+#define MX27_PAD_I2C2_SDA__I2C2_SDA 0x45 0x004
+#define MX27_PAD_I2C2_SDA__GPIO3_5 0x45 0x032
+#define MX27_PAD_I2C2_SCL__I2C2_SCL 0x46 0x004
+#define MX27_PAD_I2C2_SCL__GPIO3_6 0x46 0x032
+#define MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x47 0x004
+#define MX27_PAD_USBOTG_DATA5__GPIO3_7 0x47 0x032
+#define MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x48 0x004
+#define MX27_PAD_USBOTG_DATA6__GPIO3_8 0x48 0x032
+#define MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x49 0x004
+#define MX27_PAD_USBOTG_DATA0__GPIO3_9 0x49 0x032
+#define MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x4a 0x004
+#define MX27_PAD_USBOTG_DATA2__GPIO3_10 0x4a 0x032
+#define MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x4b 0x004
+#define MX27_PAD_USBOTG_DATA1__GPIO3_11 0x4b 0x032
+#define MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x4c 0x004
+#define MX27_PAD_USBOTG_DATA4__GPIO3_12 0x4c 0x032
+#define MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x4d 0x004
+#define MX27_PAD_USBOTG_DATA3__GPIO3_13 0x4d 0x032
+#define MX27_PAD_TOUT__TOUT 0x4e 0x004
+#define MX27_PAD_TOUT__GPIO3_14 0x4e 0x032
+#define MX27_PAD_TIN__TIN 0x4f 0x000
+#define MX27_PAD_TIN__GPIO3_15 0x4f 0x032
+#define MX27_PAD_SSI4_FS__SSI4_FS 0x50 0x004
+#define MX27_PAD_SSI4_FS__GPIO3_16 0x50 0x032
+#define MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x51 0x004
+#define MX27_PAD_SSI4_RXDAT__GPIO3_17 0x51 0x032
+#define MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x52 0x004
+#define MX27_PAD_SSI4_TXDAT__GPIO3_18 0x52 0x032
+#define MX27_PAD_SSI4_CLK__SSI4_CLK 0x53 0x004
+#define MX27_PAD_SSI4_CLK__GPIO3_19 0x53 0x032
+#define MX27_PAD_SSI1_FS__SSI1_FS 0x54 0x004
+#define MX27_PAD_SSI1_FS__GPIO3_20 0x54 0x032
+#define MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x55 0x004
+#define MX27_PAD_SSI1_RXDAT__GPIO3_21 0x55 0x032
+#define MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x56 0x004
+#define MX27_PAD_SSI1_TXDAT__GPIO3_22 0x56 0x032
+#define MX27_PAD_SSI1_CLK__SSI1_CLK 0x57 0x004
+#define MX27_PAD_SSI1_CLK__GPIO3_23 0x57 0x032
+#define MX27_PAD_SSI2_FS__SSI2_FS 0x58 0x004
+#define MX27_PAD_SSI2_FS__GPT5_TOUT 0x58 0x005
+#define MX27_PAD_SSI2_FS__GPIO3_24 0x58 0x032
+#define MX27_PAD_SSI2_RXDAT__SSI2_RXDAT 0x59 0x004
+#define MX27_PAD_SSI2_RXDAT__GPTS_TIN 0x59 0x001
+#define MX27_PAD_SSI2_RXDAT__GPIO3_25 0x59 0x032
+#define MX27_PAD_SSI2_TXDAT__SSI2_TXDAT 0x5a 0x004
+#define MX27_PAD_SSI2_TXDAT__GPT4_TOUT 0x5a 0x005
+#define MX27_PAD_SSI2_TXDAT__GPIO3_26 0x5a 0x032
+#define MX27_PAD_SSI2_CLK__SSI2_CLK 0x5b 0x004
+#define MX27_PAD_SSI2_CLK__GPT4_TIN 0x5b 0x001
+#define MX27_PAD_SSI2_CLK__GPIO3_27 0x5b 0x032
+#define MX27_PAD_SSI3_FS__SSI3_FS 0x5c 0x004
+#define MX27_PAD_SSI3_FS__SLCDC2_D0 0x5c 0x001
+#define MX27_PAD_SSI3_FS__GPIO3_28 0x5c 0x032
+#define MX27_PAD_SSI3_RXDAT__SSI3_RXDAT 0x5d 0x004
+#define MX27_PAD_SSI3_RXDAT__SLCDC2_RS 0x5d 0x001
+#define MX27_PAD_SSI3_RXDAT__GPIO3_29 0x5d 0x032
+#define MX27_PAD_SSI3_TXDAT__SSI3_TXDAT 0x5e 0x004
+#define MX27_PAD_SSI3_TXDAT__SLCDC2_CS 0x5e 0x001
+#define MX27_PAD_SSI3_TXDAT__GPIO3_30 0x5e 0x032
+#define MX27_PAD_SSI3_CLK__SSI3_CLK 0x5f 0x004
+#define MX27_PAD_SSI3_CLK__SLCDC2_CLK 0x5f 0x001
+#define MX27_PAD_SSI3_CLK__GPIO3_31 0x5f 0x032
+#define MX27_PAD_SD3_CMD__SD3_CMD 0x60 0x004
+#define MX27_PAD_SD3_CMD__FEC_TXD0 0x60 0x006
+#define MX27_PAD_SD3_CMD__GPIO4_0 0x60 0x032
+#define MX27_PAD_SD3_CLK__SD3_CLK 0x61 0x004
+#define MX27_PAD_SD3_CLK__ETMTRACEPKT15 0x61 0x005
+#define MX27_PAD_SD3_CLK__FEC_TXD1 0x61 0x006
+#define MX27_PAD_SD3_CLK__GPIO4_1 0x61 0x032
+#define MX27_PAD_ATA_DATA0__ATA_DATA0 0x62 0x004
+#define MX27_PAD_ATA_DATA0__SD3_D0 0x62 0x005
+#define MX27_PAD_ATA_DATA0__FEC_TXD2 0x62 0x006
+#define MX27_PAD_ATA_DATA0__GPIO4_2 0x62 0x032
+#define MX27_PAD_ATA_DATA1__ATA_DATA1 0x63 0x004
+#define MX27_PAD_ATA_DATA1__SD3_D1 0x63 0x005
+#define MX27_PAD_ATA_DATA1__FEC_TXD3 0x63 0x006
+#define MX27_PAD_ATA_DATA1__GPIO4_3 0x63 0x032
+#define MX27_PAD_ATA_DATA2__ATA_DATA2 0x64 0x004
+#define MX27_PAD_ATA_DATA2__SD3_D2 0x64 0x005
+#define MX27_PAD_ATA_DATA2__FEC_RX_ER 0x64 0x002
+#define MX27_PAD_ATA_DATA2__GPIO4_4 0x64 0x032
+#define MX27_PAD_ATA_DATA3__ATA_DATA3 0x65 0x004
+#define MX27_PAD_ATA_DATA3__SD3_D3 0x65 0x005
+#define MX27_PAD_ATA_DATA3__FEC_RXD1 0x65 0x002
+#define MX27_PAD_ATA_DATA3__GPIO4_5 0x65 0x032
+#define MX27_PAD_ATA_DATA4__ATA_DATA4 0x66 0x004
+#define MX27_PAD_ATA_DATA4__ETMTRACEPKT14 0x66 0x005
+#define MX27_PAD_ATA_DATA4__FEC_RXD2 0x66 0x002
+#define MX27_PAD_ATA_DATA4__GPIO4_6 0x66 0x032
+#define MX27_PAD_ATA_DATA5__ATA_DATA5 0x67 0x004
+#define MX27_PAD_ATA_DATA5__ETMTRACEPKT13 0x67 0x005
+#define MX27_PAD_ATA_DATA5__FEC_RXD3 0x67 0x002
+#define MX27_PAD_ATA_DATA5__GPIO4_7 0x67 0x032
+#define MX27_PAD_ATA_DATA6__ATA_DATA6 0x68 0x004
+#define MX27_PAD_ATA_DATA6__FEC_MDIO 0x68 0x005
+#define MX27_PAD_ATA_DATA6__GPIO4_8 0x68 0x032
+#define MX27_PAD_ATA_DATA7__ATA_DATA7 0x69 0x004
+#define MX27_PAD_ATA_DATA7__ETMTRACEPKT12 0x69 0x005
+#define MX27_PAD_ATA_DATA7__FEC_MDC 0x69 0x006
+#define MX27_PAD_ATA_DATA7__GPIO4_9 0x69 0x032
+#define MX27_PAD_ATA_DATA8__ATA_DATA8 0x6a 0x004
+#define MX27_PAD_ATA_DATA8__ETMTRACEPKT11 0x6a 0x005
+#define MX27_PAD_ATA_DATA8__FEC_CRS 0x6a 0x002
+#define MX27_PAD_ATA_DATA8__GPIO4_10 0x6a 0x032
+#define MX27_PAD_ATA_DATA9__ATA_DATA9 0x6b 0x004
+#define MX27_PAD_ATA_DATA9__ETMTRACEPKT10 0x6b 0x005
+#define MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x6b 0x002
+#define MX27_PAD_ATA_DATA9__GPIO4_11 0x6b 0x032
+#define MX27_PAD_ATA_DATA10__ATA_DATA10 0x6c 0x004
+#define MX27_PAD_ATA_DATA10__ETMTRACEPKT9 0x6c 0x005
+#define MX27_PAD_ATA_DATA10__FEC_RXD0 0x6c 0x002
+#define MX27_PAD_ATA_DATA10__GPIO4_12 0x6c 0x032
+#define MX27_PAD_ATA_DATA11__ATA_DATA11 0x6d 0x004
+#define MX27_PAD_ATA_DATA11__ETMTRACEPKT8 0x6d 0x005
+#define MX27_PAD_ATA_DATA11__FEC_RX_DV 0x6d 0x002
+#define MX27_PAD_ATA_DATA11__GPIO4_13 0x6d 0x032
+#define MX27_PAD_ATA_DATA12__ATA_DATA12 0x6e 0x004
+#define MX27_PAD_ATA_DATA12__ETMTRACEPKT7 0x6e 0x005
+#define MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x6e 0x002
+#define MX27_PAD_ATA_DATA12__GPIO4_14 0x6e 0x032
+#define MX27_PAD_ATA_DATA13__ATA_DATA13 0x6f 0x004
+#define MX27_PAD_ATA_DATA13__ETMTRACEPKT6 0x6f 0x005
+#define MX27_PAD_ATA_DATA13__FEC_COL 0x6f 0x002
+#define MX27_PAD_ATA_DATA13__GPIO4_15 0x6f 0x032
+#define MX27_PAD_ATA_DATA14__ATA_DATA14 0x70 0x004
+#define MX27_PAD_ATA_DATA14__ETMTRACEPKT5 0x70 0x005
+#define MX27_PAD_ATA_DATA14__FEC_TX_ER 0x70 0x006
+#define MX27_PAD_ATA_DATA14__GPIO4_16 0x70 0x032
+#define MX27_PAD_I2C_DATA__I2C_DATA 0x71 0x004
+#define MX27_PAD_I2C_DATA__GPIO4_17 0x71 0x032
+#define MX27_PAD_I2C_CLK__I2C_CLK 0x72 0x004
+#define MX27_PAD_I2C_CLK__GPIO4_18 0x72 0x032
+#define MX27_PAD_CSPI2_SS2__CSPI2_SS2 0x73 0x004
+#define MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x73 0x005
+#define MX27_PAD_CSPI2_SS2__GPIO4_19 0x73 0x032
+#define MX27_PAD_CSPI2_SS1__CSPI2_SS1 0x74 0x004
+#define MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x74 0x005
+#define MX27_PAD_CSPI2_SS1__GPIO4_20 0x74 0x032
+#define MX27_PAD_CSPI2_SS0__CSPI2_SS0 0x75 0x004
+#define MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x75 0x005
+#define MX27_PAD_CSPI2_SS0__GPIO4_21 0x75 0x032
+#define MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x76 0x004
+#define MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x76 0x005
+#define MX27_PAD_CSPI2_SCLK__GPIO4_22 0x76 0x032
+#define MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x77 0x004
+#define MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x77 0x005
+#define MX27_PAD_CSPI2_MISO__GPIO4_23 0x77 0x032
+#define MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x78 0x004
+#define MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x78 0x005
+#define MX27_PAD_CSPI2_MOSI__GPIO4_24 0x78 0x032
+#define MX27_PAD_CSPI1_RDY__CSPI1_RDY 0x79 0x000
+#define MX27_PAD_CSPI1_RDY__GPIO4_25 0x79 0x032
+#define MX27_PAD_CSPI1_SS2__CSPI1_SS2 0x7a 0x004
+#define MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x7a 0x005
+#define MX27_PAD_CSPI1_SS2__GPIO4_26 0x7a 0x032
+#define MX27_PAD_CSPI1_SS1__CSPI1_SS1 0x7b 0x004
+#define MX27_PAD_CSPI1_SS1__GPIO4_27 0x7b 0x032
+#define MX27_PAD_CSPI1_SS0__CSPI1_SS0 0x7c 0x004
+#define MX27_PAD_CSPI1_SS0__GPIO4_28 0x7c 0x032
+#define MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x7d 0x004
+#define MX27_PAD_CSPI1_SCLK__GPIO4_29 0x7d 0x032
+#define MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x7e 0x004
+#define MX27_PAD_CSPI1_MISO__GPIO4_30 0x7e 0x032
+#define MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x7f 0x004
+#define MX27_PAD_CSPI1_MOSI__GPIO4_31 0x7f 0x032
+#define MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x80 0x000
+#define MX27_PAD_USBOTG_NXT__KP_COL6A 0x80 0x005
+#define MX27_PAD_USBOTG_NXT__GPIO5_0 0x80 0x032
+#define MX27_PAD_USBOTG_STP__USBOTG_STP 0x81 0x004
+#define MX27_PAD_USBOTG_STP__KP_ROW6A 0x81 0x005
+#define MX27_PAD_USBOTG_STP__GPIO5_1 0x81 0x032
+#define MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x82 0x000
+#define MX27_PAD_USBOTG_DIR__KP_ROW7A 0x82 0x005
+#define MX27_PAD_USBOTG_DIR__GPIO5_2 0x82 0x032
+#define MX27_PAD_UART2_CTS__UART2_CTS 0x83 0x004
+#define MX27_PAD_UART2_CTS__KP_COL7 0x83 0x005
+#define MX27_PAD_UART2_CTS__GPIO5_3 0x83 0x032
+#define MX27_PAD_UART2_RTS__UART2_RTS 0x84 0x000
+#define MX27_PAD_UART2_RTS__KP_ROW7 0x84 0x005
+#define MX27_PAD_UART2_RTS__GPIO5_4 0x84 0x032
+#define MX27_PAD_PWMO__PWMO 0x85 0x004
+#define MX27_PAD_PWMO__GPIO5_5 0x85 0x032
+#define MX27_PAD_UART2_TXD__UART2_TXD 0x86 0x004
+#define MX27_PAD_UART2_TXD__KP_COL6 0x86 0x005
+#define MX27_PAD_UART2_TXD__GPIO5_6 0x86 0x032
+#define MX27_PAD_UART2_RXD__UART2_RXD 0x87 0x000
+#define MX27_PAD_UART2_RXD__KP_ROW6 0x87 0x005
+#define MX27_PAD_UART2_RXD__GPIO5_7 0x87 0x032
+#define MX27_PAD_UART3_TXD__UART3_TXD 0x88 0x004
+#define MX27_PAD_UART3_TXD__GPIO5_8 0x88 0x032
+#define MX27_PAD_UART3_RXD__UART3_RXD 0x89 0x000
+#define MX27_PAD_UART3_RXD__GPIO5_9 0x89 0x032
+#define MX27_PAD_UART3_CTS__UART3_CTS 0x8a 0x004
+#define MX27_PAD_UART3_CTS__GPIO5_10 0x8a 0x032
+#define MX27_PAD_UART3_RTS__UART3_RTS 0x8b 0x000
+#define MX27_PAD_UART3_RTS__GPIO5_11 0x8b 0x032
+#define MX27_PAD_UART1_TXD__UART1_TXD 0x8c 0x004
+#define MX27_PAD_UART1_TXD__GPIO5_12 0x8c 0x032
+#define MX27_PAD_UART1_RXD__UART1_RXD 0x8d 0x000
+#define MX27_PAD_UART1_RXD__GPIO5_13 0x8d 0x032
+#define MX27_PAD_UART1_CTS__UART1_CTS 0x8e 0x004
+#define MX27_PAD_UART1_CTS__GPIO5_14 0x8e 0x032
+#define MX27_PAD_UART1_RTS__UART1_RTS 0x8f 0x000
+#define MX27_PAD_UART1_RTS__GPIO5_15 0x8f 0x032
+#define MX27_PAD_RTCK__RTCK 0x90 0x004
+#define MX27_PAD_RTCK__OWIRE 0x90 0x005
+#define MX27_PAD_RTCK__GPIO5_16 0x90 0x032
+#define MX27_PAD_RESET_OUT_B__RESET_OUT_B 0x91 0x004
+#define MX27_PAD_RESET_OUT_B__GPIO5_17 0x91 0x032
+#define MX27_PAD_SD1_D0__SD1_D0 0x92 0x004
+#define MX27_PAD_SD1_D0__CSPI3_MISO 0x92 0x001
+#define MX27_PAD_SD1_D0__GPIO5_18 0x92 0x032
+#define MX27_PAD_SD1_D1__SD1_D1 0x93 0x004
+#define MX27_PAD_SD1_D1__GPIO5_19 0x93 0x032
+#define MX27_PAD_SD1_D2__SD1_D2 0x94 0x004
+#define MX27_PAD_SD1_D2__GPIO5_20 0x94 0x032
+#define MX27_PAD_SD1_D3__SD1_D3 0x95 0x004
+#define MX27_PAD_SD1_D3__CSPI3_SS 0x95 0x005
+#define MX27_PAD_SD1_D3__GPIO5_21 0x95 0x032
+#define MX27_PAD_SD1_CMD__SD1_CMD 0x96 0x004
+#define MX27_PAD_SD1_CMD__CSPI3_MOSI 0x96 0x005
+#define MX27_PAD_SD1_CMD__GPIO5_22 0x96 0x032
+#define MX27_PAD_SD1_CLK__SD1_CLK 0x97 0x004
+#define MX27_PAD_SD1_CLK__CSPI3_SCLK 0x97 0x005
+#define MX27_PAD_SD1_CLK__GPIO5_23 0x97 0x032
+#define MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x98 0x000
+#define MX27_PAD_USBOTG_CLK__GPIO5_24 0x98 0x032
+#define MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x99 0x004
+#define MX27_PAD_USBOTG_DATA7__GPIO5_25 0x99 0x032
+#define MX27_PAD_UNUSED9__UNUSED9 0x9a 0x004
+#define MX27_PAD_UNUSED9__GPIO5_26 0x9a 0x032
+#define MX27_PAD_UNUSED10__UNUSED10 0x9b 0x004
+#define MX27_PAD_UNUSED10__GPIO5_27 0x9b 0x032
+#define MX27_PAD_UNUSED11__UNUSED11 0x9c 0x004
+#define MX27_PAD_UNUSED11__GPIO5_28 0x9c 0x032
+#define MX27_PAD_UNUSED12__UNUSED12 0x9d 0x004
+#define MX27_PAD_UNUSED12__GPIO5_29 0x9d 0x032
+#define MX27_PAD_UNUSED13__UNUSED13 0x9e 0x004
+#define MX27_PAD_UNUSED13__GPIO5_30 0x9e 0x032
+#define MX27_PAD_UNUSED14__UNUSED14 0x9f 0x004
+#define MX27_PAD_UNUSED14__GPIO5_31 0x9f 0x032
+#define MX27_PAD_NFRB__NFRB 0xa0 0x000
+#define MX27_PAD_NFRB__ETMTRACEPKT3 0xa0 0x005
+#define MX27_PAD_NFRB__GPIO6_0 0xa0 0x032
+#define MX27_PAD_NFCLE__NFCLE 0xa1 0x004
+#define MX27_PAD_NFCLE__ETMTRACEPKT0 0xa1 0x005
+#define MX27_PAD_NFCLE__GPIO6_1 0xa1 0x032
+#define MX27_PAD_NFWP_B__NFWP_B 0xa2 0x004
+#define MX27_PAD_NFWP_B__ETMTRACEPKT1 0xa2 0x005
+#define MX27_PAD_NFWP_B__GPIO6_2 0xa2 0x032
+#define MX27_PAD_NFCE_B__NFCE_B 0xa3 0x004
+#define MX27_PAD_NFCE_B__ETMTRACEPKT2 0xa3 0x005
+#define MX27_PAD_NFCE_B__GPIO6_3 0xa3 0x032
+#define MX27_PAD_NFALE__NFALE 0xa4 0x004
+#define MX27_PAD_NFALE__ETMPIPESTAT0 0xa4 0x005
+#define MX27_PAD_NFALE__GPIO6_4 0xa4 0x032
+#define MX27_PAD_NFRE_B__NFRE_B 0xa5 0x004
+#define MX27_PAD_NFRE_B__ETMPIPESTAT1 0xa5 0x005
+#define MX27_PAD_NFRE_B__GPIO6_5 0xa5 0x032
+#define MX27_PAD_NFWE_B__NFWE_B 0xa6 0x004
+#define MX27_PAD_NFWE_B__ETMPIPESTAT2 0xa6 0x005
+#define MX27_PAD_NFWE_B__GPIO6_6 0xa6 0x032
+#define MX27_PAD_PC_POE__PC_POE 0xa7 0x004
+#define MX27_PAD_PC_POE__ATA_BUFFER_EN 0xa7 0x005
+#define MX27_PAD_PC_POE__GPIO6_7 0xa7 0x032
+#define MX27_PAD_PC_RW_B__PC_RW_B 0xa8 0x004
+#define MX27_PAD_PC_RW_B__ATA_IORDY 0xa8 0x001
+#define MX27_PAD_PC_RW_B__GPIO6_8 0xa8 0x032
+#define MX27_PAD_IOIS16__IOIS16 0xa9 0x000
+#define MX27_PAD_IOIS16__ATA_INTRQ 0xa9 0x001
+#define MX27_PAD_IOIS16__GPIO6_9 0xa9 0x032
+#define MX27_PAD_PC_RST__PC_RST 0xaa 0x004
+#define MX27_PAD_PC_RST__ATA_RESET_B 0xaa 0x005
+#define MX27_PAD_PC_RST__GPIO6_10 0xaa 0x032
+#define MX27_PAD_PC_BVD2__PC_BVD2 0xab 0x000
+#define MX27_PAD_PC_BVD2__ATA_DMACK 0xab 0x005
+#define MX27_PAD_PC_BVD2__GPIO6_11 0xab 0x032
+#define MX27_PAD_PC_BVD1__PC_BVD1 0xac 0x000
+#define MX27_PAD_PC_BVD1__ATA_DMARQ 0xac 0x001
+#define MX27_PAD_PC_BVD1__GPIO6_12 0xac 0x032
+#define MX27_PAD_PC_VS2__PC_VS2 0xad 0x000
+#define MX27_PAD_PC_VS2__ATA_DA0 0xad 0x005
+#define MX27_PAD_PC_VS2__GPIO6_13 0xad 0x032
+#define MX27_PAD_PC_VS1__PC_VS1 0xae 0x000
+#define MX27_PAD_PC_VS1__ATA_DA1 0xae 0x005
+#define MX27_PAD_PC_VS1__GPIO6_14 0xae 0x032
+#define MX27_PAD_CLKO__CLKO 0xaf 0x004
+#define MX27_PAD_CLKO__GPIO6_15 0xaf 0x032
+#define MX27_PAD_PC_PWRON__PC_PWRON 0xb0 0x000
+#define MX27_PAD_PC_PWRON__ATA_DA2 0xb0 0x005
+#define MX27_PAD_PC_PWRON__GPIO6_16 0xb0 0x032
+#define MX27_PAD_PC_READY__PC_READY 0xb1 0x000
+#define MX27_PAD_PC_READY__ATA_CS0 0xb1 0x005
+#define MX27_PAD_PC_READY__GPIO6_17 0xb1 0x032
+#define MX27_PAD_PC_WAIT_B__PC_WAIT_B 0xb2 0x000
+#define MX27_PAD_PC_WAIT_B__ATA_CS1 0xb2 0x005
+#define MX27_PAD_PC_WAIT_B__GPIO6_18 0xb2 0x032
+#define MX27_PAD_PC_CD2_B__PC_CD2_B 0xb3 0x000
+#define MX27_PAD_PC_CD2_B__ATA_DIOW 0xb3 0x005
+#define MX27_PAD_PC_CD2_B__GPIO6_19 0xb3 0x032
+#define MX27_PAD_PC_CD1_B__PC_CD1_B 0xb4 0x000
+#define MX27_PAD_PC_CD1_B__ATA_DIOR 0xb4 0x005
+#define MX27_PAD_PC_CD1_B__GPIO6_20 0xb4 0x032
+#define MX27_PAD_CS4_B__CS4_B 0xb5 0x004
+#define MX27_PAD_CS4_B__ETMTRACESYNC 0xb5 0x005
+#define MX27_PAD_CS4_B__GPIO6_21 0xb5 0x032
+#define MX27_PAD_CS5_B__CS5_B 0xb6 0x004
+#define MX27_PAD_CS5_B__ETMTRACECLK 0xb6 0x005
+#define MX27_PAD_CS5_B__GPIO6_22 0xb6 0x032
+#define MX27_PAD_ATA_DATA15__ATA_DATA15 0xb7 0x004
+#define MX27_PAD_ATA_DATA15__ETMTRACEPKT4 0xb7 0x005
+#define MX27_PAD_ATA_DATA15__FEC_TX_EN 0xb7 0x006
+#define MX27_PAD_ATA_DATA15__GPIO6_23 0xb7 0x032
+#define MX27_PAD_UNUSED15__UNUSED15 0xb8 0x004
+#define MX27_PAD_UNUSED15__GPIO6_24 0xb8 0x032
+#define MX27_PAD_UNUSED16__UNUSED16 0xb9 0x004
+#define MX27_PAD_UNUSED16__GPIO6_25 0xb9 0x032
+#define MX27_PAD_UNUSED17__UNUSED17 0xba 0x004
+#define MX27_PAD_UNUSED17__GPIO6_26 0xba 0x032
+#define MX27_PAD_UNUSED18__UNUSED18 0xbb 0x004
+#define MX27_PAD_UNUSED18__GPIO6_27 0xbb 0x032
+#define MX27_PAD_UNUSED19__UNUSED19 0xbc 0x004
+#define MX27_PAD_UNUSED19__GPIO6_28 0xbc 0x032
+#define MX27_PAD_UNUSED20__UNUSED20 0xbd 0x004
+#define MX27_PAD_UNUSED20__GPIO6_29 0xbd 0x032
+#define MX27_PAD_UNUSED21__UNUSED21 0xbe 0x004
+#define MX27_PAD_UNUSED21__GPIO6_30 0xbe 0x032
+#define MX27_PAD_UNUSED22__UNUSED22 0xbf 0x004
+#define MX27_PAD_UNUSED22__GPIO6_31 0xbf 0x032
+
+#endif /* __DTS_IMX27_PINFUNC_H */
diff --git a/arch/arm/dts/imx27-pingrp.h b/arch/arm/dts/imx27-pingrp.h
new file mode 100644
index 0000000..57ca02f
--- /dev/null
+++ b/arch/arm/dts/imx27-pingrp.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright 2013 Markus Pargmann <mpa@pengutronix.de>, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __DTS_IMX27_PINGRP_H
+#define __DTS_IMX27_PINGRP_H
+
+#include "imx27-pinfunc.h"
+
+#define MX27_CSPI1_PINGRP1 \
+ MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 \
+ MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 \
+ MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
+
+#define MX27_CSPI2_PINGRP1 \
+ MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 \
+ MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 \
+ MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
+
+#define MX27_CSPI3_PINGRP1 \
+ MX27_PAD_SD1_CLK__CSPI3_SCLK 0x0 \
+ MX27_PAD_SD1_D0__CSPI3_MISO 0x0 \
+ MX27_PAD_SD1_CMD__CSPI3_MOSI 0x0
+
+#define MX27_FB_PINGRP1 \
+ MX27_PAD_CLS__CLS 0x0 \
+ MX27_PAD_CONTRAST__CONTRAST 0x0 \
+ MX27_PAD_LD0__LD0 0x0 \
+ MX27_PAD_LD1__LD1 0x0 \
+ MX27_PAD_LD2__LD2 0x0 \
+ MX27_PAD_LD3__LD3 0x0 \
+ MX27_PAD_LD4__LD4 0x0 \
+ MX27_PAD_LD5__LD5 0x0 \
+ MX27_PAD_LD6__LD6 0x0 \
+ MX27_PAD_LD7__LD7 0x0 \
+ MX27_PAD_LD8__LD8 0x0 \
+ MX27_PAD_LD9__LD9 0x0 \
+ MX27_PAD_LD10__LD10 0x0 \
+ MX27_PAD_LD11__LD11 0x0 \
+ MX27_PAD_LD12__LD12 0x0 \
+ MX27_PAD_LD13__LD13 0x0 \
+ MX27_PAD_LD14__LD14 0x0 \
+ MX27_PAD_LD15__LD15 0x0 \
+ MX27_PAD_LD16__LD16 0x0 \
+ MX27_PAD_LD17__LD17 0x0 \
+ MX27_PAD_LSCLK__LSCLK 0x0 \
+ MX27_PAD_OE_ACD__OE_ACD 0x0 \
+ MX27_PAD_PS__PS 0x0 \
+ MX27_PAD_REV__REV 0x0 \
+ MX27_PAD_SPL_SPR__SPL_SPR 0x0 \
+ MX27_PAD_HSYNC__HSYNC 0x0 \
+ MX27_PAD_VSYNC__VSYNC 0x0
+
+#define MX27_FEC1_PINGRP1 \
+ MX27_PAD_SD3_CMD__FEC_TXD0 0x0 \
+ MX27_PAD_SD3_CLK__FEC_TXD1 0x0 \
+ MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 \
+ MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 \
+ MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 \
+ MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 \
+ MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 \
+ MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 \
+ MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 \
+ MX27_PAD_ATA_DATA7__FEC_MDC 0x0 \
+ MX27_PAD_ATA_DATA8__FEC_CRS 0x0 \
+ MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 \
+ MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 \
+ MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 \
+ MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 \
+ MX27_PAD_ATA_DATA13__FEC_COL 0x0 \
+ MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 \
+ MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+
+#define MX27_I2C1_PINGRP1 \
+ MX27_PAD_I2C_DATA__I2C_DATA 0x0 \
+ MX27_PAD_I2C_CLK__I2C_CLK 0x0
+
+#define MX27_I2C2_PINGRP1 \
+ MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 \
+ MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+
+#define MX27_NFC_PINGRP1 \
+ MX27_PAD_NFRB__NFRB 0x0 \
+ MX27_PAD_NFCLE__NFCLE 0x0 \
+ MX27_PAD_NFWP_B__NFWP_B 0x0 \
+ MX27_PAD_NFCE_B__NFCE_B 0x0 \
+ MX27_PAD_NFALE__NFALE 0x0 \
+ MX27_PAD_NFRE_B__NFRE_B 0x0 \
+ MX27_PAD_NFWE_B__NFWE_B 0x0
+
+#define MX27_OWIRE1_PINGRP1 \
+ MX27_PAD_RTCK__OWIRE 0x0
+
+#define MX27_PWM_PINGRP1 \
+ MX27_PAD_PWMO__PWMO 0x0
+
+#define MX27_SDHC1_PINGRP1 \
+ MX27_PAD_SD1_CLK__SD1_CLK 0x0 \
+ MX27_PAD_SD1_CMD__SD1_CMD 0x0 \
+ MX27_PAD_SD1_D0__SD1_D0 0x0 \
+ MX27_PAD_SD1_D1__SD1_D1 0x0 \
+ MX27_PAD_SD1_D2__SD1_D2 0x0 \
+ MX27_PAD_SD1_D3__SD1_D3 0x0
+
+#define MX27_SDHC2_PINGRP1 \
+ MX27_PAD_SD2_CLK__SD2_CLK 0x0 \
+ MX27_PAD_SD2_CMD__SD2_CMD 0x0 \
+ MX27_PAD_SD2_D0__SD2_D0 0x0 \
+ MX27_PAD_SD2_D1__SD2_D1 0x0 \
+ MX27_PAD_SD2_D2__SD2_D2 0x0 \
+ MX27_PAD_SD2_D3__SD2_D3 0x0
+
+#define MX27_SDHC3_PINGRP1 \
+ MX27_PAD_SD3_CLK__SD3_CLK 0x0 \
+ MX27_PAD_SD3_CMD__SD3_CMD 0x0 \
+ MX27_PAD_SD3_D0__SD3_D0 0x0 \
+ MX27_PAD_SD3_D1__SD3_D1 0x0 \
+ MX27_PAD_SD3_D2__SD3_D2 0x0 \
+ MX27_PAD_SD3_D3__SD3_D3 0x0
+
+#define MX27_UART1_PINGRP1 \
+ MX27_PAD_UART1_TXD__UART1_TXD 0x0 \
+ MX27_PAD_UART1_RXD__UART1_RXD 0x0
+
+#define MX27_UART1_RTSCTS_PINGRP1 \
+ MX27_PAD_UART1_CTS__UART1_CTS 0x0 \
+ MX27_PAD_UART1_RTS__UART1_RTS 0x0
+
+#define MX27_UART2_PINGRP1 \
+ MX27_PAD_UART2_TXD__UART2_TXD 0x0 \
+ MX27_PAD_UART2_RXD__UART2_RXD 0x0
+
+#define MX27_UART2_RTSCTS_PINGRP1 \
+ MX27_PAD_UART2_CTS__UART2_CTS 0x0 \
+ MX27_PAD_UART2_RTS__UART2_RTS 0x0
+
+#define MX27_UART3_PINGRP1 \
+ MX27_PAD_UART3_TXD__UART3_TXD 0x0 \
+ MX27_PAD_UART3_RXD__UART3_RXD 0x0
+
+#define MX27_UART3_RTSCTS_PINGRP1 \
+ MX27_PAD_UART3_CTS__UART3_CTS 0x0 \
+ MX27_PAD_UART3_RTS__UART3_RTS 0x0
+
+#endif /* __DTS_IMX27_PINGRP_H */
diff --git a/arch/arm/dts/imx27.dtsi b/arch/arm/dts/imx27.dtsi
new file mode 100644
index 0000000..7e98966
--- /dev/null
+++ b/arch/arm/dts/imx27.dtsi
@@ -0,0 +1,505 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "skeleton.dtsi"
+#include "imx27-pingrp.h"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ gpio5 = &gpio6;
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ spi0 = &cspi1;
+ spi1 = &cspi2;
+ spi2 = &cspi3;
+ };
+
+ aitc: aitc-interrupt-controller@e0000000 {
+ compatible = "fsl,imx27-aitc", "fsl,avic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x10040000 0x1000>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ osc26m {
+ compatible = "fsl,imx-osc26m", "fixed-clock";
+ clock-frequency = <26000000>;
+ };
+ };
+
+ cpus {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ cpu: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,arm926ej-s";
+ operating-points = <
+ /* kHz uV */
+ 266000 1300000
+ 399000 1450000
+ >;
+ clock-latency = <62500>;
+ clocks = <&clks 18>;
+ voltage-tolerance = <5>;
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&aitc>;
+ ranges;
+
+ aipi@10000000 { /* AIPI1 */
+ compatible = "fsl,aipi-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x10000000 0x20000>;
+ ranges;
+
+ dma: dma@10001000 {
+ compatible = "fsl,imx27-dma";
+ reg = <0x10001000 0x1000>;
+ interrupts = <32>;
+ clocks = <&clks 50>, <&clks 70>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <1>;
+ #dma-channels = <16>;
+ };
+
+ wdog: wdog@10002000 {
+ compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
+ reg = <0x10002000 0x1000>;
+ interrupts = <27>;
+ clocks = <&clks 74>;
+ };
+
+ gpt1: timer@10003000 {
+ compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
+ reg = <0x10003000 0x1000>;
+ interrupts = <26>;
+ clocks = <&clks 46>, <&clks 61>;
+ clock-names = "ipg", "per";
+ };
+
+ gpt2: timer@10004000 {
+ compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
+ reg = <0x10004000 0x1000>;
+ interrupts = <25>;
+ clocks = <&clks 45>, <&clks 61>;
+ clock-names = "ipg", "per";
+ };
+
+ gpt3: timer@10005000 {
+ compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
+ reg = <0x10005000 0x1000>;
+ interrupts = <24>;
+ clocks = <&clks 44>, <&clks 61>;
+ clock-names = "ipg", "per";
+ };
+
+ pwm: pwm@10006000 {
+ #pwm-cells = <2>;
+ compatible = "fsl,imx27-pwm";
+ reg = <0x10006000 0x1000>;
+ interrupts = <23>;
+ clocks = <&clks 34>, <&clks 61>;
+ clock-names = "ipg", "per";
+ };
+
+ kpp: kpp@10008000 {
+ compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
+ reg = <0x10008000 0x1000>;
+ interrupts = <21>;
+ clocks = <&clks 37>;
+ status = "disabled";
+ };
+
+ owire: owire@10009000 {
+ compatible = "fsl,imx27-owire", "fsl,imx21-owire";
+ reg = <0x10009000 0x1000>;
+ clocks = <&clks 35>;
+ status = "disabled";
+ };
+
+ uart1: serial@1000a000 {
+ compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+ reg = <0x1000a000 0x1000>;
+ interrupts = <20>;
+ clocks = <&clks 81>, <&clks 61>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart2: serial@1000b000 {
+ compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+ reg = <0x1000b000 0x1000>;
+ interrupts = <19>;
+ clocks = <&clks 80>, <&clks 61>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart3: serial@1000c000 {
+ compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+ reg = <0x1000c000 0x1000>;
+ interrupts = <18>;
+ clocks = <&clks 79>, <&clks 61>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart4: serial@1000d000 {
+ compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+ reg = <0x1000d000 0x1000>;
+ interrupts = <17>;
+ clocks = <&clks 78>, <&clks 61>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ cspi1: cspi@1000e000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx27-cspi";
+ reg = <0x1000e000 0x1000>;
+ interrupts = <16>;
+ clocks = <&clks 53>, <&clks 60>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ cspi2: cspi@1000f000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx27-cspi";
+ reg = <0x1000f000 0x1000>;
+ interrupts = <15>;
+ clocks = <&clks 52>, <&clks 60>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ssi1: ssi@10010000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
+ reg = <0x10010000 0x1000>;
+ interrupts = <14>;
+ clocks = <&clks 26>;
+ dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
+ dma-names = "rx0", "tx0", "rx1", "tx1";
+ fsl,fifo-depth = <8>;
+ status = "disabled";
+ };
+
+ ssi2: ssi@10011000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
+ reg = <0x10011000 0x1000>;
+ interrupts = <13>;
+ clocks = <&clks 25>;
+ dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
+ dma-names = "rx0", "tx0", "rx1", "tx1";
+ fsl,fifo-depth = <8>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@10012000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
+ reg = <0x10012000 0x1000>;
+ interrupts = <12>;
+ clocks = <&clks 40>;
+ status = "disabled";
+ };
+
+ sdhci1: sdhci@10013000 {
+ compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
+ reg = <0x10013000 0x1000>;
+ interrupts = <11>;
+ clocks = <&clks 30>, <&clks 60>;
+ clock-names = "ipg", "per";
+ dmas = <&dma 7>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ sdhci2: sdhci@10014000 {
+ compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
+ reg = <0x10014000 0x1000>;
+ interrupts = <10>;
+ clocks = <&clks 29>, <&clks 60>;
+ clock-names = "ipg", "per";
+ dmas = <&dma 6>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ iomuxc: iomuxc@10015000 {
+ compatible = "fsl,imx27-iomuxc";
+ reg = <0x10015000 0x600>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio1: gpio@10015000 {
+ compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+ reg = <0x10015000 0x100>;
+ interrupts = <8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@10015100 {
+ compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+ reg = <0x10015100 0x100>;
+ interrupts = <8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@10015200 {
+ compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+ reg = <0x10015200 0x100>;
+ interrupts = <8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@10015300 {
+ compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+ reg = <0x10015300 0x100>;
+ interrupts = <8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@10015400 {
+ compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+ reg = <0x10015400 0x100>;
+ interrupts = <8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio6: gpio@10015500 {
+ compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+ reg = <0x10015500 0x100>;
+ interrupts = <8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ audmux: audmux@10016000 {
+ compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
+ reg = <0x10016000 0x1000>;
+ clocks = <&clks 0>;
+ clock-names = "audmux";
+ status = "disabled";
+ };
+
+ cspi3: cspi@10017000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx27-cspi";
+ reg = <0x10017000 0x1000>;
+ interrupts = <6>;
+ clocks = <&clks 51>, <&clks 60>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ gpt4: timer@10019000 {
+ compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
+ reg = <0x10019000 0x1000>;
+ interrupts = <4>;
+ clocks = <&clks 43>, <&clks 61>;
+ clock-names = "ipg", "per";
+ };
+
+ gpt5: timer@1001a000 {
+ compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
+ reg = <0x1001a000 0x1000>;
+ interrupts = <3>;
+ clocks = <&clks 42>, <&clks 61>;
+ clock-names = "ipg", "per";
+ };
+
+ uart5: serial@1001b000 {
+ compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+ reg = <0x1001b000 0x1000>;
+ interrupts = <49>;
+ clocks = <&clks 77>, <&clks 61>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart6: serial@1001c000 {
+ compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+ reg = <0x1001c000 0x1000>;
+ interrupts = <48>;
+ clocks = <&clks 78>, <&clks 61>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ i2c2: i2c@1001d000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
+ reg = <0x1001d000 0x1000>;
+ interrupts = <1>;
+ clocks = <&clks 39>;
+ status = "disabled";
+ };
+
+ sdhci3: sdhci@1001e000 {
+ compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
+ reg = <0x1001e000 0x1000>;
+ interrupts = <9>;
+ clocks = <&clks 28>, <&clks 60>;
+ clock-names = "ipg", "per";
+ dmas = <&dma 36>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ gpt6: timer@1001f000 {
+ compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
+ reg = <0x1001f000 0x1000>;
+ interrupts = <2>;
+ clocks = <&clks 41>, <&clks 61>;
+ clock-names = "ipg", "per";
+ };
+ };
+
+ aipi@10020000 { /* AIPI2 */
+ compatible = "fsl,aipi-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x10020000 0x20000>;
+ ranges;
+
+ fb: fb@10021000 {
+ compatible = "fsl,imx27-fb", "fsl,imx21-fb";
+ interrupts = <61>;
+ reg = <0x10021000 0x1000>;
+ clocks = <&clks 36>, <&clks 65>, <&clks 59>;
+ clock-names = "ipg", "ahb", "per";
+ status = "disabled";
+ };
+
+ coda: coda@10023000 {
+ compatible = "fsl,imx27-vpu";
+ reg = <0x10023000 0x0200>;
+ interrupts = <53>;
+ clocks = <&clks 57>, <&clks 66>;
+ clock-names = "per", "ahb";
+ iram = <&iram>;
+ };
+
+ sahara2: sahara@10025000 {
+ compatible = "fsl,imx27-sahara";
+ reg = <0x10025000 0x1000>;
+ interrupts = <59>;
+ clocks = <&clks 32>, <&clks 64>;
+ clock-names = "ipg", "ahb";
+ };
+
+ clks: ccm@10027000{
+ compatible = "fsl,imx27-ccm";
+ reg = <0x10027000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ iim: iim@10028000 {
+ compatible = "fsl,imx27-iim";
+ reg = <0x10028000 0x1000>;
+ interrupts = <62>;
+ clocks = <&clks 38>;
+ };
+
+ fec: ethernet@1002b000 {
+ compatible = "fsl,imx27-fec";
+ reg = <0x1002b000 0x4000>;
+ interrupts = <50>;
+ clocks = <&clks 48>, <&clks 67>;
+ clock-names = "ipg", "ahb";
+ status = "disabled";
+ };
+ };
+
+ nfc: nand@d8000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,imx27-nand";
+ reg = <0xd8000000 0x1000>;
+ interrupts = <29>;
+ clocks = <&clks 54>;
+ status = "disabled";
+ };
+
+ weim: weim@d8002000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,imx27-weim";
+ reg = <0xd8002000 0x1000>;
+ clocks = <&clks 0>;
+ ranges = <
+ 0 0 0xc0000000 0x08000000
+ 1 0 0xc8000000 0x08000000
+ 2 0 0xd0000000 0x02000000
+ 3 0 0xd2000000 0x02000000
+ 4 0 0xd4000000 0x02000000
+ 5 0 0xd6000000 0x02000000
+ >;
+ status = "disabled";
+ };
+
+ iram: iram@ffff4c00 {
+ compatible = "mmio-sram";
+ reg = <0xffff4c00 0xb400>;
+ };
+ };
+};
diff --git a/include/dt-bindings/interrupt-controller/irq.h b/include/dt-bindings/interrupt-controller/irq.h
new file mode 100644
index 0000000..33a1003
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/irq.h
@@ -0,0 +1,19 @@
+/*
+ * This header provides constants for most IRQ bindings.
+ *
+ * Most IRQ bindings include a flags cell as part of the IRQ specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
+
+#define IRQ_TYPE_NONE 0
+#define IRQ_TYPE_EDGE_RISING 1
+#define IRQ_TYPE_EDGE_FALLING 2
+#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH 4
+#define IRQ_TYPE_LEVEL_LOW 8
+
+#endif
--
1.8.5.2
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 12/22] ARM: dts: Add i.MX27 devicetree files
2014-01-17 15:03 ` [PATCH 12/22] ARM: dts: Add i.MX27 devicetree files Sascha Hauer
@ 2014-01-17 16:35 ` Alexander Shiyan
0 siblings, 0 replies; 35+ messages in thread
From: Alexander Shiyan @ 2014-01-17 16:35 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
Пятница, 17 января 2014, 16:03 +01:00 от Sascha Hauer <s.hauer@pengutronix.de>:
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/dts/imx27-pinfunc.h | 526 +++++++++++++++++++++++++
> arch/arm/dts/imx27-pingrp.h | 151 +++++++
> arch/arm/dts/imx27.dtsi | 505 ++++++++++++++++++++++++
> include/dt-bindings/interrupt-controller/irq.h | 19 +
> 4 files changed, 1201 insertions(+)
> create mode 100644 arch/arm/dts/imx27-pinfunc.h
> create mode 100644 arch/arm/dts/imx27-pingrp.h
> create mode 100644 arch/arm/dts/imx27.dtsi
> create mode 100644 include/dt-bindings/interrupt-controller/irq.h
AFAIK, we already have include/dt-bindings/interrupt-controller/irq.h
with the i.MX51 series update.
---
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 13/22] ARM: dts: Add Phytec phyCARD-i.MX27 devicetree files
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (11 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 12/22] ARM: dts: Add i.MX27 devicetree files Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 16:26 ` Alexander Shiyan
2014-01-17 15:03 ` [PATCH 14/22] ARM: i.MX: external NAND boot: pass boarddata Sascha Hauer
` (8 subsequent siblings)
21 siblings, 1 reply; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/imx27-phytec-phycard-s-rdk.dts | 139 ++++++++++++++++++++++++++++
arch/arm/dts/imx27-phytec-phycard-s-som.dts | 60 ++++++++++++
3 files changed, 201 insertions(+)
create mode 100644 arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
create mode 100644 arch/arm/dts/imx27-phytec-phycard-s-som.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bc314e9..4e875c6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -2,6 +2,8 @@ dtb-$(CONFIG_ARCH_AM33XX) += \
am335x-bone.dtb \
am335x-boneblack.dtb \
am335x-phytec-phycore.dtb
+dtb-$(CONFIG_ARCH_IMX27) += imx27-phytec-phycard-s-rdk.dtb \
+ imx27-phytec-phycard-s-som.dtb
dtb-$(CONFIG_ARCH_IMX51) += imx51-babbage.dtb \
imx51-genesi-efika-sb.dtb
dtb-$(CONFIG_ARCH_IMX53) += imx53-qsb.dtb \
diff --git a/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
new file mode 100644
index 0000000..0d65023
--- /dev/null
+++ b/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
@@ -0,0 +1,139 @@
+/*
+ * Copyright 2012 Markus Pargmann, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx27-phytec-phycard-s-som.dts"
+
+/ {
+ model = "Phytec pca100 rapid development kit";
+ compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27";
+
+ display: display {
+ model = "Primeview-PD050VL1";
+ native-mode = <&timing0>;
+ bits-per-pixel = <16>; /* non-standard but required */
+ fsl,pcr = <0xf0c88080>; /* non-standard but required */
+ display-timings {
+ timing0: 640x480 {
+ hactive = <640>;
+ vactive = <480>;
+ hback-porch = <112>;
+ hfront-porch = <36>;
+ hsync-len = <32>;
+ vback-porch = <33>;
+ vfront-porch = <33>;
+ vsync-len = <2>;
+ clock-frequency = <25000000>;
+ };
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_3v3: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+};
+
+&fb {
+ display = <&display>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+
+ adc@64 {
+ compatible = "maxim,max1037";
+ vcc-supply = <®_3v3>;
+ reg = <0x64>;
+ };
+};
+
+&iomuxc {
+ imx27-phycard-s-rdk {
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <MX27_I2C2_PINGRP1>;
+ };
+
+ pinctrl_owire1: owire1grp {
+ fsl,pins = <MX27_OWIRE1_PINGRP1>;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX27_UART1_PINGRP1
+ MX27_UART1_RTSCTS_PINGRP1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX27_UART2_PINGRP1
+ MX27_UART2_RTSCTS_PINGRP1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX27_UART3_PINGRP1
+ MX27_UART3_RTSCTS_PINGRP1
+ >;
+ };
+ };
+};
+
+&owire {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_owire1>;
+ status = "okay";
+};
+
+&sdhci2 {
+ cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart1 {
+ fsl,uart-has-rtscts;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ fsl,uart-has-rtscts;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ fsl,uart-has-rtscts;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/dts/imx27-phytec-phycard-s-som.dts
new file mode 100644
index 0000000..db8c095
--- /dev/null
+++ b/arch/arm/dts/imx27-phytec-phycard-s-som.dts
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
+ * and Markus Pargmann, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx27.dtsi"
+
+/ {
+ model = "Phytec pca100";
+ compatible = "phytec,imx27-pca100", "fsl,imx27";
+
+ memory {
+ reg = <0xa0000000 0x08000000>; /* 128MB */
+ };
+};
+
+&cspi1 {
+ fsl,spi-num-chipselects = <2>;
+ cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
+ <&gpio4 27 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&iomuxc {
+ imx27-phycard-s-som {
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <MX27_FEC1_PINGRP1>;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <MX27_I2C2_PINGRP1>;
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ at24@52 {
+ compatible = "at,24c32";
+ pagesize = <32>;
+ reg = <0x52>;
+ };
+};
--
1.8.5.2
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 13/22] ARM: dts: Add Phytec phyCARD-i.MX27 devicetree files
2014-01-17 15:03 ` [PATCH 13/22] ARM: dts: Add Phytec phyCARD-i.MX27 " Sascha Hauer
@ 2014-01-17 16:26 ` Alexander Shiyan
2014-01-17 17:56 ` Sascha Hauer
0 siblings, 1 reply; 35+ messages in thread
From: Alexander Shiyan @ 2014-01-17 16:26 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
Пятница, 17 января 2014, 16:03 +01:00 от Sascha Hauer <s.hauer@pengutronix.de>:
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
...
> +&cspi1 {
> + fsl,spi-num-chipselects = <2>;
> + cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
> + <&gpio4 27 GPIO_ACTIVE_HIGH>;
Both ACTIVE_HIGH? Really?
---
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 13/22] ARM: dts: Add Phytec phyCARD-i.MX27 devicetree files
2014-01-17 16:26 ` Alexander Shiyan
@ 2014-01-17 17:56 ` Sascha Hauer
0 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 17:56 UTC (permalink / raw)
To: Alexander Shiyan; +Cc: barebox
On Fri, Jan 17, 2014 at 08:26:02PM +0400, Alexander Shiyan wrote:
> Пятница, 17 января 2014, 16:03 +01:00 от Sascha Hauer <s.hauer@pengutronix.de>:
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ...
> > +&cspi1 {
> > + fsl,spi-num-chipselects = <2>;
> > + cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
> > + <&gpio4 27 GPIO_ACTIVE_HIGH>;
>
> Both ACTIVE_HIGH? Really?
Probably this is wrong. I copied the files from the kernel, it must be
wrong there aswell. I'll have a look before applying these.
Sascha
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 14/22] ARM: i.MX: external NAND boot: pass boarddata
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (12 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 13/22] ARM: dts: Add Phytec phyCARD-i.MX27 " Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 15:03 ` [PATCH 15/22] pinctrl: Add pinctrl driver for i.MX1/21/27 Sascha Hauer
` (7 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/eukrea_cpuimx25/lowlevel.c | 2 +-
arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S | 1 +
arch/arm/boards/eukrea_cpuimx35/lowlevel.c | 2 +-
arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S | 1 +
arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S | 1 +
arch/arm/boards/guf-cupid/lowlevel.c | 2 +-
arch/arm/boards/guf-neso/lowlevel.c | 2 +-
arch/arm/boards/karo-tx25/lowlevel.c | 2 +-
arch/arm/boards/pcm037/lowlevel.c | 2 +-
arch/arm/boards/pcm038/lowlevel.c | 2 +-
arch/arm/boards/pcm043/lowlevel.c | 2 +-
arch/arm/boards/phycard-i.MX27/lowlevel.c | 2 +-
arch/arm/mach-imx/external-nand-boot.c | 14 ++++++++------
arch/arm/mach-imx/include/mach/imx-nand.h | 10 +++++-----
14 files changed, 25 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
index 11d990d..07659f5 100644
--- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
@@ -131,7 +131,7 @@ void __bare_init __naked barebox_arm_reset_vector(void)
/* setup a stack to be able to call imx25_barebox_boot_nand_external() */
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
- imx25_barebox_boot_nand_external();
+ imx25_barebox_boot_nand_external(0);
#endif
out:
imx25_barebox_entry(0);
diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
index a85b00d..ae1391c 100644
--- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
+++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
@@ -127,6 +127,7 @@ barebox_arm_reset_vector:
/* Setup a temporary stack in SDRAM */
ldr sp, =MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 4;
+ mov r0, #0
b imx27_barebox_boot_nand_external
#endif /* CONFIG_NAND_IMX_BOOT */
diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
index a667e4c..d03e110 100644
--- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
@@ -140,7 +140,7 @@ void __bare_init __naked barebox_arm_reset_vector(void)
/* setup a stack to be able to call imx35_barebox_boot_nand_external() */
arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
- imx35_barebox_boot_nand_external();
+ imx35_barebox_boot_nand_external(0);
#endif
out:
imx35_barebox_entry(0);
diff --git a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
index 174262d..8446c6f 100644
--- a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
@@ -101,6 +101,7 @@ barebox_arm_reset_vector:
/* Setup a temporary stack in SRAM */
ldr sp, =MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 4
+ mov r0, #0
b imx25_barebox_boot_nand_external
#endif /* CONFIG_NAND_IMX_BOOT */
diff --git a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
index 2844465..cb9ed0a 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
@@ -158,6 +158,7 @@ barebox_arm_reset_vector:
/* Setup a temporary stack in internal SRAM */
ldr sp, =MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 4
+ mov r0, #0
b imx35_barebox_boot_nand_external
#endif /* CONFIG_NAND_IMX_BOOT */
diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c
index d5298c1..d5dce16 100644
--- a/arch/arm/boards/guf-cupid/lowlevel.c
+++ b/arch/arm/boards/guf-cupid/lowlevel.c
@@ -316,7 +316,7 @@ void __bare_init __naked barebox_arm_reset_vector(void)
/* setup a stack to be able to call imx35_barebox_boot_nand_external() */
arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
- imx35_barebox_boot_nand_external();
+ imx35_barebox_boot_nand_external(0);
#endif
out:
imx35_barebox_entry(0);
diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c
index 386751d..c3323ee 100644
--- a/arch/arm/boards/guf-neso/lowlevel.c
+++ b/arch/arm/boards/guf-neso/lowlevel.c
@@ -90,7 +90,7 @@ void __bare_init __naked barebox_arm_reset_vector(void)
/* setup a stack to be able to call imx27_barebox_boot_nand_external() */
arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8);
- imx27_barebox_boot_nand_external();
+ imx27_barebox_boot_nand_external(0);
#endif
out:
imx27_barebox_entry(0);
diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c
index 742100d..11f4138 100644
--- a/arch/arm/boards/karo-tx25/lowlevel.c
+++ b/arch/arm/boards/karo-tx25/lowlevel.c
@@ -161,7 +161,7 @@ void __bare_init __naked barebox_arm_reset_vector(void)
/* setup a stack to be able to call imx25_barebox_boot_nand_external() */
arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 8);
- imx25_barebox_boot_nand_external();
+ imx25_barebox_boot_nand_external(0);
#endif
out:
imx25_barebox_entry(0);
diff --git a/arch/arm/boards/pcm037/lowlevel.c b/arch/arm/boards/pcm037/lowlevel.c
index b81a24f..ae2d8c0 100644
--- a/arch/arm/boards/pcm037/lowlevel.c
+++ b/arch/arm/boards/pcm037/lowlevel.c
@@ -129,7 +129,7 @@ void __bare_init __naked barebox_arm_reset_vector(void)
/* setup a stack to be able to call imx31_barebox_boot_nand_external() */
arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12);
- imx31_barebox_boot_nand_external();
+ imx31_barebox_boot_nand_external(0);
#else
imx31_barebox_entry(0);
#endif
diff --git a/arch/arm/boards/pcm038/lowlevel.c b/arch/arm/boards/pcm038/lowlevel.c
index 0ea2939..bb948f1 100644
--- a/arch/arm/boards/pcm038/lowlevel.c
+++ b/arch/arm/boards/pcm038/lowlevel.c
@@ -97,7 +97,7 @@ void __bare_init __naked barebox_arm_reset_vector(void)
/* setup a stack to be able to call mx27_barebox_boot_nand_external() */
arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8);
- imx27_barebox_boot_nand_external();
+ imx27_barebox_boot_nand_external(0);
#endif
out:
imx27_barebox_entry(0);
diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c
index ebd6b29..64b0382 100644
--- a/arch/arm/boards/pcm043/lowlevel.c
+++ b/arch/arm/boards/pcm043/lowlevel.c
@@ -192,7 +192,7 @@ void __bare_init __naked barebox_arm_reset_vector(void)
/* setup a stack to be able to call imx35_barebox_boot_nand_external() */
arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
- imx35_barebox_boot_nand_external();
+ imx35_barebox_boot_nand_external(0);
#endif
out:
imx35_barebox_entry(0);
diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel.c b/arch/arm/boards/phycard-i.MX27/lowlevel.c
index 9f5dfff..33de1c0 100644
--- a/arch/arm/boards/phycard-i.MX27/lowlevel.c
+++ b/arch/arm/boards/phycard-i.MX27/lowlevel.c
@@ -100,7 +100,7 @@ void __bare_init __naked barebox_arm_reset_vector(void)
sdram_init();
#ifdef CONFIG_NAND_IMX_BOOT
- imx27_barebox_boot_nand_external();
+ imx27_barebox_boot_nand_external(0);
#else
imx27_barebox_entry(0);
#endif
diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c
index a1956f0..7623c07 100644
--- a/arch/arm/mach-imx/external-nand-boot.c
+++ b/arch/arm/mach-imx/external-nand-boot.c
@@ -314,7 +314,8 @@ static inline int imx35_pagesize_2k(void)
#define DEFINE_EXTERNAL_NAND_ENTRY(soc) \
\
-BARE_INIT_FUNCTION(imx##soc##_boot_nand_external_cont)(void) \
+BARE_INIT_FUNCTION(imx##soc##_boot_nand_external_cont) \
+ (uint32_t boarddata) \
{ \
unsigned long nfc_base = MX##soc##_NFC_BASE_ADDR; \
unsigned long sdram = MX##soc##_CSD0_BASE_ADDR; \
@@ -324,10 +325,11 @@ BARE_INIT_FUNCTION(imx##soc##_boot_nand_external_cont)(void) \
(void *)nfc_base, \
imx##soc##_pagesize_2k()); \
\
- imx##soc##_barebox_entry(0); \
+ imx##soc##_barebox_entry(boarddata); \
} \
\
-BARE_INIT_FUNCTION(imx##soc##_barebox_boot_nand_external)(void) \
+BARE_INIT_FUNCTION(imx##soc##_barebox_boot_nand_external) \
+ (uint32_t boarddata) \
{ \
unsigned long nfc_base = MX##soc##_NFC_BASE_ADDR; \
unsigned long sdram = MX##soc##_CSD0_BASE_ADDR; \
@@ -335,12 +337,12 @@ BARE_INIT_FUNCTION(imx##soc##_barebox_boot_nand_external)(void) \
u32 r; \
u32 *src, *trg; \
int i; \
- void __noreturn (*fn)(void); \
+ void __noreturn (*fn)(uint32_t); \
\
/* skip NAND boot if not running from NFC space */ \
r = get_pc(); \
if (r < nfc_base || r > nfc_base + 0x800) \
- imx##soc##_barebox_entry(0); \
+ imx##soc##_barebox_entry(boarddata); \
\
src = (unsigned int *)nfc_base; \
trg = (unsigned int *)sdram; \
@@ -364,7 +366,7 @@ BARE_INIT_FUNCTION(imx##soc##_barebox_boot_nand_external)(void) \
\
fn = (void *)__fn; \
\
- fn(); \
+ fn(boarddata); \
}
#ifdef BROKEN
diff --git a/arch/arm/mach-imx/include/mach/imx-nand.h b/arch/arm/mach-imx/include/mach/imx-nand.h
index 9e6416e..972a0da 100644
--- a/arch/arm/mach-imx/include/mach/imx-nand.h
+++ b/arch/arm/mach-imx/include/mach/imx-nand.h
@@ -3,11 +3,11 @@
#include <linux/mtd/mtd.h>
-void imx21_barebox_boot_nand_external(void);
-void imx25_barebox_boot_nand_external(void);
-void imx27_barebox_boot_nand_external(void);
-void imx31_barebox_boot_nand_external(void);
-void imx35_barebox_boot_nand_external(void);
+void imx21_barebox_boot_nand_external(uint32_t boarddata);
+void imx25_barebox_boot_nand_external(uint32_t boarddata);
+void imx27_barebox_boot_nand_external(uint32_t boarddata);
+void imx31_barebox_boot_nand_external(uint32_t boarddata);
+void imx35_barebox_boot_nand_external(uint32_t boarddata);
void imx_nand_set_layout(int writesize, int datawidth);
struct imx_nand_platform_data {
--
1.8.5.2
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^ permalink raw reply [flat|nested] 35+ messages in thread* [PATCH 15/22] pinctrl: Add pinctrl driver for i.MX1/21/27
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (13 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 14/22] ARM: i.MX: external NAND boot: pass boarddata Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 15:13 ` Alexander Shiyan
2014-01-17 15:03 ` [PATCH 16/22] ARM: i.MX clocksource: return successful for multiple instances Sascha Hauer
` (6 subsequent siblings)
21 siblings, 1 reply; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
This turns the legacy iomux-v1 support into a full pinctrl
driver.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/imx-iomux-v1.c | 198 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 199 insertions(+)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index c6bb51c..7390971 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -8,6 +8,7 @@ config PINCTRL
support but instead provide their own SoC specific APIs
config PINCTRL_IMX_IOMUX_V1
+ select PINCTRL if OFDEVICE
bool
help
This iomux controller is found on i.MX1,21,27.
diff --git a/drivers/pinctrl/imx-iomux-v1.c b/drivers/pinctrl/imx-iomux-v1.c
index f8f9061..16415c2 100644
--- a/drivers/pinctrl/imx-iomux-v1.c
+++ b/drivers/pinctrl/imx-iomux-v1.c
@@ -1,5 +1,8 @@
#include <common.h>
#include <io.h>
+#include <init.h>
+#include <malloc.h>
+#include <pinctrl.h>
#include <mach/iomux-v1.h>
/*
@@ -29,6 +32,11 @@
static void __iomem *iomuxv1_base;
+struct imx_iomux_v1 {
+ void __iomem *base;
+ struct pinctrl_device pinctrl;
+};
+
void imx_gpio_mode(int gpio_mode)
{
unsigned int pin = gpio_mode & GPIO_PIN_MASK;
@@ -114,3 +122,193 @@ void imx_iomuxv1_init(void __iomem *base)
{
iomuxv1_base = base;
}
+
+/*
+ * MUX_ID format defines
+ */
+#define MX1_MUX_FUNCTION(val) (BIT(0) & val)
+#define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
+#define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
+#define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
+#define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
+#define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
+
+#define MX1_PORT_STRIDE 0x100
+
+/*
+ * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX
+ * control register are seperated into function, output configuration, input
+ * configuration A, input configuration B, GPIO in use and data direction.
+ *
+ * Those controls that are represented by 1 bit have a direct mapping between
+ * bit position and pin id. If they are represented by 2 bit, the lower 16 pins
+ * are in the first register and the upper 16 pins in the second (next)
+ * register. pin_id is stored in bit (pin_id%16)*2 and the bit above.
+ */
+
+/*
+ * Calculates the register offset from a pin_id
+ */
+static void __iomem *imx1_mem(struct imx_iomux_v1 *iomux, unsigned int pin_id)
+{
+ unsigned int port = pin_id / 32;
+ return iomux->base + port * MX1_PORT_STRIDE;
+}
+
+/*
+ * Write to a register with 2 bits per pin. The function will automatically
+ * use the next register if the pin is managed in the second register.
+ */
+static void imx1_write_2bit(struct imx_iomux_v1 *iomux, unsigned int pin_id,
+ u32 value, u32 reg_offset)
+{
+ void __iomem *reg = imx1_mem(iomux, pin_id) + reg_offset;
+ int offset = (pin_id % 16) * 2; /* offset, regardless of register used */
+ int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */
+ u32 old_val;
+ u32 new_val;
+
+ dev_dbg(iomux->pinctrl.dev, "write: register 0x%p offset %d value 0x%x\n",
+ reg, offset, value);
+
+ /* Use the next register if the pin's port pin number is >=16 */
+ if (pin_id % 32 >= 16)
+ reg += 0x04;
+
+ /* Get current state of pins */
+ old_val = readl(reg);
+ old_val &= mask;
+
+ new_val = value & 0x3; /* Make sure value is really 2 bit */
+ new_val <<= offset;
+ new_val |= old_val;/* Set new state for pin_id */
+
+ writel(new_val, reg);
+}
+
+static void imx1_write_bit(struct imx_iomux_v1 *iomux, unsigned int pin_id,
+ u32 value, u32 reg_offset)
+{
+ void __iomem *reg = imx1_mem(iomux, pin_id) + reg_offset;
+ int offset = pin_id % 32;
+ int mask = ~BIT_MASK(offset);
+ u32 old_val;
+ u32 new_val;
+
+ /* Get current state of pins */
+ old_val = readl(reg);
+ old_val &= mask;
+
+ new_val = value & 0x1; /* Make sure value is really 1 bit */
+ new_val <<= offset;
+ new_val |= old_val;/* Set new state for pin_id */
+
+ writel(new_val, reg);
+}
+
+static int imx_iomux_v1_set_state(struct pinctrl_device *pdev, struct device_node *np)
+{
+ struct imx_iomux_v1 *iomux = container_of(pdev, struct imx_iomux_v1, pinctrl);
+ const __be32 *list;
+ int npins, size, i;
+
+ dev_dbg(iomux->pinctrl.dev, "set state: %s\n", np->full_name);
+
+ list = of_get_property(np, "fsl,pins", &size);
+ if (!list)
+ return -EINVAL;
+
+ npins = size / 12;
+
+ for (i = 0; i < npins; i++) {
+ unsigned int pin_id = be32_to_cpu(*list++);
+ unsigned int mux = be32_to_cpu(*list++);
+ unsigned int config = be32_to_cpu(*list++);
+ unsigned int afunction = MX1_MUX_FUNCTION(mux);
+ unsigned int gpio_in_use = MX1_MUX_GPIO(mux);
+ unsigned int direction = MX1_MUX_DIR(mux);
+ unsigned int gpio_oconf = MX1_MUX_OCONF(mux);
+ unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux);
+ unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux);
+
+ dev_dbg(pdev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n",
+ np->full_name, pin_id, afunction, gpio_in_use,
+ direction, gpio_oconf, gpio_iconfa,
+ gpio_iconfb);
+
+ imx1_write_bit(iomux, pin_id, gpio_in_use, GIUS);
+ imx1_write_bit(iomux, pin_id, direction, DDIR);
+
+ if (gpio_in_use) {
+ imx1_write_2bit(iomux, pin_id, gpio_oconf, OCR1);
+ imx1_write_2bit(iomux, pin_id, gpio_iconfa, ICONFA1);
+ imx1_write_2bit(iomux, pin_id, gpio_iconfb, ICONFB1);
+ } else {
+ imx1_write_bit(iomux, pin_id, afunction, GPR);
+ }
+
+ imx1_write_bit(iomux, pin_id, config & 0x01, PUEN);
+ }
+
+ return 0;
+}
+
+static struct pinctrl_ops imx_iomux_v1_ops = {
+ .set_state = imx_iomux_v1_set_state,
+};
+
+static int imx_pinctrl_dt(struct device_d *dev, void __iomem *base)
+{
+ struct imx_iomux_v1 *iomux;
+ int ret;
+
+ iomux = xzalloc(sizeof(*iomux));
+
+ iomux->base = base;
+
+ iomux->pinctrl.dev = dev;
+ iomux->pinctrl.ops = &imx_iomux_v1_ops;
+
+ ret = pinctrl_register(&iomux->pinctrl);
+ if (ret)
+ free(iomux);
+
+ return ret;
+}
+
+static int imx_iomux_v1_probe(struct device_d *dev)
+{
+ int ret = 0;
+
+ if (iomuxv1_base)
+ return -EBUSY;
+
+ iomuxv1_base = dev_get_mem_region(dev, 0);
+
+ ret = of_platform_populate(dev->device_node, NULL, NULL);
+
+ if (IS_ENABLED(CONFIG_PINCTRL) && dev->device_node)
+ ret = imx_pinctrl_dt(dev, iomuxv1_base);
+
+ return ret;
+}
+
+static __maybe_unused struct of_device_id imx_iomux_v1_dt_ids[] = {
+ {
+ .compatible = "fsl,imx27-iomuxc",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver_d imx_iomux_v1_driver = {
+ .name = "imx-iomuxv1",
+ .probe = imx_iomux_v1_probe,
+ .of_compatible = DRV_OF_COMPAT(imx_iomux_v1_dt_ids),
+};
+
+static int imx_iomux_v1_init(void)
+{
+ return platform_driver_register(&imx_iomux_v1_driver);
+}
+postcore_initcall(imx_iomux_v1_init);
--
1.8.5.2
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 15/22] pinctrl: Add pinctrl driver for i.MX1/21/27
2014-01-17 15:03 ` [PATCH 15/22] pinctrl: Add pinctrl driver for i.MX1/21/27 Sascha Hauer
@ 2014-01-17 15:13 ` Alexander Shiyan
2014-01-17 17:55 ` Sascha Hauer
0 siblings, 1 reply; 35+ messages in thread
From: Alexander Shiyan @ 2014-01-17 15:13 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
Пятница, 17 января 2014, 16:03 +01:00 от Sascha Hauer <s.hauer@pengutronix.de>:
> This turns the legacy iomux-v1 support into a full pinctrl
> driver.
The long-awaited changes. Unfortunately I do not use "next",
so I can check it out only when the changes go to the master
branch for i.MX27 PCM038/970.
---
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^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 15/22] pinctrl: Add pinctrl driver for i.MX1/21/27
2014-01-17 15:13 ` Alexander Shiyan
@ 2014-01-17 17:55 ` Sascha Hauer
0 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 17:55 UTC (permalink / raw)
To: Alexander Shiyan; +Cc: barebox
On Fri, Jan 17, 2014 at 07:13:42PM +0400, Alexander Shiyan wrote:
> Пятница, 17 января 2014, 16:03 +01:00 от Sascha Hauer <s.hauer@pengutronix.de>:
> > This turns the legacy iomux-v1 support into a full pinctrl
> > driver.
>
> The long-awaited changes. Unfortunately I do not use "next",
> so I can check it out only when the changes go to the master
> branch for i.MX27 PCM038/970.
These patches are based on master, so you could apply them directly
there. That's also the reason why
include/dt-bindings/interrupt-controller/irq.h is introduced again in
this series.
Sascha
--
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Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 16/22] ARM: i.MX clocksource: return successful for multiple instances
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (14 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 15/22] pinctrl: Add pinctrl driver for i.MX1/21/27 Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 15:03 ` [PATCH 17/22] ARM: phycard-i.MX27: Add NAND support to dts Sascha Hauer
` (5 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
With multiple instances we returned -EBUSY which will provoke a
log message. Return successful instead since the i.MX27 has multiple
GPTs in the devicetree.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/clocksource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c
index dc29d20..9f5ca56 100644
--- a/arch/arm/mach-imx/clocksource.c
+++ b/arch/arm/mach-imx/clocksource.c
@@ -97,7 +97,7 @@ static int imx_gpt_probe(struct device_d *dev)
/* one timer is enough */
if (timer_base)
- return -EBUSY;
+ return 0;
ret = dev_get_drvdata(dev, (unsigned long *)®s);
if (ret)
--
1.8.5.2
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^ permalink raw reply [flat|nested] 35+ messages in thread* [PATCH 17/22] ARM: phycard-i.MX27: Add NAND support to dts
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (15 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 16/22] ARM: i.MX clocksource: return successful for multiple instances Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 15:03 ` [PATCH 18/22] ARM: phycard-i.MX27: Add stdout-path property Sascha Hauer
` (4 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/imx27-phytec-phycard-s-som.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/dts/imx27-phytec-phycard-s-som.dts
index db8c095..92c7f6c 100644
--- a/arch/arm/dts/imx27-phytec-phycard-s-som.dts
+++ b/arch/arm/dts/imx27-phytec-phycard-s-som.dts
@@ -38,6 +38,10 @@
pinctrl_i2c2: i2c2grp {
fsl,pins = <MX27_I2C2_PINGRP1>;
};
+
+ pinctrl_nfc: nfcgrp {
+ fsl,pins = <MX27_NFC_PINGRP1>;
+ };
};
};
@@ -58,3 +62,12 @@
reg = <0x52>;
};
};
+
+&nfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nfc>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ status = "okay";
+};
--
1.8.5.2
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^ permalink raw reply [flat|nested] 35+ messages in thread* [PATCH 18/22] ARM: phycard-i.MX27: Add stdout-path property
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (16 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 17/22] ARM: phycard-i.MX27: Add NAND support to dts Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 15:03 ` [PATCH 19/22] ARM: dts: phycard-i.MX27: Add environment and NAND partitioning Sascha Hauer
` (3 subsequent siblings)
21 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/imx27-phytec-phycard-s-som.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/dts/imx27-phytec-phycard-s-som.dts
index 92c7f6c..c0341da 100644
--- a/arch/arm/dts/imx27-phytec-phycard-s-som.dts
+++ b/arch/arm/dts/imx27-phytec-phycard-s-som.dts
@@ -17,6 +17,10 @@
model = "Phytec pca100";
compatible = "phytec,imx27-pca100", "fsl,imx27";
+ chosen {
+ linux,stdout-path = &uart1;
+ };
+
memory {
reg = <0xa0000000 0x08000000>; /* 128MB */
};
--
1.8.5.2
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^ permalink raw reply [flat|nested] 35+ messages in thread* [PATCH 19/22] ARM: dts: phycard-i.MX27: Add environment and NAND partitioning
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (17 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 18/22] ARM: phycard-i.MX27: Add stdout-path property Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 16:20 ` Alexander Shiyan
2014-01-17 15:03 ` [PATCH 20/22] ARM: dts: phycard-i.MX27: Add sdhc2 pinctrl Sascha Hauer
` (2 subsequent siblings)
21 siblings, 1 reply; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/imx27-phytec-phycard-s-som.dts | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/dts/imx27-phytec-phycard-s-som.dts
index c0341da..eba6240 100644
--- a/arch/arm/dts/imx27-phytec-phycard-s-som.dts
+++ b/arch/arm/dts/imx27-phytec-phycard-s-som.dts
@@ -19,6 +19,11 @@
chosen {
linux,stdout-path = &uart1;
+
+ environment@0 {
+ compatible = "barebox,environment";
+ device-path = &nfc, "partname:barebox-environment";
+ };
};
memory {
@@ -74,4 +79,24 @@
nand-ecc-mode = "hw";
nand-on-flash-bbt;
status = "okay";
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0x80000>;
+ };
+
+ partition@1 {
+ label = "barebox-environment";
+ reg = <0x80000 0x80000>;
+ };
+
+ partition@2 {
+ label = "kernel";
+ reg = <0x100000 0x400000>;
+ };
+
+ partition@3 {
+ label = "root";
+ reg = <0x500000 0x7b00000>;
+ };
};
--
1.8.5.2
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 19/22] ARM: dts: phycard-i.MX27: Add environment and NAND partitioning
2014-01-17 15:03 ` [PATCH 19/22] ARM: dts: phycard-i.MX27: Add environment and NAND partitioning Sascha Hauer
@ 2014-01-17 16:20 ` Alexander Shiyan
2014-01-20 9:50 ` Sascha Hauer
0 siblings, 1 reply; 35+ messages in thread
From: Alexander Shiyan @ 2014-01-17 16:20 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
Пятница, 17 января 2014, 16:03 +01:00 от Sascha Hauer <s.hauer@pengutronix.de>:
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/dts/imx27-phytec-phycard-s-som.dts | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/dts/imx27-phytec-phycard-s-som.dts
> index c0341da..eba6240 100644
> --- a/arch/arm/dts/imx27-phytec-phycard-s-som.dts
> +++ b/arch/arm/dts/imx27-phytec-phycard-s-som.dts
> @@ -19,6 +19,11 @@
>
> chosen {
> linux,stdout-path = &uart1;
> +
> + environment@0 {
> + compatible = "barebox,environment";
> + device-path = &nfc, "partname:barebox-environment";
> + };
> };
>
> memory {
> @@ -74,4 +79,24 @@
> nand-ecc-mode = "hw";
> nand-on-flash-bbt;
> status = "okay";
> +
> + partition@0 {
> + label = "barebox";
> + reg = <0x0 0x80000>;
> + };
> +
> + partition@1 {
> + label = "barebox-environment";
> + reg = <0x80000 0x80000>;
> + };
I would suggest names "boot" and "env".
This will be transparent to other bootloaders and will
not cause criticism if the change will go into the kernel.
---
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 19/22] ARM: dts: phycard-i.MX27: Add environment and NAND partitioning
2014-01-17 16:20 ` Alexander Shiyan
@ 2014-01-20 9:50 ` Sascha Hauer
0 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-20 9:50 UTC (permalink / raw)
To: Alexander Shiyan; +Cc: barebox
On Fri, Jan 17, 2014 at 08:20:33PM +0400, Alexander Shiyan wrote:
> Пятница, 17 января 2014, 16:03 +01:00 от Sascha Hauer <s.hauer@pengutronix.de>:
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> > arch/arm/dts/imx27-phytec-phycard-s-som.dts | 25 +++++++++++++++++++++++++
> > 1 file changed, 25 insertions(+)
> >
> > diff --git a/arch/arm/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/dts/imx27-phytec-phycard-s-som.dts
> > index c0341da..eba6240 100644
> > --- a/arch/arm/dts/imx27-phytec-phycard-s-som.dts
> > +++ b/arch/arm/dts/imx27-phytec-phycard-s-som.dts
> > @@ -19,6 +19,11 @@
> >
> > chosen {
> > linux,stdout-path = &uart1;
> > +
> > + environment@0 {
> > + compatible = "barebox,environment";
> > + device-path = &nfc, "partname:barebox-environment";
> > + };
> > };
> >
> > memory {
> > @@ -74,4 +79,24 @@
> > nand-ecc-mode = "hw";
> > nand-on-flash-bbt;
> > status = "okay";
> > +
> > + partition@0 {
> > + label = "barebox";
> > + reg = <0x0 0x80000>;
> > + };
> > +
> > + partition@1 {
> > + label = "barebox-environment";
> > + reg = <0x80000 0x80000>;
> > + };
>
> I would suggest names "boot" and "env".
> This will be transparent to other bootloaders and will
> not cause criticism if the change will go into the kernel.
Ok, good idea.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 20/22] ARM: dts: phycard-i.MX27: Add sdhc2 pinctrl
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (18 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 19/22] ARM: dts: phycard-i.MX27: Add environment and NAND partitioning Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-18 18:09 ` Alexander Aring
2014-01-17 15:03 ` [PATCH 21/22] mci: imx: Add devicetree probe support Sascha Hauer
2014-01-17 15:03 ` [PATCH 22/22] ARM: phyCARD-i.MX27: Switch to " Sascha Hauer
21 siblings, 1 reply; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/imx27-phytec-phycard-s-rdk.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
index 0d65023..789ce3f 100644
--- a/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
+++ b/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
@@ -83,6 +83,10 @@
fsl,pins = <MX27_OWIRE1_PINGRP1>;
};
+ pinctrl_sdhc2: sdhc3grp {
+ fsl,pins = <MX27_SDHC2_PINGRP1>;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_UART1_PINGRP1
@@ -113,6 +117,8 @@
};
&sdhci2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhc2>;
cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
status = "okay";
};
--
1.8.5.2
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 20/22] ARM: dts: phycard-i.MX27: Add sdhc2 pinctrl
2014-01-17 15:03 ` [PATCH 20/22] ARM: dts: phycard-i.MX27: Add sdhc2 pinctrl Sascha Hauer
@ 2014-01-18 18:09 ` Alexander Aring
2014-01-20 9:52 ` Sascha Hauer
0 siblings, 1 reply; 35+ messages in thread
From: Alexander Aring @ 2014-01-18 18:09 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
Hi Sascha,
On Fri, Jan 17, 2014 at 04:03:30PM +0100, Sascha Hauer wrote:
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/dts/imx27-phytec-phycard-s-rdk.dts | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
> index 0d65023..789ce3f 100644
> --- a/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
> +++ b/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
> @@ -83,6 +83,10 @@
> fsl,pins = <MX27_OWIRE1_PINGRP1>;
> };
>
> + pinctrl_sdhc2: sdhc3grp {
don't know if this is a typo, but maybe we need a s/sdhc3grp/sdhc2grp/g
here. I think it works anyway with my knowledge about devicetrees :-)
- Alex
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 20/22] ARM: dts: phycard-i.MX27: Add sdhc2 pinctrl
2014-01-18 18:09 ` Alexander Aring
@ 2014-01-20 9:52 ` Sascha Hauer
0 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-20 9:52 UTC (permalink / raw)
To: Alexander Aring; +Cc: barebox
On Sat, Jan 18, 2014 at 07:09:34PM +0100, Alexander Aring wrote:
> Hi Sascha,
>
> On Fri, Jan 17, 2014 at 04:03:30PM +0100, Sascha Hauer wrote:
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> > arch/arm/dts/imx27-phytec-phycard-s-rdk.dts | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
> > index 0d65023..789ce3f 100644
> > --- a/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
> > +++ b/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
> > @@ -83,6 +83,10 @@
> > fsl,pins = <MX27_OWIRE1_PINGRP1>;
> > };
> >
> > + pinctrl_sdhc2: sdhc3grp {
>
> don't know if this is a typo, but maybe we need a s/sdhc3grp/sdhc2grp/g
> here. I think it works anyway with my knowledge about devicetrees :-)
Ok, fixed.
Sascha
--
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Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 21/22] mci: imx: Add devicetree probe support
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (19 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 20/22] ARM: dts: phycard-i.MX27: Add sdhc2 pinctrl Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
2014-01-17 15:03 ` [PATCH 22/22] ARM: phyCARD-i.MX27: Switch to " Sascha Hauer
21 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
Only simple probing, no properties supported yet.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/mci/imx.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/mci/imx.c b/drivers/mci/imx.c
index aea78c7..6992177 100644
--- a/drivers/mci/imx.c
+++ b/drivers/mci/imx.c
@@ -520,8 +520,17 @@ static int mxcmci_probe(struct device_d *dev)
return 0;
}
+static __maybe_unused struct of_device_id mxcmci_compatible[] = {
+ {
+ .compatible = "fsl,imx27-mmc",
+ }, {
+ /* sentinel */
+ }
+};
+
static struct driver_d mxcmci_driver = {
.name = DRIVER_NAME,
.probe = mxcmci_probe,
+ .of_compatible = DRV_OF_COMPAT(mxcmci_compatible),
};
device_platform_driver(mxcmci_driver);
--
1.8.5.2
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^ permalink raw reply [flat|nested] 35+ messages in thread* [PATCH 22/22] ARM: phyCARD-i.MX27: Switch to devicetree probe support
2014-01-17 15:03 phyCARD-i.MX27 patches Sascha Hauer
` (20 preceding siblings ...)
2014-01-17 15:03 ` [PATCH 21/22] mci: imx: Add devicetree probe support Sascha Hauer
@ 2014-01-17 15:03 ` Sascha Hauer
21 siblings, 0 replies; 35+ messages in thread
From: Sascha Hauer @ 2014-01-17 15:03 UTC (permalink / raw)
To: barebox
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
.../boards/phycard-i.MX27/env/init/mtdparts-nand | 11 --
arch/arm/boards/phycard-i.MX27/pca100.c | 172 +--------------------
arch/arm/configs/pca100_defconfig | 6 +
3 files changed, 8 insertions(+), 181 deletions(-)
delete mode 100644 arch/arm/boards/phycard-i.MX27/env/init/mtdparts-nand
diff --git a/arch/arm/boards/phycard-i.MX27/env/init/mtdparts-nand b/arch/arm/boards/phycard-i.MX27/env/init/mtdparts-nand
deleted file mode 100644
index e2dcfab..0000000
--- a/arch/arm/boards/phycard-i.MX27/env/init/mtdparts-nand
+++ /dev/null
@@ -1,11 +0,0 @@
-#!/bin/sh
-
-if [ "$1" = menu ]; then
- init-menu-add-entry "$0" "NAND partitions"
- exit
-fi
-
-mtdparts="512k(nand0.barebox),512k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)"
-kernelname="mxc_nand"
-
-mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts}
diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c
index 69f9a3d..be3a840 100644
--- a/arch/arm/boards/phycard-i.MX27/pca100.c
+++ b/arch/arm/boards/phycard-i.MX27/pca100.c
@@ -41,94 +41,6 @@
#include <mach/iomux-mx27.h>
#include <mach/devices-imx27.h>
-static struct fec_platform_data fec_info = {
- .xcv_type = PHY_INTERFACE_MODE_MII,
- .phy_addr = 1,
-};
-
-struct imx_nand_platform_data nand_info = {
- .width = 1,
- .hw_ecc = 1,
- .flash_bbt = 1,
-};
-
-static struct imx_fb_videomode imxfb_mode[] = {
- {
- .mode = {
- .name = "Primeview-PD050VL1",
- .refresh = 60,
- .xres = 640,
- .yres = 480,
- .pixclock = 40000, /* in ps (25MHz) */
- .hsync_len = 32,
- .left_margin = 112,
- .right_margin = 36,
- .vsync_len = 2,
- .upper_margin = 33,
- .lower_margin = 33,
- },
- .pcr = 0xF0C88080,
- .bpp = 16,
- }, {
- .mode = {
- .name = "Primeview-PD035VL1",
- .refresh = 60,
- .xres = 640,
- .yres = 480,
- .pixclock = 40000, /* in ps (25 MHz) */
- .hsync_len = 30,
- .left_margin = 98,
- .right_margin = 36,
- .vsync_len = 2,
- .upper_margin = 15,
- .lower_margin = 33,
- },
- .pcr = 0xF0C88080,
- .bpp = 16,
- }, {
- .mode = {
- .name = "Primeview-PD104SLF",
- .refresh = 60,
- .xres = 800,
- .yres = 600,
- .pixclock = 25000, /* in ps (40,0 MHz) */
- .hsync_len = 40,
- .left_margin = 174,
- .right_margin = 174,
- .vsync_len = 4,
- .upper_margin = 24,
- .lower_margin = 23,
- },
- .pcr = 0xF0C88080,
- .bpp = 16,
- }, {
- .mode = {
- .name = "Primeview-PM070WL4",
- .refresh = 60,
- .xres = 800,
- .yres = 480,
- .pixclock = 31250, /* in ps (32 MHz) */
- .hsync_len = 40,
- .left_margin = 174,
- .right_margin = 174,
- .vsync_len = 2,
- .upper_margin = 33,
- .lower_margin = 23,
- },
- .pcr = 0xF0C88080,
- .bpp = 16,
- },
-};
-
-static struct imx_fb_platform_data pca100_fb_data = {
- .mode = imxfb_mode,
- .num_modes = ARRAY_SIZE(imxfb_mode),
- .pwmr = 0x00A903FF,
- .lscr1 = 0x00120300,
- .dmacr = 0x00040060,
-};
-
-#ifdef CONFIG_USB
static void pca100_usb_register(void)
{
mdelay(10);
@@ -143,7 +55,6 @@ static void pca100_usb_register(void)
ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1);
add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL);
}
-#endif
static void pca100_usb_init(void)
{
@@ -180,38 +91,7 @@ static void pca100_usb_init(void)
static int pca100_devices_init(void)
{
int i;
- struct device_d *nand;
-
unsigned int mode[] = {
- PD0_AIN_FEC_TXD0,
- PD1_AIN_FEC_TXD1,
- PD2_AIN_FEC_TXD2,
- PD3_AIN_FEC_TXD3,
- PD4_AOUT_FEC_RX_ER,
- PD5_AOUT_FEC_RXD1,
- PD6_AOUT_FEC_RXD2,
- PD7_AOUT_FEC_RXD3,
- PD8_AF_FEC_MDIO,
- PD9_AIN_FEC_MDC | GPIO_PUEN,
- PD10_AOUT_FEC_CRS,
- PD11_AOUT_FEC_TX_CLK,
- PD12_AOUT_FEC_RXD0,
- PD13_AOUT_FEC_RX_DV,
- PD14_AOUT_FEC_RX_CLK,
- PD15_AOUT_FEC_COL,
- PD16_AIN_FEC_TX_ER,
- PF23_AIN_FEC_TX_EN,
- PE12_PF_UART1_TXD,
- PE13_PF_UART1_RXD,
- PE14_PF_UART1_CTS,
- PE15_PF_UART1_RTS,
- PD25_PF_CSPI1_RDY,
- PD26_PF_CSPI1_SS2,
- PD27_PF_CSPI1_SS1,
- PD28_PF_CSPI1_SS0,
- PD29_PF_CSPI1_SCLK,
- PD30_PF_CSPI1_MISO,
- PD31_PF_CSPI1_MOSI,
/* USB host 2 */
PA0_PF_USBH2_CLK,
PA1_PF_USBH2_DIR,
@@ -225,13 +105,6 @@ static int pca100_devices_init(void)
PD23_AF_USBH2_DATA2,
PD24_AF_USBH2_DATA1,
PD26_AF_USBH2_DATA5,
- /* SDHC */
- PB4_PF_SD2_D0,
- PB5_PF_SD2_D1,
- PB6_PF_SD2_D2,
- PB7_PF_SD2_D3,
- PB8_PF_SD2_CMD,
- PB9_PF_SD2_CLK,
PC7_PF_USBOTG_DATA5,
PC8_PF_USBOTG_DATA6,
PC9_PF_USBOTG_DATA0,
@@ -244,33 +117,6 @@ static int pca100_devices_init(void)
PE2_PF_USBOTG_DIR,
PE24_PF_USBOTG_CLK,
PE25_PF_USBOTG_DATA7,
- /* display */
- PA5_PF_LSCLK,
- PA6_PF_LD0,
- PA7_PF_LD1,
- PA8_PF_LD2,
- PA9_PF_LD3,
- PA10_PF_LD4,
- PA11_PF_LD5,
- PA12_PF_LD6,
- PA13_PF_LD7,
- PA14_PF_LD8,
- PA15_PF_LD9,
- PA16_PF_LD10,
- PA17_PF_LD11,
- PA18_PF_LD12,
- PA19_PF_LD13,
- PA20_PF_LD14,
- PA21_PF_LD15,
- PA22_PF_LD16,
- PA23_PF_LD17,
- PA26_PF_PS,
- PA28_PF_HSYNC,
- PA29_PF_VSYNC,
- PA31_PF_OE_ACD,
- /* external I2C */
- PD17_PF_I2C_DATA,
- PD18_PF_I2C_CLK,
};
pca100_usb_init();
@@ -279,21 +125,8 @@ static int pca100_devices_init(void)
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
- imx27_add_nand(&nand_info);
- imx27_add_fec(&fec_info);
- imx27_add_mmc1(NULL);
- imx27_add_fb(&pca100_fb_data);
-
-#ifdef CONFIG_USB
- pca100_usb_register();
-#endif
-
- nand = get_device_by_name("nand0");
- devfs_add_partition("nand0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw");
- dev_add_bb_dev("self_raw", "self0");
-
- devfs_add_partition("nand0", SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, "env_raw");
- dev_add_bb_dev("env_raw", "env0");
+ if (IS_ENABLED(CONFIG_USB))
+ pca100_usb_register();
imx_bbu_external_nand_register_handler("nand", "/dev/nand0.barebox",
BBU_HANDLER_FLAG_DEFAULT);
@@ -310,7 +143,6 @@ static int pca100_console_init(void)
barebox_set_model("Phytec phyCARD-i.MX27");
barebox_set_hostname("phycard-imx27");
- imx27_add_uart0();
return 0;
}
diff --git a/arch/arm/configs/pca100_defconfig b/arch/arm/configs/pca100_defconfig
index 12753cf..b6fefbf 100644
--- a/arch/arm/configs/pca100_defconfig
+++ b/arch/arm/configs/pca100_defconfig
@@ -1,3 +1,5 @@
+CONFIG_BUILTIN_DTB=y
+CONFIG_BUILTIN_DTB_NAME="imx27-phytec-phycard-s-rdk"
CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y
CONFIG_MACH_PCA100=y
@@ -15,6 +17,7 @@ CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_MENU=y
CONFIG_BLSPEC=y
+CONFIG_CONSOLE_ACTIVATE_NONE=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phycard-i.MX27/env"
CONFIG_RESET_SOURCE=y
@@ -60,6 +63,8 @@ CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_PING=y
CONFIG_NET_NETCONSOLE=y
+CONFIG_OFDEVICE=y
+CONFIG_OF_BAREBOX_DRIVERS=y
CONFIG_DRIVER_NET_FEC_IMX=y
CONFIG_NET_USB=y
CONFIG_NET_USB_ASIX=y
@@ -76,6 +81,7 @@ CONFIG_USB_EHCI=y
CONFIG_USB_ULPI=y
CONFIG_MCI=y
CONFIG_MCI_IMX=y
+CONFIG_IMX_WEIM=y
CONFIG_FS_EXT4=y
CONFIG_FS_TFTP=y
CONFIG_FS_FAT=y
--
1.8.5.2
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^ permalink raw reply [flat|nested] 35+ messages in thread