* bug in arm_cpu_lowlevel_init ??
@ 2014-02-27 6:15 zzs
2014-02-27 6:53 ` Alexander Shiyan
2014-02-27 7:27 ` Sascha Hauer
0 siblings, 2 replies; 6+ messages in thread
From: zzs @ 2014-02-27 6:15 UTC (permalink / raw)
To: barebox
My cpu is at91rm9200
When start barebox at reset time by burn it in Nor flash, all things Ok.
But when start it by my first stage boot program, It's crash. And
Execption process code which install by my boot program, report Undef
instruction detected.
The only diff is my boot program change the cpu to svc mode already.
I try the flowwing patch:
------------------------------------------------
--- a/arch/arm/cpu/lowlevel.S
+++ b/arch/arm/cpu/lowlevel.S
@@ -4,6 +4,7 @@
.section ".text_bare_init_","ax"
ENTRY(arm_cpu_lowlevel_init)
+ mov r2, lr
/* set the cpu to SVC32 mode */
mrs r12, cpsr
bic r12, r12, #0x1f
@@ -35,5 +36,5 @@ ENTRY(arm_cpu_lowlevel_init)
mcr p15, 0, r12, c1, c0, 0
- mov pc, lr
+ mov pc, r2
ENDPROC(arm_cpu_lowlevel_init)
------------------------------------------------
The problem dispeared, All things worked!!
I'm not very familiar with asm code,
Anybody tell me is this a bug, Or my boot program has strange behavior?
Thanks!!
--
Best Regards,
zzs
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: bug in arm_cpu_lowlevel_init ??
2014-02-27 6:15 bug in arm_cpu_lowlevel_init ?? zzs
@ 2014-02-27 6:53 ` Alexander Shiyan
2014-02-27 7:53 ` zzs
2014-02-27 7:27 ` Sascha Hauer
1 sibling, 1 reply; 6+ messages in thread
From: Alexander Shiyan @ 2014-02-27 6:53 UTC (permalink / raw)
To: zzs; +Cc: barebox
Четверг, 27 февраля 2014, 14:15 +08:00 от zzs <zzs213@126.com>:
> My cpu is at91rm9200
>
> When start barebox at reset time by burn it in Nor flash, all things Ok.
>
> But when start it by my first stage boot program, It's crash. And
> Execption process code which install by my boot program, report Undef
> instruction detected.
>
> The only diff is my boot program change the cpu to svc mode already.
>
> I try the flowwing patch:
>
> ------------------------------------------------
> --- a/arch/arm/cpu/lowlevel.S
> +++ b/arch/arm/cpu/lowlevel.S
> @@ -4,6 +4,7 @@
>
> .section ".text_bare_init_","ax"
> ENTRY(arm_cpu_lowlevel_init)
> + mov r2, lr
> /* set the cpu to SVC32 mode */
> mrs r12, cpsr
> bic r12, r12, #0x1f
> @@ -35,5 +36,5 @@ ENTRY(arm_cpu_lowlevel_init)
>
> mcr p15, 0, r12, c1, c0, 0
>
> - mov pc, lr
> + mov pc, r2
> ENDPROC(arm_cpu_lowlevel_init)
> ------------------------------------------------
>
> The problem dispeared, All things worked!!
>
> I'm not very familiar with asm code,
>
> Anybody tell me is this a bug, Or my boot program has strange behavior?
I can not say anything about this issue,
but maybe something will help article below:
http://www.heyrick.co.uk/armwiki/The_Status_register
---
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: bug in arm_cpu_lowlevel_init ??
2014-02-27 6:15 bug in arm_cpu_lowlevel_init ?? zzs
2014-02-27 6:53 ` Alexander Shiyan
@ 2014-02-27 7:27 ` Sascha Hauer
2014-02-27 7:51 ` zzs
1 sibling, 1 reply; 6+ messages in thread
From: Sascha Hauer @ 2014-02-27 7:27 UTC (permalink / raw)
To: barebox
Hi,
On Thu, Feb 27, 2014 at 02:15:44PM +0800, zzs wrote:
> My cpu is at91rm9200
>
> When start barebox at reset time by burn it in Nor flash, all things Ok.
>
> But when start it by my first stage boot program, It's crash. And
> Execption process code which install by my boot program, report Undef
> instruction detected.
>
> The only diff is my boot program change the cpu to svc mode already.
>
> I try the flowwing patch:
>
> ------------------------------------------------
> --- a/arch/arm/cpu/lowlevel.S
> +++ b/arch/arm/cpu/lowlevel.S
> @@ -4,6 +4,7 @@
>
> .section ".text_bare_init_","ax"
> ENTRY(arm_cpu_lowlevel_init)
> + mov r2, lr
> /* set the cpu to SVC32 mode */
> mrs r12, cpsr
> bic r12, r12, #0x1f
> @@ -35,5 +36,5 @@ ENTRY(arm_cpu_lowlevel_init)
>
> mcr p15, 0, r12, c1, c0, 0
>
> - mov pc, lr
> + mov pc, r2
> ENDPROC(arm_cpu_lowlevel_init)
The lr (r14) register has different instances, one for each mode. It
could be that once we switch to a different mode in arm_cpu_lowlevel_init
we see another instance of r14. So to me the patch looks correct, we
shouldn't rely on lr as return address but rather use another register
for storing the address.
The above only happens though when the CPU is not in SVC32 mode already.
What first stage loader are you using? Could you analyze in which mode
the CPU is when the loader jumps to barebox?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: bug in arm_cpu_lowlevel_init ??
2014-02-27 7:27 ` Sascha Hauer
@ 2014-02-27 7:51 ` zzs
2014-02-27 8:01 ` Sascha Hauer
0 siblings, 1 reply; 6+ messages in thread
From: zzs @ 2014-02-27 7:51 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
>
> The lr (r14) register has different instances, one for each mode. It
> could be that once we switch to a different mode in arm_cpu_lowlevel_init
> we see another instance of r14. So to me the patch looks correct, we
> shouldn't rely on lr as return address but rather use another register
> for storing the address.
> The above only happens though when the CPU is not in SVC32 mode already.
> What first stage loader are you using? Could you analyze in which mode
> the CPU is when the loader jumps to barebox?
>
The first stage loader was written by myself longlong ago. So forgot the
details. I just look the code closer, Found the flowwing line just
before jumps to barebox.
asm ("msr CPSR_c, %0" : :"i"(ARM_MODE_SYS|I_BIT|F_BIT));
So it seems the cpu is in system mode when run barebox.
Your explanation is right.
--
Best Regards,
zzs
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: bug in arm_cpu_lowlevel_init ??
2014-02-27 7:51 ` zzs
@ 2014-02-27 8:01 ` Sascha Hauer
0 siblings, 0 replies; 6+ messages in thread
From: Sascha Hauer @ 2014-02-27 8:01 UTC (permalink / raw)
To: barebox
On Thu, Feb 27, 2014 at 03:51:26PM +0800, zzs wrote:
> >
> > The lr (r14) register has different instances, one for each mode. It
> > could be that once we switch to a different mode in arm_cpu_lowlevel_init
> > we see another instance of r14. So to me the patch looks correct, we
> > shouldn't rely on lr as return address but rather use another register
> > for storing the address.
> > The above only happens though when the CPU is not in SVC32 mode already.
> > What first stage loader are you using? Could you analyze in which mode
> > the CPU is when the loader jumps to barebox?
> >
> The first stage loader was written by myself longlong ago. So forgot the
> details. I just look the code closer, Found the flowwing line just
> before jumps to barebox.
>
> asm ("msr CPSR_c, %0" : :"i"(ARM_MODE_SYS|I_BIT|F_BIT));
>
> So it seems the cpu is in system mode when run barebox.
> Your explanation is right.
Ok, so arm_cpu_lowlevel_init currently only works if the CPU is in SVC32
mode already. Could you send a formal patch with the change you made
with a Signed-off-by line? Then I'll include it in barebox.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
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^ permalink raw reply [flat|nested] 6+ messages in thread
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2014-02-27 6:15 bug in arm_cpu_lowlevel_init ?? zzs
2014-02-27 6:53 ` Alexander Shiyan
2014-02-27 7:53 ` zzs
2014-02-27 7:27 ` Sascha Hauer
2014-02-27 7:51 ` zzs
2014-02-27 8:01 ` Sascha Hauer
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