Re: [PATCH 6/6] ARM: pfla02: Set new ethernet phy tx timings

[Alexander Aring <alex.aring@gmail.com>]

On Fri, Mar 14, 2014 at 02:30:20PM +0100, Sascha Hauer wrote:
> From: Christian Hemp <c.hemp@phytec.de>
> 
> TX_CLK line is approx. 54mm longer than other TX lines which adds
> a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we have to add
> a delay of 0.64ns. We choose 0.78 to have a little gap. This can be done by
> setting GTX pad skew value to 11100
>  => Set register 2.8 (RGMII Clock Pad Skew) to 0x038F.
> 
> Signed-off-by: Christian Hemp <c.hemp@phytec.de>
> ---
>  arch/arm/boards/phytec-phyflex-imx6/board.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm/boards/phytec-phyflex-imx6/board.c b/arch/arm/boards/phytec-phyflex-imx6/board.c
> index f510407..3db88da 100644
> --- a/arch/arm/boards/phytec-phyflex-imx6/board.c
> +++ b/arch/arm/boards/phytec-phyflex-imx6/board.c
> @@ -21,6 +21,9 @@
>  #include <gpio.h>
>  #include <init.h>
>  #include <of.h>
> +#include <fec.h>
> +
> +#include <linux/micrel_phy.h>
>  
>  #include <mach/imx6.h>
>  
> @@ -36,6 +39,21 @@ static int eth_phy_reset(void)
>  	return 0;
>  }
>  
> +static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
> +{
> +	phy_write(dev, 0x0d, device);
> +	phy_write(dev, 0x0e, reg);
> +	phy_write(dev, 0x0d, (1 << 14) | device);
> +	phy_write(dev, 0x0e, val);
> +}
> +
> +static int ksz9031rn_phy_fixup(struct phy_device *dev)
> +{
> +	mmd_write_reg(dev, 2, 8, 0x039F);
> +
commit msg says 0x038F and here is 0x039F. Which one is correct now?

- Alex

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