From: Sascha Hauer <s.hauer@pengutronix.de>
To: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH] ARM: remove unused code from __v7_mmu_cache_flush_invalidate
Date: Wed, 21 Jan 2015 14:56:45 +0100 [thread overview]
Message-ID: <20150121135645.GH12209@pengutronix.de> (raw)
In-Reply-To: <1421814254-13282-1-git-send-email-yamada.m@jp.panasonic.com>
On Wed, Jan 21, 2015 at 01:24:14PM +0900, Masahiro Yamada wrote:
> This code is unnecessary (wrong) for the following reasons.
>
> [1] As ARM ARM clearly says, the entire Level 1 cache maintenance
> operations are not supported for ARMv7, i.e. the bit19-16 of
> the ID_MMFR1 is always 0b0000. The code always jumps to the
> "hierarchical" label.
The offending code is from the kernel from arch/arm/boot/compressed/head.S
The test for ID_MMFR1 nearly unchanged since:
commit 7d09e85448dfa78e3e58186c934449aaf6d49b50
Author: Catalin Marinas <catalin.marinas@arm.com>
Date: Fri Jun 1 17:14:53 2007 +0100
That of course doesn't make it more correct. Maybe we should send the
same patch to the kernel and let Catalin explain why this code is
necessary (or why not)
>
> [2] The value of "r0" is supposed to determine which cache operation
> should be done, invalidate or clean+invalidate. The line
> "mcr p15, 0, r12, c7, c14, 0" tries to clean+invalidate
> regardless of the value of "r0", this is weird.
> Anyway, as mentioned above, this line cannot be reached.
This is since
commit 465950ee64f6fbeb0daf138c2d43ad71be159375
Author: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Date: Tue May 14 15:14:56 2013 +0200
ARM v7: added v7_mmu_cache_invalidate()
Appearantly Enrico only handled the hierarchical case.
Sascha
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next prev parent reply other threads:[~2015-01-21 13:57 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-21 4:24 Masahiro Yamada
2015-01-21 13:56 ` Sascha Hauer [this message]
2015-01-21 16:46 ` Masahiro YAMADA
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