Re: [PATCH 00/24] Phasing out direct usage of asm/mmu.h on ARM

[Sascha Hauer <s.hauer@pengutronix.de>]

On Sun, Mar 01, 2015 at 02:16:58PM +0100, Lucas Stach wrote:
> This series introduces to Barebox the streaming DMA ops and implements
> them for the ARM architecture. This will make it a lot easier to
> get common cache maintenance operations for all architectures and in
> turn allows for wider reuse of driver across architectures.
> 
> I've tested this on a Tegra124 which is known to fall over in all sorts
> of funny ways if cache maintenance is broken. No odd behavior spotted.
> 
> The series is bisect-clean and I've compile tested it on some defconfigs,
> but please go wild and TEST. I'll take any complaints.
> 
> Changes since RFT:
> - rebased to current master
> - now compile tested on all ARM defconfigs
> - fixed a few compile errors by reordering stuff in patches
> - A few more words in commit logs

As discussed with Lucas personally:

The series breaks MIPS and NIOS2 support.

On ARM we assume that the address returned from dma_alloc_coherent
can be used as physical DMA address. This is not true on MIPS and NIOS2.
On MIPS and NIOS2 dma_alloc_coherent also returns the DMA address which
differs from the virtual address. This means most users of DMA memory
are broken on MIPS and NIOS2, only the drivers which use the MIPS/NIOS2
variant of dma_alloc_coherent work on these architectures.

The outcome is that we'll implement dma_alloc_coherent() for all
architectures which also returns the physical address:

void *dma_alloc_coherent(size_t len, dma_addr_t *handle);

For all the users which do not handle converting the virtual address
into a DMA address properly we'll add a

#define DMA_ADDRESS_BROKEN	NULL

define which can be passed as the handle pointer. This will allow us to
identify broken users easily and to fix them one by one.

Sascha



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