From: Sascha Hauer <s.hauer@pengutronix.de>
To: "Michael D. Burkey" <mdburkey@gmail.com>
Cc: barebox@lists.infradead.org
Subject: Re: Early access I2C and/or clock for iMX6?
Date: Tue, 21 Jun 2016 08:32:05 +0200 [thread overview]
Message-ID: <20160621063205.GW9677@pengutronix.de> (raw)
In-Reply-To: <CAO6XYUs7ytpWZyTnp04Fo-Ee_D2PYAJ36fg_tC8M20KHLc59TA@mail.gmail.com>
On Mon, Jun 20, 2016 at 03:34:06PM -0400, Michael D. Burkey wrote:
> In a quest to support the new Variscite SOM's EEPROM based DDR
> configuration, I am continuing to try to get all the pieces together.
>
> Now that I have the SOM actually booting from IRAM, I am actually
> trying to get the "real" DDR configuration values out of the EEPROM on
> the SOM.
>
> Which brings me to the next hurdle -- getting early I2C access up and running.
>
> Thanks to some pointers from Sascha, I have been working with the
> fsl_i2c.c code that had already been used for this task on the mpc85xx
> PPC platform, and while the I2C controller is essentially the same,
> the clock tree setup, etc. for the iMX6 is quite different.
The fsl_i2c.c driver as currently in arch/ppc/ needs the input clock
frequency and some timer for a timeout loop. The timeout could be
dropped from the loop which is ok for a early bringup driver. For the
input clock frequency you can pass in the reset default value,
statically compiled into the binary; no need to calculate it during
runtime. I still think fsl_i2c.c is the way to go, but you could also
you whatever else "early" variant of the driver, I wouldn't start from a
driver implementing the Linux I2C API though.
Sascha
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next prev parent reply other threads:[~2016-06-21 6:32 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-20 19:34 Michael D. Burkey
2016-06-21 6:32 ` Sascha Hauer [this message]
2016-06-20 21:02 Michael D. Burkey
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