[PATCH 1/2] i.MX: Introduce imx6_cpu_revision()

* [PATCH 1/2] i.MX: Introduce imx6_cpu_revision()
@ 2016-09-29 22:21 Andrey Smirnov
  2016-09-29 22:21 ` [PATCH 2/2] i.MX: Register imx6_fixup_cpus() for MX6Q+ as well Andrey Smirnov
  2016-10-04  6:10 ` [PATCH 1/2] i.MX: Introduce imx6_cpu_revision() Sascha Hauer
  0 siblings, 2 replies; 3+ messages in thread
From: Andrey Smirnov @ 2016-09-29 22:21 UTC (permalink / raw)
  To: barebox; +Cc: Andrey Smirnov

Factor out CPU revision identification code from imx6_init() into a
standalone inline function (similar to imx6_cpu_type()), so that it
would be possible to use that functionality in PBL code.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---

Sascha:

I have an almost ready to send, board support patch that uses this in
PBL. Unfortunately at the last minute a regression in functionality
was discovered in that code, so I can't post it until that is
resolved, meanwhile I am hoping I can get this code in while I am
debugging.

Let me know if you'd rathe I send everything together.

 arch/arm/mach-imx/imx6.c              | 38 +----------------------------------
 arch/arm/mach-imx/include/mach/imx6.h | 36 +++++++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+), 37 deletions(-)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index ba8fb89..101a2f6 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -25,8 +25,6 @@
 #include <asm/mmu.h>
 #include <asm/cache-l2x0.h>
 
-#define SI_REV 0x260
-
 void imx6_init_lowlevel(void)
 {
 	void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
@@ -115,47 +113,13 @@ void imx6_init_lowlevel(void)
 int imx6_init(void)
 {
 	const char *cputypestr;
-	u32 rev;
 	u32 mx6_silicon_revision;
 
 	imx6_init_lowlevel();
 
 	imx6_boot_save_loc((void *)MX6_SRC_BASE_ADDR);
 
-	rev = readl(MX6_ANATOP_BASE_ADDR + SI_REV);
-
-	switch (rev & 0xfff) {
-	case 0x00:
-		mx6_silicon_revision = IMX_CHIP_REV_1_0;
-		break;
-
-	case 0x01:
-		mx6_silicon_revision = IMX_CHIP_REV_1_1;
-		break;
-
-	case 0x02:
-		mx6_silicon_revision = IMX_CHIP_REV_1_2;
-		break;
-
-	case 0x03:
-		mx6_silicon_revision = IMX_CHIP_REV_1_3;
-		break;
-
-	case 0x04:
-		mx6_silicon_revision = IMX_CHIP_REV_1_4;
-		break;
-
-	case 0x05:
-		mx6_silicon_revision = IMX_CHIP_REV_1_5;
-		break;
-
-	case 0x100:
-		mx6_silicon_revision = IMX_CHIP_REV_2_0;
-		break;
-
-	default:
-		mx6_silicon_revision = IMX_CHIP_REV_UNKNOWN;
-	}
+	mx6_silicon_revision = imx6_cpu_revision();
 
 	switch (imx6_cpu_type()) {
 	case IMX6_CPUTYPE_IMX6Q:
diff --git a/arch/arm/mach-imx/include/mach/imx6.h b/arch/arm/mach-imx/include/mach/imx6.h
index e8ffa47..fb5eaf1 100644
--- a/arch/arm/mach-imx/include/mach/imx6.h
+++ b/arch/arm/mach-imx/include/mach/imx6.h
@@ -4,6 +4,7 @@
 #include <io.h>
 #include <mach/generic.h>
 #include <mach/imx6-regs.h>
+#include <mach/revision.h>
 
 void imx6_init_lowlevel(void);
 
@@ -48,6 +49,41 @@ static inline int imx6_cpu_type(void)
 	return __imx6_cpu_type();
 }
 
+static inline int __imx6_cpu_revision(void)
+{
+
+	uint32_t rev;
+
+	rev = readl(MX6_ANATOP_BASE_ADDR + IMX6_ANATOP_SI_REV);
+
+	switch (rev & 0xfff) {
+	case 0x00:
+		return IMX_CHIP_REV_1_0;
+	case 0x01:
+		return IMX_CHIP_REV_1_1;
+	case 0x02:
+		return IMX_CHIP_REV_1_2;
+	case 0x03:
+		return IMX_CHIP_REV_1_3;
+	case 0x04:
+		return IMX_CHIP_REV_1_4;
+	case 0x05:
+		return IMX_CHIP_REV_1_5;
+	case 0x100:
+		return IMX_CHIP_REV_2_0;
+	}
+
+	return IMX_CHIP_REV_UNKNOWN;
+}
+
+static inline int imx6_cpu_revision(void)
+{
+	if (!cpu_is_mx6())
+		return 0;
+
+	return __imx6_cpu_revision();
+}
+
 #define DEFINE_MX6_CPU_TYPE(str, type)					\
 	static inline int cpu_mx6_is_##str(void)			\
 	{								\
-- 
2.5.5


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