* [PATCH 1/4] net/designware: Consecutive writes to the same register to be avoided
2016-11-07 18:16 [PATCH 0/4] net/designware: A few patches from U-Boot Ian Abbott
@ 2016-11-07 18:16 ` Ian Abbott
2016-11-07 18:16 ` [PATCH 2/4] net/designware: Do not select MIIPORT for RGMII interface Ian Abbott
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Ian Abbott @ 2016-11-07 18:16 UTC (permalink / raw)
To: barebox; +Cc: Ian Abbott
There are a few registers where consecutive writes to the same location
should be avoided or have a delay.
According to Synopsys, here is a list of the registers and bit(s) where
consecutive writes should be avoided or a delay is required:
DMA Registers:
Register 0 Bit 7
Register 6 All bits except for 24, 16-13, 2-1.
GMAC Registers:
Registers 0-3 All bits
Registers 6-7 All bits
Register 10 All bits
Register 11 All bits except for 5-6.
Registers 16-47 All bits
Register 48 All bits except for 18-16, 14.
Register 448 Bit 4.
Register 459 Bits 0-3.
[Original U-Boot patch by Dinh Nguyen <dinguyen@altera.com>]
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/net/designware.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 1d662a7..21fb44e 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -248,8 +248,8 @@ static int dwc_ether_init(struct eth_device *dev)
dev->set_ethaddr(dev, priv->macaddr);
writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode);
- writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode);
- writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode);
+ writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD |
+ TXSECONDFRAME, &dma_p->opmode);
writel(FRAMEBURSTENABLE | DISABLERXOWN, &mac_p->conf);
return 0;
}
--
2.10.1
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* [PATCH 2/4] net/designware: Do not select MIIPORT for RGMII interface
2016-11-07 18:16 [PATCH 0/4] net/designware: A few patches from U-Boot Ian Abbott
2016-11-07 18:16 ` [PATCH 1/4] net/designware: Consecutive writes to the same register to be avoided Ian Abbott
@ 2016-11-07 18:16 ` Ian Abbott
2016-11-07 18:16 ` [PATCH 3/4] net: designware: Respect "bus mode" register contents on SW reset Ian Abbott
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Ian Abbott @ 2016-11-07 18:16 UTC (permalink / raw)
To: barebox; +Cc: Ian Abbott
Do not select MIIPORT for RGMII interface
[Original U-Boot patch by Vipin Kumar <vipin.kumar@st.com>]
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/net/designware.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 21fb44e..85e4c58 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -129,7 +129,9 @@ static int mac_reset(struct eth_device *dev)
u64 start;
writel(DMAMAC_SRST, &dma_p->busmode);
- writel(MII_PORTSELECT, &mac_p->conf);
+
+ if (priv->interface != PHY_INTERFACE_MODE_RGMII)
+ writel(MII_PORTSELECT, &mac_p->conf);
start = get_time_ns();
while (readl(&dma_p->busmode) & DMAMAC_SRST) {
--
2.10.1
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* [PATCH 3/4] net: designware: Respect "bus mode" register contents on SW reset
2016-11-07 18:16 [PATCH 0/4] net/designware: A few patches from U-Boot Ian Abbott
2016-11-07 18:16 ` [PATCH 1/4] net/designware: Consecutive writes to the same register to be avoided Ian Abbott
2016-11-07 18:16 ` [PATCH 2/4] net/designware: Do not select MIIPORT for RGMII interface Ian Abbott
@ 2016-11-07 18:16 ` Ian Abbott
2016-11-07 18:16 ` [PATCH 4/4] net/designware: add explicit reset of {tx|rx}_currdescnum Ian Abbott
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Ian Abbott @ 2016-11-07 18:16 UTC (permalink / raw)
To: barebox; +Cc: Ian Abbott
"bus mode" register contains lots of fields and some of them don't
expect to be written with 0 (zero). So since we're only interested in
resetting MAC (which is done with setting the least significant bit of
this register with "0") I believe it's better to modify only 1 bit of
the register.
[Original U-Boot patch by Alexey Brodkin <abrodkin@synopsys.com>]
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/net/designware.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 85e4c58..6702d4c 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -128,7 +128,7 @@ static int mac_reset(struct eth_device *dev)
struct eth_dma_regs *dma_p = priv->dma_regs_p;
u64 start;
- writel(DMAMAC_SRST, &dma_p->busmode);
+ writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
if (priv->interface != PHY_INTERFACE_MODE_RGMII)
writel(MII_PORTSELECT, &mac_p->conf);
--
2.10.1
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* [PATCH 4/4] net/designware: add explicit reset of {tx|rx}_currdescnum
2016-11-07 18:16 [PATCH 0/4] net/designware: A few patches from U-Boot Ian Abbott
` (2 preceding siblings ...)
2016-11-07 18:16 ` [PATCH 3/4] net: designware: Respect "bus mode" register contents on SW reset Ian Abbott
@ 2016-11-07 18:16 ` Ian Abbott
2016-11-10 8:49 ` [PATCH 0/4] net/designware: A few patches from U-Boot Sascha Hauer
2016-11-10 14:04 ` Sascha Hauer
5 siblings, 0 replies; 8+ messages in thread
From: Ian Abbott @ 2016-11-07 18:16 UTC (permalink / raw)
To: barebox; +Cc: Ian Abbott
Driver "init" function might be called multiple times.
On every "init" Tx/Rx buffer descriptors are initialized: "descs_init"
-> "{tx|rx}_descs_init".
In its turn those init functions set MAC's "{tx|rx}desclistaddr" to
point on the first buffer descriptor in the list.
So CPU to start operation from the first buffer descriptor as well after
every "init" we have to reset "{tx|rx}_currdescnum".
[Original U-Boot patch by Alexey Brodkin <abrodkin@synopsys.com>]
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/net/designware.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 6702d4c..bd20a87 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -176,6 +176,7 @@ static void tx_descs_init(struct eth_device *dev)
desc_p->dmamac_next = &desc_table_p[0];
writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
+ priv->tx_currdescnum = 0;
}
static void rx_descs_init(struct eth_device *dev)
@@ -207,6 +208,7 @@ static void rx_descs_init(struct eth_device *dev)
desc_p->dmamac_next = &desc_table_p[0];
writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
+ priv->rx_currdescnum = 0;
}
static void descs_init(struct eth_device *dev)
--
2.10.1
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* Re: [PATCH 0/4] net/designware: A few patches from U-Boot
2016-11-07 18:16 [PATCH 0/4] net/designware: A few patches from U-Boot Ian Abbott
` (3 preceding siblings ...)
2016-11-07 18:16 ` [PATCH 4/4] net/designware: add explicit reset of {tx|rx}_currdescnum Ian Abbott
@ 2016-11-10 8:49 ` Sascha Hauer
2016-11-10 10:26 ` Ian Abbott
2016-11-10 14:04 ` Sascha Hauer
5 siblings, 1 reply; 8+ messages in thread
From: Sascha Hauer @ 2016-11-10 8:49 UTC (permalink / raw)
To: Ian Abbott; +Cc: barebox
Hi Ian,
On Mon, Nov 07, 2016 at 06:16:20PM +0000, Ian Abbott wrote:
> Here are a few old-ish patches for the Synopsys Designware Ethernet
> driver, ported over from U-Boot.
>
> 1) net/designware: Consecutive writes to the same register to be avoided
> 2) net/designware: Do not select MIIPORT for RGMII interface
> 3) net: designware: Respect "bus mode" register contents on SW reset
> 4) net/designware: add explicit reset of {tx|rx}_currdescnum
The patches look ok to me. Do you want me to apply them or should we
rather wait until you resolved your network issues?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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* Re: [PATCH 0/4] net/designware: A few patches from U-Boot
2016-11-10 8:49 ` [PATCH 0/4] net/designware: A few patches from U-Boot Sascha Hauer
@ 2016-11-10 10:26 ` Ian Abbott
0 siblings, 0 replies; 8+ messages in thread
From: Ian Abbott @ 2016-11-10 10:26 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
Hi Sascha,
On 10/11/16 08:49, Sascha Hauer wrote:
> On Mon, Nov 07, 2016 at 06:16:20PM +0000, Ian Abbott wrote:
>> Here are a few old-ish patches for the Synopsys Designware Ethernet
>> driver, ported over from U-Boot.
>>
>> 1) net/designware: Consecutive writes to the same register to be avoided
>> 2) net/designware: Do not select MIIPORT for RGMII interface
>> 3) net: designware: Respect "bus mode" register contents on SW reset
>> 4) net/designware: add explicit reset of {tx|rx}_currdescnum
>
> The patches look ok to me. Do you want me to apply them or should we
> rather wait until you resolved your network issues?
I'm fine with you applying them. I think my network issues maybe more
hardware related.
--
-=( Ian Abbott @ MEV Ltd. E-mail: <abbotti@mev.co.uk> )=-
-=( Web: http://www.mev.co.uk/ )=-
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* Re: [PATCH 0/4] net/designware: A few patches from U-Boot
2016-11-07 18:16 [PATCH 0/4] net/designware: A few patches from U-Boot Ian Abbott
` (4 preceding siblings ...)
2016-11-10 8:49 ` [PATCH 0/4] net/designware: A few patches from U-Boot Sascha Hauer
@ 2016-11-10 14:04 ` Sascha Hauer
5 siblings, 0 replies; 8+ messages in thread
From: Sascha Hauer @ 2016-11-10 14:04 UTC (permalink / raw)
To: Ian Abbott; +Cc: barebox
On Mon, Nov 07, 2016 at 06:16:20PM +0000, Ian Abbott wrote:
> Here are a few old-ish patches for the Synopsys Designware Ethernet
> driver, ported over from U-Boot.
>
> 1) net/designware: Consecutive writes to the same register to be avoided
> 2) net/designware: Do not select MIIPORT for RGMII interface
> 3) net: designware: Respect "bus mode" register contents on SW reset
> 4) net/designware: add explicit reset of {tx|rx}_currdescnum
>
> drivers/net/designware.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
Applied, thanks
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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