From: Sascha Hauer <s.hauer@pengutronix.de>
To: Jose Luis Zabalza <jlz.3008@gmail.com>
Cc: barebox@lists.infradead.org
Subject: Re: Configure RAM size on iMX53 board
Date: Tue, 8 Nov 2016 08:53:17 +0100 [thread overview]
Message-ID: <20161108075317.j4xkf7zpkdfyt5y3@pengutronix.de> (raw)
In-Reply-To: <CAKZffXG6vuJjaQqB9QYSMeSocWZY33vFLSrWfCFf=0ATMM1fkQ@mail.gmail.com>
On Tue, Nov 08, 2016 at 06:09:52AM +0100, Jose Luis Zabalza wrote:
> Thanks Sascha
>
> RAM memory reference is MT41K128M16JT-125 XIT
> https://www.micron.com/parts/dram/ddr3-sdram/mt41k128m16jt-125-xit
>
> ================<cut>=========================
> barebox 2016.09.0-00071-ga38b701-dirty #11 Tue Nov 8 05:56:31 CET 2016
>
>
> Board: MyBoard i.MX53
> detected i.MX53 revision 2.1
> CS0: 0x20000000
> CS1: 0x20000000
> ...
>
> ================<cut>=========================
So you have 512MiB on each chip select, so I assume that on the 512MiB
board variants CS1 is not equipped. In that case you can in lowlevel.c
test if you find SDRAM on CS1 and if not, disable the chip select
completely in the SDRAM controller.
I am not sure how you can detect if there's SDRAM on CS1. I've seen
situations in which the board just hangs if you access non existent RAM
areas.
Sascha
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next prev parent reply other threads:[~2016-11-08 7:53 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-03 20:30 Jose Luis Zabalza
2016-11-03 22:42 ` Andrey Smirnov
2016-11-04 7:18 ` Sascha Hauer
2016-11-05 6:39 ` Jose Luis Zabalza
2016-11-07 7:43 ` Sascha Hauer
2016-11-08 5:09 ` Jose Luis Zabalza
2016-11-08 7:53 ` Sascha Hauer [this message]
2016-11-08 20:51 ` Jose Luis Zabalza
2016-11-08 21:24 ` Sascha Hauer
2016-11-09 4:23 ` Jose Luis Zabalza
2016-11-09 6:41 ` Sascha Hauer
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