From: Sascha Hauer <s.hauer@pengutronix.de>
To: Lucas Stach <l.stach@pengutronix.de>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH 2/3] ARM: correctly identify ARMv6 K/Z
Date: Fri, 3 Mar 2017 07:04:55 +0100 [thread overview]
Message-ID: <20170303060455.2s5gge5wpf3cjjpe@pengutronix.de> (raw)
In-Reply-To: <1488451368.2526.1.camel@pengutronix.de>
On Thu, Mar 02, 2017 at 11:42:48AM +0100, Lucas Stach wrote:
> Am Mittwoch, den 01.03.2017, 18:55 +0100 schrieb Jean-Christophe
> PLAGNIOL-VILLARD:
> > On 15:26 Wed 01 Mar , Lucas Stach wrote:
> > > The ARMv6 K/Z derivatives have a v7 compatible MMU, but all other
> > > parts
> > > (including the cache handling) is still at v6. As we don't make use
> > > of
> > > the more advanced features of the v7 MMU in Barebox, it's okay to
> > > just
> > > override this to properly identify the CPU as ARMv6.
> >
> > evenif we do not use it now I do not liek the idea to report it as
> > ARMv6
> >
> > It will be better to report it correctly
> >
> Weather you like it or not, ARM1176 is ARMv6 with a v7 MMU bolted on,
> so reporting it as ARMv6 is the correct thing to do.
+1
Sascha
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next prev parent reply other threads:[~2017-03-03 6:05 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-01 14:26 [PATCH 1/3] ARM: align exception vectors to 32 byte Lucas Stach
2017-03-01 14:26 ` [PATCH 2/3] ARM: correctly identify ARMv6 K/Z Lucas Stach
2017-03-01 17:55 ` Jean-Christophe PLAGNIOL-VILLARD
2017-03-02 10:42 ` Lucas Stach
2017-03-03 6:04 ` Sascha Hauer [this message]
2017-03-03 14:26 ` Jean-Christophe PLAGNIOL-VILLARD
2017-03-01 14:26 ` [PATCH 3/3] ARM: execute DMB before trying to flush cache Lucas Stach
2017-03-02 8:08 ` [PATCH 1/3] ARM: align exception vectors to 32 byte Uwe Kleine-König
2017-03-03 6:06 ` Sascha Hauer
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