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From: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
To: barebox@lists.infradead.org
Cc: andrey.gusakov@cogentembedded.com, Chris.Healy@zii.aero
Subject: [PATCH 7/8] video: tc358767: filter out modes with too high pixelclock
Date: Fri, 30 Jun 2017 14:43:03 +0300	[thread overview]
Message-ID: <20170630114304.8070-8-andrey.gusakov@cogentembedded.com> (raw)
In-Reply-To: <20170630114304.8070-1-andrey.gusakov@cogentembedded.com>

Minimum pixel clock period is 6.5 nS for DPI. Remove modes with
lower pixel clock period. Also sort modes in decreasing order
because currently first resolution in list is picked.
---
 drivers/video/tc358767.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 83 insertions(+)

diff --git a/drivers/video/tc358767.c b/drivers/video/tc358767.c
index 1541b18c9..61695b61c 100644
--- a/drivers/video/tc358767.c
+++ b/drivers/video/tc358767.c
@@ -1210,6 +1210,82 @@ err:
 	return ret;
 }
 
+static int tc_filter_videomodes(struct tc_data *tc, struct display_timings *timings)
+{
+	int i;
+	int num_modes = 0;
+	struct fb_videomode *mode, *valid_modes;
+
+	valid_modes = xzalloc(timings->num_modes * sizeof(struct fb_videomode));
+
+	/* first filter modes with too high pclock */
+	for (i = 0; i < timings->num_modes; i++) {
+		mode = &timings->modes[i];
+
+		/* minimum Pixel Clock Period for DPI is 6.5 nS = 6500 pS */
+		if (mode->pixclock < 6500) {
+			dev_dbg(tc->dev, "%dx%d@%d (%d KHz, flags 0x%08x, sync 0x%08x) skipped\n",
+				mode->xres, mode->yres, mode->refresh,
+				(int)PICOS2KHZ(mode->pixclock), mode->display_flags,
+				mode->sync);
+			/* remove from list */
+			mode->xres = mode->yres = 0;
+		}
+	}
+
+	/* then sort from hi to low */
+	do {
+		int index = -1;
+
+		/* find higest resolution */
+		for (i = 0; i < timings->num_modes; i++) {
+			mode = &timings->modes[i];
+			if (!(mode->xres && mode->yres))
+				continue;
+			if (index == -1) {
+				index = i;
+			} else {
+				/* compare square */
+				if (timings->modes[index].xres * timings->modes[index].yres <
+				    mode->xres * mode->yres)
+					index = i;
+			}
+		}
+
+		/* nothing left */
+		if (index == -1)
+			break;
+
+		/* copy to output list */
+		mode = &timings->modes[index];
+		memcpy(&valid_modes[num_modes], mode, sizeof(struct fb_videomode));
+		mode->xres = mode->yres = 0;
+		num_modes++;
+	} while (1);
+
+	free(timings->modes);
+	timings->modes = NULL;
+
+	if (!num_modes) {
+		free(valid_modes);
+		return -EINVAL;
+	}
+
+	timings->num_modes = num_modes;
+	timings->modes = valid_modes;
+
+	dev_dbg(tc->dev, "Valid modes (%d):\n", num_modes);
+	for (i = 0; i < timings->num_modes; i++) {
+		mode = &timings->modes[i];
+		dev_dbg(tc->dev, "%dx%d@%d (%d KHz, flags 0x%08x, sync 0x%08x)\n",
+			mode->xres, mode->yres, mode->refresh,
+			(int)PICOS2KHZ(mode->pixclock), mode->display_flags,
+			mode->sync);
+	}
+
+	return 0;
+}
+
 static int tc_get_videomodes(struct tc_data *tc, struct display_timings *timings)
 {
 	int ret;
@@ -1229,6 +1305,13 @@ static int tc_get_videomodes(struct tc_data *tc, struct display_timings *timings
 		return ret;
 	}
 
+	/* filter out unsupported due to high pixelxlock */
+	ret = tc_filter_videomodes(tc, timings);
+	if (ret < 0) {
+		dev_err(tc->dev, "No supported modes found\n");
+		return ret;
+	}
+
 	/* hsync, vsync active low */
 	timings->modes->sync &= ~(FB_SYNC_HOR_HIGH_ACT |
 				  FB_SYNC_VERT_HIGH_ACT);
-- 
2.13.0


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  parent reply	other threads:[~2017-06-30 11:41 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-30 11:42 [PATCH 0/8] video: tc358767: fixes and improvements Andrey Gusakov
2017-06-30 11:42 ` [PATCH 1/8] video: tc358767: do not fail if sink supports more than 2 lanes Andrey Gusakov
2017-06-30 11:42 ` [PATCH 2/8] video: tc358767: support newer DPCD revisions and higher data rates Andrey Gusakov
2017-06-30 11:42 ` [PATCH 3/8] video: tc358767: fix EDID read for DP displays Andrey Gusakov
2017-06-30 11:43 ` [PATCH 4/8] video: tc358767: fix DP0_MISC register set Andrey Gusakov
2017-06-30 11:43 ` [PATCH 5/8] video: tc358767: fix timing calculation Andrey Gusakov
2017-07-03  9:19   ` Lucas Stach
2017-06-30 11:43 ` [PATCH 6/8] video: tc358767: fix AUXDATAn registers access Andrey Gusakov
2017-07-03  9:22   ` Lucas Stach
2017-06-30 11:43 ` Andrey Gusakov [this message]
2017-06-30 11:43 ` [PATCH 8/8] video: tc358767: accept any hsync and vsync polatiry Andrey Gusakov
2017-07-03  9:27 ` [PATCH 0/8] video: tc358767: fixes and improvements Lucas Stach

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