Re: [PATCH 0/2] spi: imx: don't loop endlessly

["Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>]

On Wed, Aug 02, 2017 at 10:32:40PM +0200, Sam Ravnborg wrote:
> Hi Uwe.
> > I havn't looked at it, but it is included in my barebox as I'm using
> > 2017.08.0 + some patches.
> And I did not expect it to solve your problem, only to give you
> inspiration what could be the issue.
> 
> > 
> > Reading through the patch description, it doesn't match my situation.
> OK
> 
> > I'm doing USB-Booting because when I made eMMC work all my available
> > remote hands already called it a day. So unless the boot ROM does
> > something strange (impossible!) barebox is the first spi user.
> > 
> > What seems to be similar is that TESTREG.TXCNT is != 0. For me this
> > smells clk-related. On i.MX6 I recently identified a problem (but didn't
> > come around yet to mainline a fix) that might match at least your
> > problem.
> > 
> > Can you still reproduce?
> We have used the patch from Sascha for a long time now (from before it
> hit barebox-next, and on our proprietary IMX6 target we never
> saw the SPI related error since.
> 
> 	Sam
> 
> > How does your clk-tree look like (clk_dump)?
> 
> This is with:
> $ version
> barebox 2017.03.0-1 #1 Sun May 14 16:17:24 CEST 2017
> + some of our own patches (nothing clk related).
> 
> $ clk_dump
> [...]
>             ecspi_root (rate 60000000, enabled)
>                 ecspi1 (rate 60000000, enabled)
>                 ecspi2 (rate 60000000, enabled)
>                 ecspi3 (rate 60000000, enabled)
>                 ecspi4 (rate 60000000, enabled)
>                 ecspi5 (rate 60000000, enabled)

ecspi_root is defined as:

	clks[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);

The RM (Reference Manual) describes this register as follows:

	CCM_CSCDR2, bits 24–19: ... NOTE: Divider should be updated when
	output clock is gated.

It seems the BOOTROM in some older revisions of the chips didn't respect
this requirement (for a different clk though) which resulted in
ERR007117 (described in the ChipErrata document for the i.XM6DQ):

	For raw NAND boot, ROM switches the source of enfc_clk_root from
	PLL2_PFD2 to PLL3. The root clock is required to be gated before
	switching the source clock. If the root clock is not gated, clock
	glitches might be passed to the divider that follows the clock mux, and
	the divider might behave unpredictably. This can cause the clock
	generation to fail and the chip will not boot successfully.
	
	This problem can also occur elsewhere in application code if the
	root clock is not properly gated when the clock configuration is
	changed.

IMHO this fits nicely to your error description. i.MX6UL is affected for
sure as it does

        clk_set_parent(clks[IMX6UL_CLK_ENFC_SEL], clks[IMX6UL_CLK_PLL2_PFD2]);

without making sure that some affected clks are off. This resulted in
failures to probe the NAND occasionally on a customer machine.

For i.MX6SDL or i.MX6DQ I don't see a matching change for the ecspi_root
clk, but maybe this is triggered by setting the frequency on one of the
child clocks?!

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

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