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From: Sascha Hauer <s.hauer@pengutronix.de>
To: Barebox List <barebox@lists.infradead.org>
Subject: [PATCH] ARM: am335x: beaglebone: Fix DDR register values
Date: Thu,  1 Mar 2018 12:31:05 +0100	[thread overview]
Message-ID: <20180301113105.18150-1-s.hauer@pengutronix.de> (raw)

For the DDR2 PHY register values there are tons of warnings that more
than 32bit are required to store the values. Looking at the reference
manual it seems only the lower ten bits have any meaning, so drop all
other values.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/beaglebone/lowlevel.c | 26 ++++++--------------------
 1 file changed, 6 insertions(+), 20 deletions(-)

diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c
index a56b4b6240..f2e1690b15 100644
--- a/arch/arm/boards/beaglebone/lowlevel.c
+++ b/arch/arm/boards/beaglebone/lowlevel.c
@@ -48,26 +48,12 @@ static const struct am33xx_emif_regs ddr2_regs = {
 };
 
 static const struct am33xx_ddr_data ddr2_data = {
-	.rd_slave_ratio0        = (DDR2_RD_DQS << 30) | (DDR2_RD_DQS << 20) |
-				(DDR2_RD_DQS << 10) | (DDR2_RD_DQS << 0),
-	.wr_dqs_slave_ratio0    = (DDR2_WR_DQS << 30) | (DDR2_WR_DQS << 20) |
-				(DDR2_WR_DQS << 10) | (DDR2_WR_DQS << 0),
-	.wrlvl_init_ratio0	= (DDR2_PHY_WRLVL << 30) |
-				(DDR2_PHY_WRLVL << 20) |
-				(DDR2_PHY_WRLVL << 10) |
-				(DDR2_PHY_WRLVL << 0),
-	.gatelvl_init_ratio0	= (DDR2_PHY_GATELVL << 30) |
-				(DDR2_PHY_GATELVL << 20) |
-				(DDR2_PHY_GATELVL << 10) |
-				(DDR2_PHY_GATELVL << 0),
-	.fifo_we_slave_ratio0	= (DDR2_PHY_FIFO_WE << 30) |
-				(DDR2_PHY_FIFO_WE << 20) |
-				(DDR2_PHY_FIFO_WE << 10) |
-				(DDR2_PHY_FIFO_WE << 0),
-	.wr_slave_ratio0        = (DDR2_PHY_WR_DATA << 30) |
-				(DDR2_PHY_WR_DATA << 20) |
-				(DDR2_PHY_WR_DATA << 10) |
-				(DDR2_PHY_WR_DATA << 0),
+	.rd_slave_ratio0        = DDR2_RD_DQS,
+	.wr_dqs_slave_ratio0    = DDR2_WR_DQS,
+	.wrlvl_init_ratio0	= DDR2_PHY_WRLVL,
+	.gatelvl_init_ratio0	= DDR2_PHY_GATELVL,
+	.fifo_we_slave_ratio0	= DDR2_PHY_FIFO_WE,
+	.wr_slave_ratio0        = DDR2_PHY_WR_DATA,
 	.use_rank0_delay	= 0x01,
 	.dll_lock_diff0		= 0x0,
 };
-- 
2.16.1


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                 reply	other threads:[~2018-03-01 11:31 UTC|newest]

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