* [PATCH v2 01/48] ARM: i.MX: xload: Fix compiler warning
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-27 7:28 ` Sam Ravnborg
2018-05-26 20:44 ` [PATCH v2 02/48] ARM: i.MX: compile arm32 specific errata only for CPU32 Andrey Smirnov
` (46 subsequent siblings)
47 siblings, 1 reply; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
the ESDHC controller is a 32bit device, so can do DMA only on the
lower 32bit. Fix the compiler warning about casting a pointer to integer
of different size on aarch64 by casting to unsigned long first. Error
out if the destination does not fit into 32bit though.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/xload-esdhc.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/xload-esdhc.c b/arch/arm/mach-imx/xload-esdhc.c
index e774e4e68..bd58bdc64 100644
--- a/arch/arm/mach-imx/xload-esdhc.c
+++ b/arch/arm/mach-imx/xload-esdhc.c
@@ -109,8 +109,13 @@ esdhc_send_cmd(struct esdhc *esdhc, struct mci_cmd *cmd, struct mci_data *data)
__udelay(1);
if (data) {
+ unsigned long dest = (unsigned long)data->dest;
+
+ if (dest > 0xffffffff)
+ return -EINVAL;
+
/* Set up for a data transfer if we have one */
- esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)data->dest);
+ esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)dest);
esdhc_write32(regs + SDHCI_BLOCK_SIZE__BLOCK_COUNT, data->blocks << 16 | SECTOR_SIZE);
}
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* Re: [PATCH v2 01/48] ARM: i.MX: xload: Fix compiler warning
2018-05-26 20:44 ` [PATCH v2 01/48] ARM: i.MX: xload: Fix compiler warning Andrey Smirnov
@ 2018-05-27 7:28 ` Sam Ravnborg
2018-05-28 1:03 ` Andrey Smirnov
0 siblings, 1 reply; 57+ messages in thread
From: Sam Ravnborg @ 2018-05-27 7:28 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: barebox
Hi Andrey
On Sat, May 26, 2018 at 01:44:04PM -0700, Andrey Smirnov wrote:
> From: Sascha Hauer <s.hauer@pengutronix.de>
>
> the ESDHC controller is a 32bit device, so can do DMA only on the
> lower 32bit. Fix the compiler warning about casting a pointer to integer
> of different size on aarch64 by casting to unsigned long first. Error
> out if the destination does not fit into 32bit though.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
Nitpicking...
In the kernel the "Signed-off-by:" lines shall document the path of the patch
towards the kernel. So every time a patch passes a person, this person is supposed
to add a "Signed-off" to explicit say that:
"
The contribution was provided directly to me by some other
person who certified (a), (b) or (c) and I have not modified
it.
"
From Documentation/process/submitting-patches.rst
So in other words - I had expected to see:
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Andrey Smirnov <...>
And then, when Sasha apply the patch he adds a third "Signed-off".
I dunno how strong the rules are followed for barebox,
and you can also find many examples in the kernel where
the rules are not followed strict.
But in general this is how it is used.
Sam
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* Re: [PATCH v2 01/48] ARM: i.MX: xload: Fix compiler warning
2018-05-27 7:28 ` Sam Ravnborg
@ 2018-05-28 1:03 ` Andrey Smirnov
0 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-28 1:03 UTC (permalink / raw)
To: Sam Ravnborg; +Cc: Barebox List
On Sun, May 27, 2018 at 12:28 AM, Sam Ravnborg <sam@ravnborg.org> wrote:
> Hi Andrey
>
> On Sat, May 26, 2018 at 01:44:04PM -0700, Andrey Smirnov wrote:
>> From: Sascha Hauer <s.hauer@pengutronix.de>
>>
>> the ESDHC controller is a 32bit device, so can do DMA only on the
>> lower 32bit. Fix the compiler warning about casting a pointer to integer
>> of different size on aarch64 by casting to unsigned long first. Error
>> out if the destination does not fit into 32bit though.
>>
>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>> ---
> Nitpicking...
>
> In the kernel the "Signed-off-by:" lines shall document the path of the patch
> towards the kernel. So every time a patch passes a person, this person is supposed
> to add a "Signed-off" to explicit say that:
Hmm, that's not really how I interpret "11) Sign your work - the
Developer's Certificate of Origin". Not saying that my interpretation
is right, but I added Signed-off-by's with "To improve tracking of who
did what" goal in mind.
> "
> The contribution was provided directly to me by some other
> person who certified (a), (b) or (c) and I have not modified
> it.
> "
Yeah, that's item (c), which I can't really certify since there was no
direct communication involved and I just got the patches that Sascha
previously posted on the mailing list ([v1] in the cover letter).
Items (a) and (b) don't really seem applicable to me, since they all
involve me being responsible for writing some portion of the patch.
Anyway, it is trivial for me to add those, and I am more than happy to
do it, but since I am lazy, I'll wait for Sascha's say-so for that.
Thanks,
Andrey Smirnov
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH v2 02/48] ARM: i.MX: compile arm32 specific errata only for CPU32
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 01/48] ARM: i.MX: xload: Fix compiler warning Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 03/48] ARM: Add i.MX8 support Andrey Smirnov
` (45 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/cpu_init.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
index 6a6c4c521..5b93d12da 100644
--- a/arch/arm/mach-imx/cpu_init.c
+++ b/arch/arm/mach-imx/cpu_init.c
@@ -16,6 +16,7 @@
#include <asm/errata.h>
#include <linux/types.h>
+#ifdef CONFIG_CPU_32
void imx5_cpu_lowlevel_init(void)
{
arm_cpu_lowlevel_init();
@@ -50,3 +51,4 @@ void vf610_cpu_lowlevel_init(void)
{
arm_cpu_lowlevel_init();
}
+#endif
\ No newline at end of file
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 03/48] ARM: Add i.MX8 support
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 01/48] ARM: i.MX: xload: Fix compiler warning Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 02/48] ARM: i.MX: compile arm32 specific errata only for CPU32 Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 04/48] aarch64: Add i.MX8 debug UART support Andrey Smirnov
` (44 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/imx8mq-pinfunc.h | 623 +++++++++++++++++
arch/arm/dts/imx8mq.dtsi | 624 +++++++++++++++++
arch/arm/mach-imx/Kconfig | 9 +
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/imx.c | 4 +
arch/arm/mach-imx/imx8mq.c | 66 ++
arch/arm/mach-imx/include/mach/generic.h | 13 +
arch/arm/mach-imx/include/mach/imx8mq-regs.h | 121 ++++
.../arm/mach-imx/include/mach/imx_cpu_types.h | 1 +
include/dt-bindings/clock/imx8mq-clock.h | 629 ++++++++++++++++++
10 files changed, 2091 insertions(+)
create mode 100644 arch/arm/dts/imx8mq-pinfunc.h
create mode 100644 arch/arm/dts/imx8mq.dtsi
create mode 100644 arch/arm/mach-imx/imx8mq.c
create mode 100644 arch/arm/mach-imx/include/mach/imx8mq-regs.h
create mode 100644 include/dt-bindings/clock/imx8mq-clock.h
diff --git a/arch/arm/dts/imx8mq-pinfunc.h b/arch/arm/dts/imx8mq-pinfunc.h
new file mode 100644
index 000000000..b94b02080
--- /dev/null
+++ b/arch/arm/dts/imx8mq-pinfunc.h
@@ -0,0 +1,623 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef __DTS_IMX8MQ_PINFUNC_H
+#define __DTS_IMX8MQ_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1
+#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1
+#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3
+#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1
+#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2
+#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2
+#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2
+#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2
+#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3
+#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2
+#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1
+#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2
+#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
+#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
+#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2
+#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1
+#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
+#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
+#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1
+#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0
+
+#endif /* __DTS_IMX8MQ_PINFUNC_H */
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
new file mode 100644
index 000000000..c67438a48
--- /dev/null
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -0,0 +1,624 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2017 NXP
+ * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+#include <dt-bindings/clock/imx8mq-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "imx8mq-pinfunc.h"
+
+/* first 128 KiB of memory are owned by ATF */
+/memreserve/ 0x40000000 0x00020000;
+
+/ {
+ /* This should really be the GPC, but we need a driver for this first */
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ };
+
+ ckil: clk-ckil {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ckil";
+ };
+
+ osc_25m: clk-osc-25m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "osc_25m";
+ };
+
+ osc_27m: clk-osc-27m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ clock-output-names = "osc_27m";
+ };
+
+ clk_ext1: clk-ext1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext1";
+ };
+
+ clk_ext2: clk-ext2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext2";
+ };
+
+ clk_ext3: clk-ext3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext3";
+ };
+
+ clk_ext4: clk-ext4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency= <133000000>;
+ clock-output-names = "clk_ext4";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ A53_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ };
+
+ A53_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ };
+
+ A53_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ };
+
+ A53_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ };
+
+ A53_L2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
+ interrupt-parent = <&gic>;
+ arm,no-tick-in-suspend;
+ };
+
+ display-subsystem {
+ compatible = "fsl,imx-display-subsystem";
+ ports = <&dcss_disp0>;
+ };
+
+ peripherals@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x3e000000>;
+
+ bus@30000000 { /* AIPS1 */
+ compatible = "fsl,imx8mq-aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x30000000 0x30000000 0x400000>;
+
+ gpio1: gpio@30200000 {
+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+ reg = <0x30200000 0x10000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@30210000 {
+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+ reg = <0x30210000 0x10000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@30220000 {
+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+ reg = <0x30220000 0x10000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@30230000 {
+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+ reg = <0x30230000 0x10000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@30240000 {
+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+ reg = <0x30240000 0x10000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ iomuxc: iomuxc@30330000 {
+ compatible = "fsl,imx8mq-iomuxc";
+ reg = <0x30330000 0x10000>;
+ };
+
+ gpr: iomuxc-gpr@30340000 {
+ compatible = "fsl,imx8mq-iomuxc-gpr", "syscon";
+ reg = <0x30340000 0x10000>;
+ };
+
+ ocotp: ocotp@30350000 {
+ compatible = "fsl,imx8mq-ocotp";
+ reg = <0x30350000 0x10000>;
+ clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
+ };
+
+ anatop: anatop@30360000 {
+ compatible = "fsl,imx8mq-anatop", "syscon";
+ reg = <0x30360000 0x10000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ clk: clock-controller@30380000 {
+ compatible = "fsl,imx8mq-ccm";
+ reg = <0x30380000 0x10000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
+ <&clk_ext1>, <&clk_ext2>,
+ <&clk_ext3>, <&clk_ext4>;
+ clock-names = "ckil", "osc_25m", "osc_27m",
+ "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4";
+ };
+
+ wdog1: watchdog@30280000 {
+ compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
+ reg = <0x30280000 0x10000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
+ status = "disabled";
+ };
+
+ wdog2: watchdog@30290000 {
+ compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
+ reg = <0x30290000 0x10000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
+ status = "disabled";
+ };
+
+ wdog3: watchdog@302a0000 {
+ compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
+ reg = <0x302a0000 0x10000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
+ status = "disabled";
+ };
+ };
+
+ bus@30400000 { /* AIPS2 */
+ compatible = "fsl,imx8mq-aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x30400000 0x30400000 0x400000>;
+ };
+
+ bus@30800000 { /* AIPS3 */
+ compatible = "fsl,imx8mq-aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x30800000 0x30800000 0x400000>;
+
+ uart1: serial@30860000 {
+ compatible = "fsl,imx8mq-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30860000 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
+ <&clk IMX8MQ_CLK_UART1_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart3: serial@30880000 {
+ compatible = "fsl,imx8mq-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30880000 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
+ <&clk IMX8MQ_CLK_UART3_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart2: serial@30890000 {
+ compatible = "fsl,imx8mq-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30890000 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
+ <&clk IMX8MQ_CLK_UART2_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ i2c1: i2c@30a20000 {
+ compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
+ reg = <0x30a20000 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@30a30000 {
+ compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
+ reg = <0x30a30000 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@30a40000 {
+ compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
+ reg = <0x30a40000 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@30a50000 {
+ compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
+ reg = <0x30a50000 0x10000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart4: serial@30a60000 {
+ compatible = "fsl,imx8mq-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30a60000 0x10000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
+ <&clk IMX8MQ_CLK_UART4_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ usdhc1: usdhc@30b40000 {
+ compatible = "fsl,imx8mq-usdhc",
+ "fsl,imx7d-usdhc";
+ reg = <0x30b40000 0x10000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_DUMMY>,
+ <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
+ <&clk IMX8MQ_CLK_USDHC1_ROOT>;
+ clock-names = "ipg", "ahb", "per";
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step = <2>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc2: usdhc@30b50000 {
+ compatible = "fsl,imx8mq-usdhc",
+ "fsl,imx7d-usdhc";
+ reg = <0x30b50000 0x10000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_DUMMY>,
+ <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
+ <&clk IMX8MQ_CLK_USDHC2_ROOT>;
+ clock-names = "ipg", "ahb", "per";
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step = <2>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ fec1: ethernet@30be0000 {
+ compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
+ reg = <0x30be0000 0x10000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
+ <&clk IMX8MQ_CLK_ENET1_ROOT>,
+ <&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
+ <&clk IMX8MQ_CLK_ENET_REF_DIV>,
+ <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref", "enet_out";
+ fsl,num-tx-queues = <3>;
+ fsl,num-rx-queues = <3>;
+ status = "disabled";
+ };
+ };
+
+ bus@32c00000 { /* AIPS4 */
+ compatible = "fsl,imx8mq-aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x32c00000 0x32c00000 0x400000>;
+
+ hdmi: hdmi@32c00000 {
+ compatible = "fsl,imx8mq-hdmi";
+ reg = <0x32c00000 0x33800>, /* HDP registers */
+ <0x32e40000 0x40000>; /* HDP SEC register */
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "plug_in", "plug_out";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+ hdmi_disp: endpoint {
+ remote-endpoint = <&dcss_disp0_hdmi>;
+ };
+ };
+ };
+
+ dcss: dcss@32e00000 {
+ compatible = "nxp,imx8mq-dcss";
+ reg = <0x32e00000 0x30000>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>,
+ <4 IRQ_TYPE_LEVEL_HIGH>,
+ <5 IRQ_TYPE_LEVEL_HIGH>,
+ <6 IRQ_TYPE_LEVEL_HIGH>,
+ <8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dpr_dc_ch0",
+ "dpr_dc_ch1",
+ "dpr_dc_ch2",
+ "ctx_ld",
+ "dtg_prg1";
+ interrupt-parent = <&irqsteer_dcss>;
+ clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
+ <&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
+ <&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
+ clock-names = "apb", "axi", "rtrm",
+ "pixel", "dtrc";
+ assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
+ <&clk IMX8MQ_CLK_DISP_AXI_SRC>,
+ <&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
+ <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>;
+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
+ <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_SYS1_PLL_800M>;
+ assigned-clock-rates = <594000000>,
+ <800000000>,
+ <400000000>,
+ <400000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ dcss_disp0: port@0 {
+ reg = <0>;
+ dcss_disp0_hdmi: hdmi-endpoint {
+ remote-endpoint = <&hdmi_disp>;
+ };
+ };
+ };
+
+ irqsteer_dcss: interrupt-controller@32e2d000 {
+ compatible = "nxp,imx-irqsteer";
+ reg = <0x32e2d000 0x1000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+ clock-names = "ipg";
+ nxp,channel = <2>;
+ nxp,endian = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ gpu: gpu@38000000 {
+ compatible = "vivante,gc";
+ reg = <0x38000000 0x40000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
+ <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
+ <&clk IMX8MQ_CLK_GPU_AXI_DIV>,
+ <&clk IMX8MQ_CLK_GPU_AHB_DIV>;
+ clock-names = "core", "shader", "bus", "reg";
+
+ assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
+ <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
+ <&clk IMX8MQ_CLK_GPU_AXI_SRC>,
+ <&clk IMX8MQ_CLK_GPU_AHB_SRC>;
+ assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
+ <&clk IMX8MQ_GPU_PLL_OUT>,
+ <&clk IMX8MQ_GPU_PLL_OUT>,
+ <&clk IMX8MQ_GPU_PLL_OUT>;
+ assigned-clock-rates = <800000000>, <800000000>,
+ <800000000>, <800000000>;
+ //power-domains = <&gpu_pd>;
+ };
+
+ usb3_0: usb0@38100000 {
+ compatible = "fsl,imx8mq-dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x38100000 0x38100000 0x10000>;
+ clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>;
+ clock-names = "usb1_ctrl_root_clk";
+ assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>,
+ <&clk IMX8MQ_CLK_USB_CORE_REF_SRC>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
+ <&clk IMX8MQ_SYS1_PLL_100M>;
+ assigned-clock-rates = <500000000>, <100000000>;
+ status = "disabled";
+
+ usb_dwc3_0: dwc3@38100000 {
+ compatible = "snps,dwc3";
+ reg = <0x38100000 0x10000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy0 0>, <&usb3_phy0 1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ //power-domains = <&usb_otg1_pd>;
+ snps,power-down-scale = <2>;
+ usb3-resume-missing-cas;
+ status = "disabled";
+ };
+ };
+
+ usb3_phy0: phy@381f0040 {
+ compatible = "fsl,imx8mq-usb-phy";
+ reg = <0x381f0040 0x40>;
+ clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
+ clock-names = "usb_phy_root_clk";
+ #phy-cells = <1>;
+
+ assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF_SRC>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
+ assigned-clock-rates = <100000000>;
+
+ status = "disabled";
+ };
+
+ usb3_1: usb1@38200000 {
+ compatible = "fsl,imx8mq-dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x38200000 0x38200000 0x10000>;
+ clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>;
+ clock-names = "usb2_ctrl_root_clk";
+ assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>,
+ <&clk IMX8MQ_CLK_USB_CORE_REF_SRC>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
+ <&clk IMX8MQ_SYS1_PLL_100M>;
+ assigned-clock-rates = <500000000>, <100000000>;
+ status = "disabled";
+
+ usb_dwc3_1: dwc3@38200000 {
+ compatible = "snps,dwc3";
+ reg = <0x38200000 0x10000>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy1 0>, <&usb3_phy1 1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ //power-domains = <&usb_otg2_pd>;
+ snps,power-down-scale = <2>;
+ usb3-resume-missing-cas;
+ status = "disabled";
+ };
+ };
+
+ usb3_phy1: phy@382f0040 {
+ compatible = "fsl,imx8mq-usb-phy";
+ reg = <0x382f0040 0x40>;
+ clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
+ clock-names = "usb_phy_root_clk";
+ #phy-cells = <1>;
+
+ assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF_SRC>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
+ assigned-clock-rates = <100000000>;
+
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@38800000 {
+ compatible = "arm,gic-v3";
+ reg = <0x38800000 0x10000>, /* GIC Dist */
+ <0x38880000 0xc0000>, /* GICR */
+ <0x31000000 0x2000>, /* GICC */
+ <0x31010000 0x2000>, /* GICV */
+ <0x31020000 0x2000>; /* GICH */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ };
+ };
+};
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index e6956acbd..85143bd26 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -170,6 +170,15 @@ config ARCH_IMX7
select COMMON_CLK_OF_PROVIDER
select ARCH_HAS_FEC_IMX
+config ARCH_IMX8MQ
+ bool
+ select CPU_V8
+ select PINCTRL_IMX_IOMUX_V3
+ select OFTREE
+ select SYS_SUPPORTS_64BIT_KERNEL
+ select COMMON_CLK_OF_PROVIDER
+ select ARCH_HAS_FEC_IMX
+
config ARCH_VF610
bool
select ARCH_HAS_L2X0
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 8ec846cce..a6385ff90 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_IMX6) += imx6.o usb-imx6.o
CFLAGS_imx6.o := -march=armv7-a
lwl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o
obj-$(CONFIG_ARCH_IMX7) += imx7.o
+obj-$(CONFIG_ARCH_IMX8MQ) += imx8mq.o
obj-$(CONFIG_ARCH_IMX_XLOAD) += xload.o
obj-$(CONFIG_IMX_IIM) += iim.o
obj-$(CONFIG_IMX_OCOTP) += ocotp.o
diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c
index 9400105c6..e5fe4a264 100644
--- a/arch/arm/mach-imx/imx.c
+++ b/arch/arm/mach-imx/imx.c
@@ -73,6 +73,8 @@ static int imx_soc_from_dt(void)
return IMX_CPU_IMX7;
if (of_machine_is_compatible("fsl,imx7d"))
return IMX_CPU_IMX7;
+ if (of_machine_is_compatible("fsl,imx8mq"))
+ return IMX_CPU_IMX8MQ;
if (of_machine_is_compatible("fsl,vf610"))
return IMX_CPU_VF610;
@@ -113,6 +115,8 @@ static int imx_init(void)
ret = imx6_init();
else if (cpu_is_mx7())
ret = imx7_init();
+ else if (cpu_is_mx8mq())
+ ret = imx8mq_init();
else if (cpu_is_vf610())
ret = 0;
else
diff --git a/arch/arm/mach-imx/imx8mq.c b/arch/arm/mach-imx/imx8mq.c
new file mode 100644
index 000000000..a9bd9f444
--- /dev/null
+++ b/arch/arm/mach-imx/imx8mq.c
@@ -0,0 +1,66 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <init.h>
+#include <common.h>
+#include <io.h>
+#include <mach/generic.h>
+#include <mach/revision.h>
+#include <mach/imx8mq-regs.h>
+
+#define IMX8MQ_ROM_VERSION_A0 0x800
+#define IMX8MQ_ROM_VERSION_B0 0x83C
+
+#define MX8MQ_ANATOP_DIGPROG 0x6c
+
+static void imx8mq_silicon_revision(void)
+{
+ void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR);
+ uint32_t reg = readl(anatop + MX8MQ_ANATOP_DIGPROG);
+ uint32_t type = (reg >> 16) & 0xff;
+ uint32_t rom_version;
+ const char *cputypestr;
+
+ reg &= 0xff;
+
+ if (reg == IMX_CHIP_REV_1_0) {
+ /*
+ * For B0 chip, the DIGPROG is not updated, still TO1.0.
+ * we have to check ROM version further
+ */
+ rom_version = readl(IOMEM(IMX8MQ_ROM_VERSION_A0));
+ if (rom_version != IMX_CHIP_REV_1_0) {
+ rom_version = readl(IOMEM(IMX8MQ_ROM_VERSION_B0));
+ if (rom_version >= IMX_CHIP_REV_2_0)
+ reg = IMX_CHIP_REV_1_0;
+ }
+ }
+
+ switch (type) {
+ case 0x82:
+ cputypestr = "i.MX8MQ";
+ break;
+ default:
+ cputypestr = "unknown i.MX8M";
+ break;
+ };
+
+ imx_set_silicon_revision(cputypestr, reg);
+}
+
+int imx8mq_init(void)
+{
+ imx8mq_silicon_revision();
+
+ return 0;
+}
diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h
index dedb4bbf0..204bd40f7 100644
--- a/arch/arm/mach-imx/include/mach/generic.h
+++ b/arch/arm/mach-imx/include/mach/generic.h
@@ -36,6 +36,7 @@ int imx51_init(void);
int imx53_init(void);
int imx6_init(void);
int imx7_init(void);
+int imx8mq_init(void);
int imx1_devices_init(void);
int imx21_devices_init(void);
@@ -193,6 +194,18 @@ extern unsigned int __imx_cpu_type;
# define cpu_is_mx7() (0)
#endif
+#ifdef CONFIG_ARCH_IMX8MQ
+# ifdef imx_cpu_type
+# undef imx_cpu_type
+# define imx_cpu_type __imx_cpu_type
+# else
+# define imx_cpu_type IMX_CPU_IMX8MQ
+# endif
+# define cpu_is_mx8mq() (imx_cpu_type == IMX_CPU_IMX8MQ)
+#else
+# define cpu_is_mx8mq() (0)
+#endif
+
#ifdef CONFIG_ARCH_VF610
# ifdef imx_cpu_type
# undef imx_cpu_type
diff --git a/arch/arm/mach-imx/include/mach/imx8mq-regs.h b/arch/arm/mach-imx/include/mach/imx8mq-regs.h
new file mode 100644
index 000000000..6dac00107
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx8mq-regs.h
@@ -0,0 +1,121 @@
+#ifndef __MACH_IMX8MQ_REGS_H
+#define __MACH_IMX8MQ_REGS_H
+
+#define MX8MQ_M4_BOOTROM_BASE_ADDR 0x007E0000
+
+#define MX8MQ_SAI1_BASE_ADDR 0x30010000
+#define MX8MQ_SAI6_BASE_ADDR 0x30030000
+#define MX8MQ_SAI5_BASE_ADDR 0x30040000
+#define MX8MQ_SAI4_BASE_ADDR 0x30050000
+#define MX8MQ_SPBA2_BASE_ADDR 0x300F0000
+#define MX8MQ_AIPS1_BASE_ADDR 0x301F0000
+#define MX8MQ_GPIO1_BASE_ADDR 0X30200000
+#define MX8MQ_GPIO2_BASE_ADDR 0x30210000
+#define MX8MQ_GPIO3_BASE_ADDR 0x30220000
+#define MX8MQ_GPIO4_BASE_ADDR 0x30230000
+#define MX8MQ_GPIO5_BASE_ADDR 0x30240000
+#define MX8MQ_ANA_TSENSOR_BASE_ADDR 0x30260000
+#define MX8MQ_ANA_OSC_BASE_ADDR 0x30270000
+#define MX8MQ_WDOG1_BASE_ADDR 0x30280000
+#define MX8MQ_WDOG2_BASE_ADDR 0x30290000
+#define MX8MQ_WDOG3_BASE_ADDR 0x302A0000
+#define MX8MQ_SDMA2_BASE_ADDR 0x302C0000
+#define MX8MQ_GPT1_BASE_ADDR 0x302D0000
+#define MX8MQ_GPT2_BASE_ADDR 0x302E0000
+#define MX8MQ_GPT3_BASE_ADDR 0x302F0000
+#define MX8MQ_ROMCP_BASE_ADDR 0x30310000
+#define MX8MQ_LCDIF_BASE_ADDR 0x30320000
+#define MX8MQ_IOMUXC_BASE_ADDR 0x30330000
+#define MX8MQ_IOMUXC_GPR_BASE_ADDR 0x30340000
+#define MX8MQ_OCOTP_BASE_ADDR 0x30350000
+#define MX8MQ_ANATOP_BASE_ADDR 0x30360000
+#define MX8MQ_SNVS_HP_BASE_ADDR 0x30370000
+#define MX8MQ_CCM_BASE_ADDR 0x30380000
+#define MX8MQ_SRC_BASE_ADDR 0x30390000
+#define MX8MQ_GPC_BASE_ADDR 0x303A0000
+#define MX8MQ_SEMAPHORE1_BASE_ADDR 0x303B0000
+#define MX8MQ_SEMAPHORE2_BASE_ADDR 0x303C0000
+#define MX8MQ_RDC_BASE_ADDR 0x303D0000
+#define MX8MQ_CSU_BASE_ADDR 0x303E0000
+
+#define MX8MQ_AIPS2_BASE_ADDR 0x305F0000
+#define MX8MQ_PWM1_BASE_ADDR 0x30660000
+#define MX8MQ_PWM2_BASE_ADDR 0x30670000
+#define MX8MQ_PWM3_BASE_ADDR 0x30680000
+#define MX8MQ_PWM4_BASE_ADDR 0x30690000
+#define MX8MQ_SYSCNT_RD_BASE_ADDR 0x306A0000
+#define MX8MQ_SYSCNT_CMP_BASE_ADDR 0x306B0000
+#define MX8MQ_SYSCNT_CTRL_BASE_ADDR 0x306C0000
+#define MX8MQ_GPT6_BASE_ADDR 0x306E0000
+#define MX8MQ_GPT5_BASE_ADDR 0x306F0000
+#define MX8MQ_GPT4_BASE_ADDR 0x30700000
+#define MX8MQ_PERFMON1_BASE_ADDR 0x307C0000
+#define MX8MQ_PERFMON2_BASE_ADDR 0x307D0000
+#define MX8MQ_QOSC_BASE_ADDR 0x307F0000
+
+#define MX8MQ_SPDIF1_BASE_ADDR 0x30810000
+#define MX8MQ_ECSPI1_BASE_ADDR 0x30820000
+#define MX8MQ_ECSPI2_BASE_ADDR 0x30830000
+#define MX8MQ_ECSPI3_BASE_ADDR 0x30840000
+#define MX8MQ_UART1_BASE_ADDR 0x30860000
+#define MX8MQ_UART3_BASE_ADDR 0x30880000
+#define MX8MQ_UART2_BASE_ADDR 0x30890000
+#define MX8MQ_SPDIF2_BASE_ADDR 0x308A0000
+#define MX8MQ_SAI2_BASE_ADDR 0x308B0000
+#define MX8MQ_SAI3_BASE_ADDR 0x308C0000
+#define MX8MQ_SPBA1_BASE_ADDR 0x308F0000
+#define MX8MQ_CAAM_BASE_ADDR 0x30900000
+#define MX8MQ_AIPS3_BASE_ADDR 0x309F0000
+#define MX8MQ_MIPI_PHY_BASE_ADDR 0x30A00000
+#define MX8MQ_MIPI_DSI_BASE_ADDR 0x30A10000
+#define MX8MQ_I2C1_BASE_ADDR 0x30A20000
+#define MX8MQ_I2C2_BASE_ADDR 0x30A30000
+#define MX8MQ_I2C3_BASE_ADDR 0x30A40000
+#define MX8MQ_I2C4_BASE_ADDR 0x30A50000
+#define MX8MQ_UART4_BASE_ADDR 0x30A60000
+#define MX8MQ_MIPI_CSI_BASE_ADDR 0x30A70000
+#define MX8MQ_MIPI_CSI_PHY1_BASE_ADDR 0x30A80000
+#define MX8MQ_CSI1_BASE_ADDR 0x30A90000
+#define MX8MQ_MU_A_BASE_ADDR 0x30AA0000
+#define MX8MQ_MU_B_BASE_ADDR 0x30AB0000
+#define MX8MQ_SEMAPHOR_HS_BASE_ADDR 0x30AC0000
+#define MX8MQ_USDHC1_BASE_ADDR 0x30B40000
+#define MX8MQ_USDHC2_BASE_ADDR 0x30B50000
+#define MX8MQ_MIPI_CS2_BASE_ADDR 0x30B60000
+#define MX8MQ_MIPI_CSI_PHY2_BASE_ADDR 0x30B70000
+#define MX8MQ_CSI2_BASE_ADDR 0x30B80000
+#define MX8MQ_QSPI0_BASE_ADDR 0x30BB0000
+#define MX8MQ_QSPI0_AMBA_BASE 0x08000000
+#define MX8MQ_SDMA1_BASE_ADDR 0x30BD0000
+#define MX8MQ_ENET1_BASE_ADDR 0x30BE0000
+
+#define MX8MQ_HDMI_CTRL_BASE_ADDR 0x32C00000
+#define MX8MQ_AIPS4_BASE_ADDR 0x32DF0000
+#define MX8MQ_DC1_BASE_ADDR 0x32E00000
+#define MX8MQ_DC2_BASE_ADDR 0x32E10000
+#define MX8MQ_DC3_BASE_ADDR 0x32E20000
+#define MX8MQ_HDMI_SEC_BASE_ADDR 0x32E40000
+#define MX8MQ_TZASC_BASE_ADDR 0x32F80000
+#define MX8MQ_MTR_BASE_ADDR 0x32FB0000
+#define MX8MQ_PLATFORM_CTRL_BASE_ADDR 0x32FE0000
+
+#define MX8MQ_MXS_APBH_BASE 0x33000000
+#define MX8MQ_MXS_GPMI_BASE 0x33002000
+#define MX8MQ_MXS_BCH_BASE 0x33004000
+
+#define MX8MQ_USB1_BASE_ADDR 0x38100000
+#define MX8MQ_USB2_BASE_ADDR 0x38200000
+#define MX8MQ_USB1_PHY_BASE_ADDR 0x381F0000
+#define MX8MQ_USB2_PHY_BASE_ADDR 0x382F0000
+
+#define MX8MQ_MXS_LCDIF_BASE LCDIF_BASE_ADDR
+
+#define MX8MQ_SRC_IPS_BASE_ADDR 0x30390000
+#define MX8MQ_SRC_DDRC_RCR_ADDR 0x30391000
+#define MX8MQ_SRC_DDRC2_RCR_ADDR 0x30391004
+
+#define MX8MQ_DDRC_DDR_SS_GPR0 0x3d000000
+#define MX8MQ_DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
+#define MX8MQ_DDR_CSD1_BASE_ADDR 0x40000000
+
+#endif /* __MACH_IMX8MQ_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx_cpu_types.h b/arch/arm/mach-imx/include/mach/imx_cpu_types.h
index f95ef6f13..754fb9822 100644
--- a/arch/arm/mach-imx/include/mach/imx_cpu_types.h
+++ b/arch/arm/mach-imx/include/mach/imx_cpu_types.h
@@ -12,6 +12,7 @@
#define IMX_CPU_IMX53 53
#define IMX_CPU_IMX6 6
#define IMX_CPU_IMX7 7
+#define IMX_CPU_IMX8MQ 8
#define IMX_CPU_VF610 610
#endif /* __MACH_IMX_CPU_TYPES_H */
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
new file mode 100644
index 000000000..7f880629e
--- /dev/null
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -0,0 +1,629 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
+#define __DT_BINDINGS_CLOCK_IMX8MQ_H
+
+#define IMX8MQ_CLK_DUMMY 0
+#define IMX8MQ_CLK_32K 1
+#define IMX8MQ_CLK_25M 2
+#define IMX8MQ_CLK_27M 3
+#define IMX8MQ_CLK_EXT1 4
+#define IMX8MQ_CLK_EXT2 5
+#define IMX8MQ_CLK_EXT3 6
+#define IMX8MQ_CLK_EXT4 7
+
+/* ANAMIX PLL clocks */
+/* FRAC PLLs */
+/* ARM PLL */
+#define IMX8MQ_ARM_PLL_REF_SEL 8
+#define IMX8MQ_ARM_PLL_REF_DIV 9
+#define IMX8MQ_ARM_PLL 10
+#define IMX8MQ_ARM_PLL_BYPASS 11
+#define IMX8MQ_ARM_PLL_OUT 12
+
+/* GPU PLL */
+#define IMX8MQ_GPU_PLL_REF_SEL 13
+#define IMX8MQ_GPU_PLL_REF_DIV 14
+#define IMX8MQ_GPU_PLL 15
+#define IMX8MQ_GPU_PLL_BYPASS 16
+#define IMX8MQ_GPU_PLL_OUT 17
+
+/* VPU PLL */
+#define IMX8MQ_VPU_PLL_REF_SEL 18
+#define IMX8MQ_VPU_PLL_REF_DIV 19
+#define IMX8MQ_VPU_PLL 20
+#define IMX8MQ_VPU_PLL_BYPASS 21
+#define IMX8MQ_VPU_PLL_OUT 22
+
+/* AUDIO PLL1 */
+#define IMX8MQ_AUDIO_PLL1_REF_SEL 23
+#define IMX8MQ_AUDIO_PLL1_REF_DIV 24
+#define IMX8MQ_AUDIO_PLL1 25
+#define IMX8MQ_AUDIO_PLL1_BYPASS 26
+#define IMX8MQ_AUDIO_PLL1_OUT 27
+
+/* AUDIO PLL2 */
+#define IMX8MQ_AUDIO_PLL2_REF_SEL 28
+#define IMX8MQ_AUDIO_PLL2_REF_DIV 29
+#define IMX8MQ_AUDIO_PLL2 30
+#define IMX8MQ_AUDIO_PLL2_BYPASS 31
+#define IMX8MQ_AUDIO_PLL2_OUT 32
+
+/* VIDEO PLL1 */
+#define IMX8MQ_VIDEO_PLL1_REF_SEL 33
+#define IMX8MQ_VIDEO_PLL1_REF_DIV 34
+#define IMX8MQ_VIDEO_PLL1 35
+#define IMX8MQ_VIDEO_PLL1_BYPASS 36
+#define IMX8MQ_VIDEO_PLL1_OUT 37
+
+/* SYS1 PLL */
+#define IMX8MQ_SYS1_PLL1_REF_SEL 38
+#define IMX8MQ_SYS1_PLL1_REF_DIV 39
+#define IMX8MQ_SYS1_PLL1 40
+#define IMX8MQ_SYS1_PLL1_OUT 41
+#define IMX8MQ_SYS1_PLL1_OUT_DIV 42
+#define IMX8MQ_SYS1_PLL2 43
+#define IMX8MQ_SYS1_PLL2_DIV 44
+#define IMX8MQ_SYS1_PLL2_OUT 45
+
+/* SYS2 PLL */
+#define IMX8MQ_SYS2_PLL1_REF_SEL 46
+#define IMX8MQ_SYS2_PLL1_REF_DIV 47
+#define IMX8MQ_SYS2_PLL1 48
+#define IMX8MQ_SYS2_PLL1_OUT 49
+#define IMX8MQ_SYS2_PLL1_OUT_DIV 50
+#define IMX8MQ_SYS2_PLL2 51
+#define IMX8MQ_SYS2_PLL2_DIV 52
+#define IMX8MQ_SYS2_PLL2_OUT 53
+
+/* SYS3 PLL */
+#define IMX8MQ_SYS3_PLL1_REF_SEL 54
+#define IMX8MQ_SYS3_PLL1_REF_DIV 55
+#define IMX8MQ_SYS3_PLL1 56
+#define IMX8MQ_SYS3_PLL1_OUT 57
+#define IMX8MQ_SYS3_PLL1_OUT_DIV 58
+#define IMX8MQ_SYS3_PLL2 59
+#define IMX8MQ_SYS3_PLL2_DIV 60
+#define IMX8MQ_SYS3_PLL2_OUT 61
+
+/* DRAM PLL */
+#define IMX8MQ_DRAM_PLL1_REF_SEL 62
+#define IMX8MQ_DRAM_PLL1_REF_DIV 63
+#define IMX8MQ_DRAM_PLL1 64
+#define IMX8MQ_DRAM_PLL1_OUT 65
+#define IMX8MQ_DRAM_PLL1_OUT_DIV 66
+#define IMX8MQ_DRAM_PLL2 67
+#define IMX8MQ_DRAM_PLL2_DIV 68
+#define IMX8MQ_DRAM_PLL2_OUT 69
+
+/* SYS PLL DIV */
+#define IMX8MQ_SYS1_PLL_40M 70
+#define IMX8MQ_SYS1_PLL_80M 71
+#define IMX8MQ_SYS1_PLL_100M 72
+#define IMX8MQ_SYS1_PLL_133M 73
+#define IMX8MQ_SYS1_PLL_160M 74
+#define IMX8MQ_SYS1_PLL_200M 75
+#define IMX8MQ_SYS1_PLL_266M 76
+#define IMX8MQ_SYS1_PLL_400M 77
+#define IMX8MQ_SYS1_PLL_800M 78
+
+#define IMX8MQ_SYS2_PLL_50M 79
+#define IMX8MQ_SYS2_PLL_100M 80
+#define IMX8MQ_SYS2_PLL_125M 81
+#define IMX8MQ_SYS2_PLL_166M 82
+#define IMX8MQ_SYS2_PLL_200M 83
+#define IMX8MQ_SYS2_PLL_250M 84
+#define IMX8MQ_SYS2_PLL_333M 85
+#define IMX8MQ_SYS2_PLL_500M 86
+#define IMX8MQ_SYS2_PLL_1000M 87
+
+/* CCM ROOT clocks */
+/* A53 */
+#define IMX8MQ_CLK_A53_SRC 88
+#define IMX8MQ_CLK_A53_CG 89
+#define IMX8MQ_CLK_A53_DIV 90
+/* M4 */
+#define IMX8MQ_CLK_M4_SRC 91
+#define IMX8MQ_CLK_M4_CG 92
+#define IMX8MQ_CLK_M4_DIV 93
+/* VPU */
+#define IMX8MQ_CLK_VPU_SRC 94
+#define IMX8MQ_CLK_VPU_CG 95
+#define IMX8MQ_CLK_VPU_DIV 96
+/* GPU CORE */
+#define IMX8MQ_CLK_GPU_CORE_SRC 97
+#define IMX8MQ_CLK_GPU_CORE_CG 98
+#define IMX8MQ_CLK_GPU_CORE_DIV 99
+/* GPU SHADER */
+#define IMX8MQ_CLK_GPU_SHADER_SRC 100
+#define IMX8MQ_CLK_GPU_SHADER_CG 101
+#define IMX8MQ_CLK_GPU_SHADER_DIV 102
+
+/* BUS TYPE */
+/* MAIN AXI */
+#define IMX8MQ_CLK_MAIN_AXI_SRC 103
+#define IMX8MQ_CLK_MAIN_AXI_CG 104
+#define IMX8MQ_CLK_MAIN_AXI_PRE_DIV 105
+#define IMX8MQ_CLK_MAIN_AXI_DIV 106
+/* ENET AXI */
+#define IMX8MQ_CLK_ENET_AXI_SRC 107
+#define IMX8MQ_CLK_ENET_AXI_CG 108
+#define IMX8MQ_CLK_ENET_AXI_PRE_DIV 109
+#define IMX8MQ_CLK_ENET_AXI_DIV 110
+/* NAND_USDHC_BUS */
+#define IMX8MQ_CLK_NAND_USDHC_BUS_SRC 111
+#define IMX8MQ_CLK_NAND_USDHC_BUS_CG 112
+#define IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV 113
+#define IMX8MQ_CLK_NAND_USDHC_BUS_DIV 114
+/* VPU BUS */
+#define IMX8MQ_CLK_VPU_BUS_SRC 115
+#define IMX8MQ_CLK_VPU_BUS_CG 116
+#define IMX8MQ_CLK_VPU_BUS_PRE_DIV 117
+#define IMX8MQ_CLK_VPU_BUS_DIV 118
+/* DISP_AXI */
+#define IMX8MQ_CLK_DISP_AXI_SRC 119
+#define IMX8MQ_CLK_DISP_AXI_CG 120
+#define IMX8MQ_CLK_DISP_AXI_PRE_DIV 121
+#define IMX8MQ_CLK_DISP_AXI_DIV 122
+/* DISP APB */
+#define IMX8MQ_CLK_DISP_APB_SRC 123
+#define IMX8MQ_CLK_DISP_APB_CG 124
+#define IMX8MQ_CLK_DISP_APB_PRE_DIV 125
+#define IMX8MQ_CLK_DISP_APB_DIV 126
+/* DISP RTRM */
+#define IMX8MQ_CLK_DISP_RTRM_SRC 127
+#define IMX8MQ_CLK_DISP_RTRM_CG 128
+#define IMX8MQ_CLK_DISP_RTRM_PRE_DIV 129
+#define IMX8MQ_CLK_DISP_RTRM_DIV 130
+/* USB_BUS */
+#define IMX8MQ_CLK_USB_BUS_SRC 131
+#define IMX8MQ_CLK_USB_BUS_CG 132
+#define IMX8MQ_CLK_USB_BUS_PRE_DIV 133
+#define IMX8MQ_CLK_USB_BUS_DIV 134
+/* GPU_AXI */
+#define IMX8MQ_CLK_GPU_AXI_SRC 135
+#define IMX8MQ_CLK_GPU_AXI_CG 136
+#define IMX8MQ_CLK_GPU_AXI_PRE_DIV 137
+#define IMX8MQ_CLK_GPU_AXI_DIV 138
+/* GPU_AHB */
+#define IMX8MQ_CLK_GPU_AHB_SRC 139
+#define IMX8MQ_CLK_GPU_AHB_CG 140
+#define IMX8MQ_CLK_GPU_AHB_PRE_DIV 141
+#define IMX8MQ_CLK_GPU_AHB_DIV 142
+/* NOC */
+#define IMX8MQ_CLK_NOC_SRC 143
+#define IMX8MQ_CLK_NOC_CG 144
+#define IMX8MQ_CLK_NOC_PRE_DIV 145
+#define IMX8MQ_CLK_NOC_DIV 146
+/* NOC_APB */
+#define IMX8MQ_CLK_NOC_APB_SRC 147
+#define IMX8MQ_CLK_NOC_APB_CG 148
+#define IMX8MQ_CLK_NOC_APB_PRE_DIV 149
+#define IMX8MQ_CLK_NOC_APB_DIV 150
+
+/* AHB */
+#define IMX8MQ_CLK_AHB_SRC 151
+#define IMX8MQ_CLK_AHB_CG 152
+#define IMX8MQ_CLK_AHB_PRE_DIV 153
+#define IMX8MQ_CLK_AHB_DIV 154
+/* AUDIO AHB */
+#define IMX8MQ_CLK_AUDIO_AHB_SRC 155
+#define IMX8MQ_CLK_AUDIO_AHB_CG 156
+#define IMX8MQ_CLK_AUDIO_AHB_PRE_DIV 157
+#define IMX8MQ_CLK_AUDIO_AHB_DIV 158
+
+/* DRAM_ALT */
+#define IMX8MQ_CLK_DRAM_ALT_SRC 159
+#define IMX8MQ_CLK_DRAM_ALT_CG 160
+#define IMX8MQ_CLK_DRAM_ALT_PRE_DIV 161
+#define IMX8MQ_CLK_DRAM_ALT_DIV 162
+/* DRAM APB */
+#define IMX8MQ_CLK_DRAM_APB_SRC 163
+#define IMX8MQ_CLK_DRAM_APB_CG 164
+#define IMX8MQ_CLK_DRAM_APB_PRE_DIV 165
+#define IMX8MQ_CLK_DRAM_APB_DIV 166
+/* VPU_G1 */
+#define IMX8MQ_CLK_VPU_G1_SRC 167
+#define IMX8MQ_CLK_VPU_G1_CG 168
+#define IMX8MQ_CLK_VPU_G1_PRE_DIV 169
+#define IMX8MQ_CLK_VPU_G1_DIV 170
+/* VPU_G2 */
+#define IMX8MQ_CLK_VPU_G2_SRC 171
+#define IMX8MQ_CLK_VPU_G2_CG 172
+#define IMX8MQ_CLK_VPU_G2_PRE_DIV 173
+#define IMX8MQ_CLK_VPU_G2_DIV 174
+/* DISP_DTRC */
+#define IMX8MQ_CLK_DISP_DTRC_SRC 175
+#define IMX8MQ_CLK_DISP_DTRC_CG 176
+#define IMX8MQ_CLK_DISP_DTRC_PRE_DIV 177
+#define IMX8MQ_CLK_DISP_DTRC_DIV 178
+/* DISP_DC8000 */
+#define IMX8MQ_CLK_DISP_DC8000_SRC 179
+#define IMX8MQ_CLK_DISP_DC8000_CG 180
+#define IMX8MQ_CLK_DISP_DC8000_PRE_DIV 181
+#define IMX8MQ_CLK_DISP_DC8000_DIV 182
+/* PCIE_CTRL */
+#define IMX8MQ_CLK_PCIE1_CTRL_SRC 183
+#define IMX8MQ_CLK_PCIE1_CTRL_CG 184
+#define IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV 185
+#define IMX8MQ_CLK_PCIE1_CTRL_DIV 186
+/* PCIE_PHY */
+#define IMX8MQ_CLK_PCIE1_PHY_SRC 187
+#define IMX8MQ_CLK_PCIE1_PHY_CG 188
+#define IMX8MQ_CLK_PCIE1_PHY_PRE_DIV 189
+#define IMX8MQ_CLK_PCIE1_PHY_DIV 190
+/* PCIE_AUX */
+#define IMX8MQ_CLK_PCIE1_AUX_SRC 191
+#define IMX8MQ_CLK_PCIE1_AUX_CG 192
+#define IMX8MQ_CLK_PCIE1_AUX_PRE_DIV 193
+#define IMX8MQ_CLK_PCIE1_AUX_DIV 194
+/* DC_PIXEL */
+#define IMX8MQ_CLK_DC_PIXEL_SRC 195
+#define IMX8MQ_CLK_DC_PIXEL_CG 196
+#define IMX8MQ_CLK_DC_PIXEL_PRE_DIV 197
+#define IMX8MQ_CLK_DC_PIXEL_DIV 198
+/* LCDIF_PIXEL */
+#define IMX8MQ_CLK_LCDIF_PIXEL_SRC 199
+#define IMX8MQ_CLK_LCDIF_PIXEL_CG 200
+#define IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV 201
+#define IMX8MQ_CLK_LCDIF_PIXEL_DIV 202
+/* SAI1~6 */
+#define IMX8MQ_CLK_SAI1_SRC 203
+#define IMX8MQ_CLK_SAI1_CG 204
+#define IMX8MQ_CLK_SAI1_PRE_DIV 205
+#define IMX8MQ_CLK_SAI1_DIV 206
+
+#define IMX8MQ_CLK_SAI2_SRC 207
+#define IMX8MQ_CLK_SAI2_CG 208
+#define IMX8MQ_CLK_SAI2_PRE_DIV 209
+#define IMX8MQ_CLK_SAI2_DIV 210
+
+#define IMX8MQ_CLK_SAI3_SRC 211
+#define IMX8MQ_CLK_SAI3_CG 212
+#define IMX8MQ_CLK_SAI3_PRE_DIV 213
+#define IMX8MQ_CLK_SAI3_DIV 214
+
+#define IMX8MQ_CLK_SAI4_SRC 215
+#define IMX8MQ_CLK_SAI4_CG 216
+#define IMX8MQ_CLK_SAI4_PRE_DIV 217
+#define IMX8MQ_CLK_SAI4_DIV 218
+
+#define IMX8MQ_CLK_SAI5_SRC 219
+#define IMX8MQ_CLK_SAI5_CG 220
+#define IMX8MQ_CLK_SAI5_PRE_DIV 221
+#define IMX8MQ_CLK_SAI5_DIV 222
+
+#define IMX8MQ_CLK_SAI6_SRC 223
+#define IMX8MQ_CLK_SAI6_CG 224
+#define IMX8MQ_CLK_SAI6_PRE_DIV 225
+#define IMX8MQ_CLK_SAI6_DIV 226
+/* SPDIF1 */
+#define IMX8MQ_CLK_SPDIF1_SRC 227
+#define IMX8MQ_CLK_SPDIF1_CG 228
+#define IMX8MQ_CLK_SPDIF1_PRE_DIV 229
+#define IMX8MQ_CLK_SPDIF1_DIV 230
+/* SPDIF2 */
+#define IMX8MQ_CLK_SPDIF2_SRC 231
+#define IMX8MQ_CLK_SPDIF2_CG 232
+#define IMX8MQ_CLK_SPDIF2_PRE_DIV 233
+#define IMX8MQ_CLK_SPDIF2_DIV 234
+/* ENET_REF */
+#define IMX8MQ_CLK_ENET_REF_SRC 235
+#define IMX8MQ_CLK_ENET_REF_CG 236
+#define IMX8MQ_CLK_ENET_REF_PRE_DIV 237
+#define IMX8MQ_CLK_ENET_REF_DIV 238
+/* ENET_TIMER */
+#define IMX8MQ_CLK_ENET_TIMER_SRC 239
+#define IMX8MQ_CLK_ENET_TIMER_CG 240
+#define IMX8MQ_CLK_ENET_TIMER_PRE_DIV 241
+#define IMX8MQ_CLK_ENET_TIMER_DIV 242
+/* ENET_PHY */
+#define IMX8MQ_CLK_ENET_PHY_REF_SRC 243
+#define IMX8MQ_CLK_ENET_PHY_REF_CG 244
+#define IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV 245
+#define IMX8MQ_CLK_ENET_PHY_REF_DIV 246
+/* NAND */
+#define IMX8MQ_CLK_NAND_SRC 247
+#define IMX8MQ_CLK_NAND_CG 248
+#define IMX8MQ_CLK_NAND_PRE_DIV 249
+#define IMX8MQ_CLK_NAND_DIV 250
+/* QSPI */
+#define IMX8MQ_CLK_QSPI_SRC 251
+#define IMX8MQ_CLK_QSPI_CG 252
+#define IMX8MQ_CLK_QSPI_PRE_DIV 253
+#define IMX8MQ_CLK_QSPI_DIV 254
+/* USDHC1 */
+#define IMX8MQ_CLK_USDHC1_SRC 255
+#define IMX8MQ_CLK_USDHC1_CG 256
+#define IMX8MQ_CLK_USDHC1_PRE_DIV 257
+#define IMX8MQ_CLK_USDHC1_DIV 258
+/* USDHC2 */
+#define IMX8MQ_CLK_USDHC2_SRC 259
+#define IMX8MQ_CLK_USDHC2_CG 260
+#define IMX8MQ_CLK_USDHC2_PRE_DIV 261
+#define IMX8MQ_CLK_USDHC2_DIV 262
+/* I2C1 */
+#define IMX8MQ_CLK_I2C1_SRC 263
+#define IMX8MQ_CLK_I2C1_CG 264
+#define IMX8MQ_CLK_I2C1_PRE_DIV 265
+#define IMX8MQ_CLK_I2C1_DIV 266
+/* I2C2 */
+#define IMX8MQ_CLK_I2C2_SRC 267
+#define IMX8MQ_CLK_I2C2_CG 268
+#define IMX8MQ_CLK_I2C2_PRE_DIV 269
+#define IMX8MQ_CLK_I2C2_DIV 270
+/* I2C3 */
+#define IMX8MQ_CLK_I2C3_SRC 271
+#define IMX8MQ_CLK_I2C3_CG 272
+#define IMX8MQ_CLK_I2C3_PRE_DIV 273
+#define IMX8MQ_CLK_I2C3_DIV 274
+/* I2C4 */
+#define IMX8MQ_CLK_I2C4_SRC 275
+#define IMX8MQ_CLK_I2C4_CG 276
+#define IMX8MQ_CLK_I2C4_PRE_DIV 277
+#define IMX8MQ_CLK_I2C4_DIV 278
+/* UART1 */
+#define IMX8MQ_CLK_UART1_SRC 279
+#define IMX8MQ_CLK_UART1_CG 280
+#define IMX8MQ_CLK_UART1_PRE_DIV 281
+#define IMX8MQ_CLK_UART1_DIV 282
+/* UART2 */
+#define IMX8MQ_CLK_UART2_SRC 283
+#define IMX8MQ_CLK_UART2_CG 284
+#define IMX8MQ_CLK_UART2_PRE_DIV 285
+#define IMX8MQ_CLK_UART2_DIV 286
+/* UART3 */
+#define IMX8MQ_CLK_UART3_SRC 287
+#define IMX8MQ_CLK_UART3_CG 288
+#define IMX8MQ_CLK_UART3_PRE_DIV 289
+#define IMX8MQ_CLK_UART3_DIV 290
+/* UART4 */
+#define IMX8MQ_CLK_UART4_SRC 291
+#define IMX8MQ_CLK_UART4_CG 292
+#define IMX8MQ_CLK_UART4_PRE_DIV 293
+#define IMX8MQ_CLK_UART4_DIV 294
+/* USB_CORE_REF */
+#define IMX8MQ_CLK_USB_CORE_REF_SRC 295
+#define IMX8MQ_CLK_USB_CORE_REF_CG 296
+#define IMX8MQ_CLK_USB_CORE_REF_PRE_DIV 297
+#define IMX8MQ_CLK_USB_CORE_REF_DIV 298
+/* USB_PHY_REF */
+#define IMX8MQ_CLK_USB_PHY_REF_SRC 299
+#define IMX8MQ_CLK_USB_PHY_REF_CG 300
+#define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV 301
+#define IMX8MQ_CLK_USB_PHY_REF_DIV 302
+/* ECSPI1 */
+#define IMX8MQ_CLK_ECSPI1_SRC 303
+#define IMX8MQ_CLK_ECSPI1_CG 304
+#define IMX8MQ_CLK_ECSPI1_PRE_DIV 305
+#define IMX8MQ_CLK_ECSPI1_DIV 306
+/* ECSPI2 */
+#define IMX8MQ_CLK_ECSPI2_SRC 307
+#define IMX8MQ_CLK_ECSPI2_CG 308
+#define IMX8MQ_CLK_ECSPI2_PRE_DIV 309
+#define IMX8MQ_CLK_ECSPI2_DIV 310
+/* PWM1 */
+#define IMX8MQ_CLK_PWM1_SRC 311
+#define IMX8MQ_CLK_PWM1_CG 312
+#define IMX8MQ_CLK_PWM1_PRE_DIV 313
+#define IMX8MQ_CLK_PWM1_DIV 314
+/* PWM2 */
+#define IMX8MQ_CLK_PWM2_SRC 315
+#define IMX8MQ_CLK_PWM2_CG 316
+#define IMX8MQ_CLK_PWM2_PRE_DIV 317
+#define IMX8MQ_CLK_PWM2_DIV 318
+/* PWM3 */
+#define IMX8MQ_CLK_PWM3_SRC 319
+#define IMX8MQ_CLK_PWM3_CG 320
+#define IMX8MQ_CLK_PWM3_PRE_DIV 321
+#define IMX8MQ_CLK_PWM3_DIV 322
+/* PWM4 */
+#define IMX8MQ_CLK_PWM4_SRC 323
+#define IMX8MQ_CLK_PWM4_CG 324
+#define IMX8MQ_CLK_PWM4_PRE_DIV 325
+#define IMX8MQ_CLK_PWM4_DIV 326
+/* GPT1 */
+#define IMX8MQ_CLK_GPT1_SRC 327
+#define IMX8MQ_CLK_GPT1_CG 328
+#define IMX8MQ_CLK_GPT1_PRE_DIV 329
+#define IMX8MQ_CLK_GPT1_DIV 330
+/* WDOG */
+#define IMX8MQ_CLK_WDOG_SRC 331
+#define IMX8MQ_CLK_WDOG_CG 332
+#define IMX8MQ_CLK_WDOG_PRE_DIV 333
+#define IMX8MQ_CLK_WDOG_DIV 334
+/* WRCLK */
+#define IMX8MQ_CLK_WRCLK_SRC 335
+#define IMX8MQ_CLK_WRCLK_CG 336
+#define IMX8MQ_CLK_WRCLK_PRE_DIV 337
+#define IMX8MQ_CLK_WRCLK_DIV 338
+/* DSI_CORE */
+#define IMX8MQ_CLK_DSI_CORE_SRC 339
+#define IMX8MQ_CLK_DSI_CORE_CG 340
+#define IMX8MQ_CLK_DSI_CORE_PRE_DIV 341
+#define IMX8MQ_CLK_DSI_CORE_DIV 342
+/* DSI_PHY */
+#define IMX8MQ_CLK_DSI_PHY_REF_SRC 343
+#define IMX8MQ_CLK_DSI_PHY_REF_CG 344
+#define IMX8MQ_CLK_DSI_PHY_REF_PRE_DIV 345
+#define IMX8MQ_CLK_DSI_PHY_REF_DIV 346
+/* DSI_DBI */
+#define IMX8MQ_CLK_DSI_DBI_SRC 347
+#define IMX8MQ_CLK_DSI_DBI_CG 348
+#define IMX8MQ_CLK_DSI_DBI_PRE_DIV 349
+#define IMX8MQ_CLK_DSI_DBI_DIV 350
+/*DSI_ESC */
+#define IMX8MQ_CLK_DSI_ESC_SRC 351
+#define IMX8MQ_CLK_DSI_ESC_CG 352
+#define IMX8MQ_CLK_DSI_ESC_PRE_DIV 353
+#define IMX8MQ_CLK_DSI_ESC_DIV 354
+/* CSI1_CORE */
+#define IMX8MQ_CLK_CSI1_CORE_SRC 355
+#define IMX8MQ_CLK_CSI1_CORE_CG 356
+#define IMX8MQ_CLK_CSI1_CORE_PRE_DIV 357
+#define IMX8MQ_CLK_CSI1_CORE_DIV 358
+/* CSI1_PHY */
+#define IMX8MQ_CLK_CSI1_PHY_REF_SRC 359
+#define IMX8MQ_CLK_CSI1_PHY_REF_CG 360
+#define IMX8MQ_CLK_CSI1_PHY_REF_PRE_DIV 361
+#define IMX8MQ_CLK_CSI1_PHY_REF_DIV 362
+/* CSI_ESC */
+#define IMX8MQ_CLK_CSI1_ESC_SRC 363
+#define IMX8MQ_CLK_CSI1_ESC_CG 364
+#define IMX8MQ_CLK_CSI1_ESC_PRE_DIV 365
+#define IMX8MQ_CLK_CSI1_ESC_DIV 366
+/* CSI2_CORE */
+#define IMX8MQ_CLK_CSI2_CORE_SRC 367
+#define IMX8MQ_CLK_CSI2_CORE_CG 368
+#define IMX8MQ_CLK_CSI2_CORE_PRE_DIV 369
+#define IMX8MQ_CLK_CSI2_CORE_DIV 370
+/* CSI2_PHY */
+#define IMX8MQ_CLK_CSI2_PHY_REF_SRC 371
+#define IMX8MQ_CLK_CSI2_PHY_REF_CG 372
+#define IMX8MQ_CLK_CSI2_PHY_REF_PRE_DIV 373
+#define IMX8MQ_CLK_CSI2_PHY_REF_DIV 374
+/* CSI2_ESC */
+#define IMX8MQ_CLK_CSI2_ESC_SRC 375
+#define IMX8MQ_CLK_CSI2_ESC_CG 376
+#define IMX8MQ_CLK_CSI2_ESC_PRE_DIV 377
+#define IMX8MQ_CLK_CSI2_ESC_DIV 378
+/* PCIE2_CTRL */
+#define IMX8MQ_CLK_PCIE2_CTRL_SRC 379
+#define IMX8MQ_CLK_PCIE2_CTRL_CG 380
+#define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV 381
+#define IMX8MQ_CLK_PCIE2_CTRL_DIV 382
+/* PCIE2_PHY */
+#define IMX8MQ_CLK_PCIE2_PHY_SRC 383
+#define IMX8MQ_CLK_PCIE2_PHY_CG 384
+#define IMX8MQ_CLK_PCIE2_PHY_PRE_DIV 385
+#define IMX8MQ_CLK_PCIE2_PHY_DIV 386
+/* PCIE2_AUX */
+#define IMX8MQ_CLK_PCIE2_AUX_SRC 387
+#define IMX8MQ_CLK_PCIE2_AUX_CG 388
+#define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV 389
+#define IMX8MQ_CLK_PCIE2_AUX_DIV 390
+/* ECSPI3 */
+#define IMX8MQ_CLK_ECSPI3_SRC 391
+#define IMX8MQ_CLK_ECSPI3_CG 392
+#define IMX8MQ_CLK_ECSPI3_PRE_DIV 393
+#define IMX8MQ_CLK_ECSPI3_DIV 394
+
+/* CCGR clocks */
+#define IMX8MQ_CLK_A53_ROOT 395
+#define IMX8MQ_CLK_DRAM_ROOT 396
+#define IMX8MQ_CLK_ECSPI1_ROOT 397
+#define IMX8MQ_CLK_ECSPI2_ROOT 398
+#define IMX8MQ_CLK_ECSPI3_ROOT 399
+#define IMX8MQ_CLK_ENET1_ROOT 400
+#define IMX8MQ_CLK_GPT1_ROOT 401
+#define IMX8MQ_CLK_I2C1_ROOT 402
+#define IMX8MQ_CLK_I2C2_ROOT 403
+#define IMX8MQ_CLK_I2C3_ROOT 404
+#define IMX8MQ_CLK_I2C4_ROOT 405
+#define IMX8MQ_CLK_M4_ROOT 406
+#define IMX8MQ_CLK_PCIE1_ROOT 407
+#define IMX8MQ_CLK_PCIE2_ROOT 408
+#define IMX8MQ_CLK_PWM1_ROOT 409
+#define IMX8MQ_CLK_PWM2_ROOT 410
+#define IMX8MQ_CLK_PWM3_ROOT 411
+#define IMX8MQ_CLK_PWM4_ROOT 412
+#define IMX8MQ_CLK_QSPI_ROOT 413
+#define IMX8MQ_CLK_SAI1_ROOT 414
+#define IMX8MQ_CLK_SAI2_ROOT 415
+#define IMX8MQ_CLK_SAI3_ROOT 416
+#define IMX8MQ_CLK_SAI4_ROOT 417
+#define IMX8MQ_CLK_SAI5_ROOT 418
+#define IMX8MQ_CLK_SAI6_ROOT 419
+#define IMX8MQ_CLK_UART1_ROOT 420
+#define IMX8MQ_CLK_UART2_ROOT 421
+#define IMX8MQ_CLK_UART3_ROOT 422
+#define IMX8MQ_CLK_UART4_ROOT 423
+#define IMX8MQ_CLK_USB1_CTRL_ROOT 424
+#define IMX8MQ_CLK_USB2_CTRL_ROOT 425
+#define IMX8MQ_CLK_USB1_PHY_ROOT 426
+#define IMX8MQ_CLK_USB2_PHY_ROOT 427
+#define IMX8MQ_CLK_USDHC1_ROOT 428
+#define IMX8MQ_CLK_USDHC2_ROOT 429
+#define IMX8MQ_CLK_WDOG1_ROOT 430
+#define IMX8MQ_CLK_WDOG2_ROOT 431
+#define IMX8MQ_CLK_WDOG3_ROOT 432
+#define IMX8MQ_CLK_GPU_ROOT 433
+#define IMX8MQ_CLK_HEVC_ROOT 434
+#define IMX8MQ_CLK_AVC_ROOT 435
+#define IMX8MQ_CLK_VP9_ROOT 436
+#define IMX8MQ_CLK_HEVC_INTER_ROOT 437
+#define IMX8MQ_CLK_DISP_ROOT 438
+#define IMX8MQ_CLK_HDMI_ROOT 439
+#define IMX8MQ_CLK_HDMI_PHY_ROOT 440
+#define IMX8MQ_CLK_VPU_DEC_ROOT 441
+#define IMX8MQ_CLK_CSI1_ROOT 442
+#define IMX8MQ_CLK_CSI2_ROOT 443
+#define IMX8MQ_CLK_RAWNAND_ROOT 444
+#define IMX8MQ_CLK_SDMA1_ROOT 445
+#define IMX8MQ_CLK_SDMA2_ROOT 446
+#define IMX8MQ_CLK_VPU_G1_ROOT 447
+#define IMX8MQ_CLK_VPU_G2_ROOT 448
+
+/* SCCG PLL GATE */
+#define IMX8MQ_SYS1_PLL_OUT 449
+#define IMX8MQ_SYS2_PLL_OUT 450
+#define IMX8MQ_SYS3_PLL_OUT 451
+#define IMX8MQ_DRAM_PLL_OUT 452
+
+#define IMX8MQ_GPT_3M_CLK 453
+
+#define IMX8MQ_CLK_IPG_ROOT 454
+#define IMX8MQ_CLK_IPG_AUDIO_ROOT 455
+#define IMX8MQ_CLK_SAI1_IPG 456
+#define IMX8MQ_CLK_SAI2_IPG 457
+#define IMX8MQ_CLK_SAI3_IPG 458
+#define IMX8MQ_CLK_SAI4_IPG 459
+#define IMX8MQ_CLK_SAI5_IPG 460
+#define IMX8MQ_CLK_SAI6_IPG 461
+
+/* DSI AHB/IPG clocks */
+/* rxesc clock */
+#define IMX8MQ_CLK_DSI_AHB_SRC 462
+#define IMX8MQ_CLK_DSI_AHB_CG 463
+#define IMX8MQ_CLK_DSI_AHB_PRE_DIV 464
+#define IMX8MQ_CLK_DSI_AHB_DIV 465
+/* txesc clock */
+#define IMX8MQ_CLK_DSI_IPG_DIV 466
+
+/* VIDEO2 PLL */
+#define IMX8MQ_VIDEO2_PLL1_REF_SEL 467
+#define IMX8MQ_VIDEO2_PLL1_REF_DIV 468
+#define IMX8MQ_VIDEO2_PLL1 469
+#define IMX8MQ_VIDEO2_PLL1_OUT 470
+#define IMX8MQ_VIDEO2_PLL1_OUT_DIV 471
+#define IMX8MQ_VIDEO2_PLL2 472
+#define IMX8MQ_VIDEO2_PLL2_DIV 473
+#define IMX8MQ_VIDEO2_PLL2_OUT 474
+#define IMX8MQ_CLK_TMU_ROOT 475
+
+/* Display root clocks */
+#define IMX8MQ_CLK_DISP_AXI_ROOT 476
+#define IMX8MQ_CLK_DISP_APB_ROOT 477
+#define IMX8MQ_CLK_DISP_RTRM_ROOT 478
+
+#define IMX8MQ_CLK_OCOTP_ROOT 479
+
+#define IMX8MQ_CLK_DRAM_ALT_ROOT 480
+#define IMX8MQ_CLK_DRAM_CORE 481
+
+#define IMX8MQ_CLK_MU_ROOT 482
+#define IMX8MQ_VIDEO2_PLL_OUT 483
+
+#define IMX8MQ_CLK_CLKO2_SRC 484
+#define IMX8MQ_CLK_CLKO2_CG 485
+#define IMX8MQ_CLK_CLKO2_PRE_DIV 486
+#define IMX8MQ_CLK_CLKO2_DIV 487
+
+#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 488
+
+#define IMX8MQ_CLK_END 489
+#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 04/48] aarch64: Add i.MX8 debug UART support
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (2 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 03/48] ARM: Add i.MX8 support Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 05/48] Include our own include/dt-bindings Andrey Smirnov
` (43 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
[andrew.smirnov@gmail.com: Added imx8_uart_setup_ll()]
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
fixup! aarch64: Add i.MX8 debug UART support
---
arch/arm/mach-imx/include/mach/debug_ll.h | 11 +++++++++++
common/Kconfig | 8 ++++++++
2 files changed, 19 insertions(+)
diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h
index d54d601db..1550e059e 100644
--- a/arch/arm/mach-imx/include/mach/debug_ll.h
+++ b/arch/arm/mach-imx/include/mach/debug_ll.h
@@ -15,6 +15,7 @@
#include <mach/imx53-regs.h>
#include <mach/imx6-regs.h>
#include <mach/imx7-regs.h>
+#include <mach/imx8mq-regs.h>
#include <mach/vf610-regs.h>
#include <serial/imx-uart.h>
@@ -47,6 +48,8 @@
#define IMX_DEBUG_SOC MX6
#elif defined CONFIG_DEBUG_IMX7D_UART
#define IMX_DEBUG_SOC MX7
+#elif defined CONFIG_DEBUG_IMX8MQ_UART
+#define IMX_DEBUG_SOC MX8MQ
#elif defined CONFIG_DEBUG_VF610_UART
#define IMX_DEBUG_SOC VF610
#else
@@ -95,6 +98,13 @@ static inline void vf610_uart_setup_ll(void)
lpuart_setup(base, 66000000);
}
+static inline void imx8_uart_setup_ll(void)
+{
+ void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC,
+ CONFIG_DEBUG_IMX_UART_PORT));
+ imx8mq_uart_setup(base);
+}
+
static inline void PUTC_LL(int c)
{
void __iomem *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC,
@@ -117,6 +127,7 @@ static inline void imx53_uart_setup_ll(void) {}
static inline void imx6_uart_setup_ll(void) {}
static inline void imx7_uart_setup_ll(void) {}
static inline void vf610_uart_setup_ll(void) {}
+static inline void imx8_uart_setup_ll(void) {}
#endif /* CONFIG_DEBUG_LL */
diff --git a/common/Kconfig b/common/Kconfig
index b7000c4d7..75aea460a 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -1099,6 +1099,13 @@ config DEBUG_IMX7D_UART
Say Y here if you want barebox low-level debugging support
on i.MX7D.
+config DEBUG_IMX8MQ_UART
+ bool "i.MX8MQ Debug UART"
+ depends on ARCH_IMX8MQ
+ help
+ Say Y here if you want barebox low-level debugging support
+ on i.MX8MQ.
+
config DEBUG_VF610_UART
bool "VF610 Debug UART"
depends on ARCH_VF610
@@ -1163,6 +1170,7 @@ config DEBUG_IMX_UART_PORT
DEBUG_IMX6Q_UART || \
DEBUG_IMX6SL_UART || \
DEBUG_IMX7D_UART || \
+ DEBUG_IMX8MQ_UART || \
DEBUG_VF610_UART
default 1
depends on ARCH_IMX
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 05/48] Include our own include/dt-bindings
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (3 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 04/48] aarch64: Add i.MX8 debug UART support Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 06/48] mci: imx-esdhc: use dma mapping functions Andrey Smirnov
` (42 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Allow to use dt-bindings files that are not yet upstreamed. They can
be put into include/dt-bindings.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/mips/dts/include/dt-bindings | 1 -
scripts/Makefile.lib | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
delete mode 120000 arch/mips/dts/include/dt-bindings
diff --git a/arch/mips/dts/include/dt-bindings b/arch/mips/dts/include/dt-bindings
deleted file mode 120000
index 0cecb3d08..000000000
--- a/arch/mips/dts/include/dt-bindings
+++ /dev/null
@@ -1 +0,0 @@
-../../../../include/dt-bindings
\ No newline at end of file
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 272b5981e..3024b068e 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -154,6 +154,7 @@ ld_flags = $(LDFLAGS) $(EXTRA_LDFLAGS)
dtc_cpp_flags = -Wp,-MD,$(depfile).pre -nostdinc \
-I$(srctree)/arch/$(SRCARCH)/dts/include \
-I$(srctree)/dts/include \
+ -I$(srctree)/include \
-I$(srctree)/dts/src/ \
-undef -D__DTS__
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 06/48] mci: imx-esdhc: use dma mapping functions
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (4 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 05/48] Include our own include/dt-bindings Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 07/48] net: fec_imx: remove unnecessary DMA sync ops Andrey Smirnov
` (41 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Rather than relying on the fact that addresses can be just casted
into DMA addresses use proper DMA mapping functions.
This fixes compiler warnings when we do DMA on this 32bit only device
on aarch64 SoCs.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/mci/imx-esdhc.c | 53 ++++++++++++++++++++---------------------
1 file changed, 26 insertions(+), 27 deletions(-)
diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index b91f94b99..8929901d4 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -211,18 +211,14 @@ esdhc_pio_read_write(struct mci_host *mci, struct mci_data *data)
return 0;
}
-static int esdhc_setup_data(struct mci_host *mci, struct mci_data *data)
+static int esdhc_setup_data(struct mci_host *mci, struct mci_data *data,
+ dma_addr_t dma)
{
struct fsl_esdhc_host *host = to_fsl_esdhc(mci);
void __iomem *regs = host->regs;
u32 wml_value;
- if (IS_ENABLED(CONFIG_MCI_IMX_ESDHC_PIO)) {
- if (!(data->flags & MMC_DATA_READ))
- esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)data->src);
- else
- esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)data->dest);
- } else {
+ if (!IS_ENABLED(CONFIG_MCI_IMX_ESDHC_PIO)) {
wml_value = data->blocksize/4;
if (data->flags & MMC_DATA_READ) {
@@ -230,15 +226,14 @@ static int esdhc_setup_data(struct mci_host *mci, struct mci_data *data)
wml_value = 0x10;
esdhc_clrsetbits32(regs + IMX_SDHCI_WML, WML_RD_WML_MASK, wml_value);
- esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)data->dest);
} else {
if (wml_value > 0x80)
wml_value = 0x80;
esdhc_clrsetbits32(regs + IMX_SDHCI_WML, WML_WR_WML_MASK,
wml_value << 16);
- esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)data->src);
}
+ esdhc_write32(regs + SDHCI_DMA_ADDRESS, dma);
}
esdhc_write32(regs + SDHCI_BLOCK_SIZE__BLOCK_COUNT, data->blocks << 16 | data->blocksize);
@@ -250,7 +245,6 @@ static int esdhc_do_data(struct mci_host *mci, struct mci_data *data)
{
struct fsl_esdhc_host *host = to_fsl_esdhc(mci);
void __iomem *regs = host->regs;
- unsigned int num_bytes = data->blocks * data->blocksize;
u32 irqstat;
if (IS_ENABLED(CONFIG_MCI_IMX_ESDHC_PIO))
@@ -267,13 +261,6 @@ static int esdhc_do_data(struct mci_host *mci, struct mci_data *data)
} while (!(irqstat & IRQSTAT_TC) &&
(esdhc_read32(regs + SDHCI_PRESENT_STATE) & PRSSTAT_DLA));
- if (data->flags & MMC_DATA_WRITE)
- dma_sync_single_for_cpu((unsigned long)data->src,
- num_bytes, DMA_TO_DEVICE);
- else
- dma_sync_single_for_cpu((unsigned long)data->dest,
- num_bytes, DMA_FROM_DEVICE);
-
return 0;
}
@@ -290,6 +277,9 @@ esdhc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
void __iomem *regs = host->regs;
unsigned int num_bytes = 0;
int ret;
+ void *ptr;
+ enum dma_data_direction dir = 0;
+ dma_addr_t dma = 0;
esdhc_write32(regs + SDHCI_INT_STATUS, -1);
@@ -300,19 +290,25 @@ esdhc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
if (data) {
int err;
- err = esdhc_setup_data(mci, data);
- if(err)
- return err;
+ if (!IS_ENABLED(CONFIG_MCI_IMX_ESDHC_PIO)) {
+ num_bytes = data->blocks * data->blocksize;
- num_bytes = data->blocks * data->blocksize;
+ if (data->flags & MMC_DATA_WRITE) {
+ ptr = (void *)data->src;
+ dir = DMA_TO_DEVICE;
+ } else {
+ ptr = data->dest;
+ dir = DMA_FROM_DEVICE;
+ }
- if (data->flags & MMC_DATA_WRITE)
- dma_sync_single_for_device((unsigned long)data->src,
- num_bytes, DMA_TO_DEVICE);
- else
- dma_sync_single_for_device((unsigned long)data->dest,
- num_bytes, DMA_FROM_DEVICE);
+ dma = dma_map_single(host->dev, ptr, num_bytes, dir);
+ if (dma_mapping_error(host->dev, dma))
+ return -EIO;
+ }
+ err = esdhc_setup_data(mci, data, dma);
+ if(err)
+ return err;
}
/* Figure out the transfer arguments */
@@ -383,6 +379,9 @@ esdhc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
ret = esdhc_do_data(mci, data);
if (ret)
return ret;
+
+ if (!IS_ENABLED(CONFIG_MCI_IMX_ESDHC_PIO))
+ dma_unmap_single(host->dev, dma, num_bytes, dir);
}
esdhc_write32(regs + SDHCI_INT_STATUS, -1);
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 07/48] net: fec_imx: remove unnecessary DMA sync ops
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (5 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 06/48] mci: imx-esdhc: use dma mapping functions Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 08/48] net: fec_imx: Use dma mapping functions Andrey Smirnov
` (40 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
The fec receive buffers are coherently mapped, no need to dma_sync on
them.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/net/fec_imx.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c
index d506fd64f..33599dd82 100644
--- a/drivers/net/fec_imx.c
+++ b/drivers/net/fec_imx.c
@@ -580,11 +580,7 @@ static int fec_recv(struct eth_device *dev)
*/
frame = phys_to_virt(readl(&rbd->data_pointer));
frame_length = readw(&rbd->data_length) - 4;
- dma_sync_single_for_cpu((unsigned long)frame->data,
- frame_length, DMA_FROM_DEVICE);
net_receive(dev, frame->data, frame_length);
- dma_sync_single_for_device((unsigned long)frame->data,
- frame_length, DMA_FROM_DEVICE);
len = frame_length;
} else {
if (bd_status & FEC_RBD_ERR) {
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 08/48] net: fec_imx: Use dma mapping functions
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (6 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 07/48] net: fec_imx: remove unnecessary DMA sync ops Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 09/48] net: fec_imx: Make use of IS_ALIGNED Andrey Smirnov
` (39 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Rather than doing DMA on the input buffer address get a proper DMA
address from the mapping functions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/net/fec_imx.c | 15 +++++++++------
drivers/net/fec_imx.h | 1 +
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c
index 33599dd82..0ca594082 100644
--- a/drivers/net/fec_imx.c
+++ b/drivers/net/fec_imx.c
@@ -453,6 +453,7 @@ static int fec_send(struct eth_device *dev, void *eth_data, int data_length)
{
unsigned int status;
uint64_t tmo;
+ dma_addr_t dma;
/*
* This routine transmits one frame. This routine only accepts
@@ -466,7 +467,7 @@ static int fec_send(struct eth_device *dev, void *eth_data, int data_length)
return -1;
}
- if ((uint32_t)eth_data & (DB_DATA_ALIGNMENT-1))
+ if ((unsigned long)eth_data & (DB_DATA_ALIGNMENT - 1))
dev_warn(&dev->dev, "Transmit data not aligned: %p!\n", eth_data);
/*
@@ -479,10 +480,12 @@ static int fec_send(struct eth_device *dev, void *eth_data, int data_length)
writew(data_length, &fec->tbd_base[fec->tbd_index].data_length);
- writel((uint32_t)(eth_data), &fec->tbd_base[fec->tbd_index].data_pointer);
+ dma = dma_map_single(fec->dev, eth_data, data_length, DMA_TO_DEVICE);
+ if (dma_mapping_error(fec->dev, dma))
+ return -EIO;
+
+ writel((uint32_t)(dma), &fec->tbd_base[fec->tbd_index].data_pointer);
- dma_sync_single_for_device((unsigned long)eth_data, data_length,
- DMA_TO_DEVICE);
/*
* update BD's status now
* This block:
@@ -505,8 +508,7 @@ static int fec_send(struct eth_device *dev, void *eth_data, int data_length)
break;
}
}
- dma_sync_single_for_cpu((unsigned long)eth_data, data_length,
- DMA_TO_DEVICE);
+ dma_unmap_single(fec->dev, dma, data_length, DMA_TO_DEVICE);
/* for next transmission use the other buffer */
if (fec->tbd_index)
@@ -748,6 +750,7 @@ static int fec_probe(struct device_d *dev)
fec = xzalloc(sizeof(*fec));
fec->type = type;
+ fec->dev = dev;
edev = &fec->edev;
dev->priv = fec;
edev->priv = fec;
diff --git a/drivers/net/fec_imx.h b/drivers/net/fec_imx.h
index 561de0890..e3f60dd66 100644
--- a/drivers/net/fec_imx.h
+++ b/drivers/net/fec_imx.h
@@ -149,6 +149,7 @@ enum fec_opt_clock {
*/
struct fec_priv {
struct eth_device edev;
+ struct device_d *dev;
void __iomem *regs;
struct buffer_descriptor __iomem *rbd_base; /* RBD ring */
int rbd_index; /* next receive BD to read */
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 09/48] net: fec_imx: Make use of IS_ALIGNED
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (7 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 08/48] net: fec_imx: Use dma mapping functions Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 10/48] clock: Add i.MX8MQ clock driver Andrey Smirnov
` (38 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/net/fec_imx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c
index 0ca594082..98711baa7 100644
--- a/drivers/net/fec_imx.c
+++ b/drivers/net/fec_imx.c
@@ -467,7 +467,7 @@ static int fec_send(struct eth_device *dev, void *eth_data, int data_length)
return -1;
}
- if ((unsigned long)eth_data & (DB_DATA_ALIGNMENT - 1))
+ if (!IS_ALIGNED((unsigned long)eth_data, DB_DATA_ALIGNMENT))
dev_warn(&dev->dev, "Transmit data not aligned: %p!\n", eth_data);
/*
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 10/48] clock: Add i.MX8MQ clock driver
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (8 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 09/48] net: fec_imx: Make use of IS_ALIGNED Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 11/48] serial: i.MX: Add i.MX8 support Andrey Smirnov
` (37 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
This is based on Lucas' patch sent as "[PATCH v2 4/4] clk: imx: add
clock driver for i.MX8MQ CCM" to the mailing list.
It will likely need some rework before it is finally merged, so apply
the reworks here before merging into barebox.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/clk/imx/Makefile | 3 +
drivers/clk/imx/clk-frac-pll.c | 226 +++++++++++++
drivers/clk/imx/clk-imx8mq.c | 580 +++++++++++++++++++++++++++++++++
drivers/clk/imx/clk-sccg-pll.c | 242 ++++++++++++++
drivers/clk/imx/clk.h | 27 ++
5 files changed, 1078 insertions(+)
create mode 100644 drivers/clk/imx/clk-frac-pll.c
create mode 100644 drivers/clk/imx/clk-imx8mq.c
create mode 100644 drivers/clk/imx/clk-sccg-pll.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index b864b4f32..8f441a97e 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -6,6 +6,8 @@ obj-$(CONFIG_COMMON_CLK) += \
clk-gate2.o \
clk-gate-exclusive.o \
clk-cpu.o \
+ clk-frac-pll.o \
+ clk-sccg-pll.o \
clk.o
obj-$(CONFIG_ARCH_IMX1) += clk-imx1.o
@@ -22,4 +24,5 @@ obj-$(CONFIG_ARCH_IMX6SX) += clk-imx6sx.o
obj-$(CONFIG_ARCH_IMX6SL) += clk-imx6sl.o
obj-$(CONFIG_ARCH_IMX6UL) += clk-imx6ul.o
obj-$(CONFIG_ARCH_IMX7) += clk-imx7.o
+obj-$(CONFIG_ARCH_IMX8MQ) += clk-imx8mq.o
obj-$(CONFIG_ARCH_VF610) += clk-vf610.o
diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c
new file mode 100644
index 000000000..def870e24
--- /dev/null
+++ b/drivers/clk/imx/clk-frac-pll.c
@@ -0,0 +1,226 @@
+/*
+ * Copyright 2017 NXP.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <common.h>
+#include <io.h>
+#include <malloc.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <asm-generic/div64.h>
+
+#include "clk.h"
+
+#define PLL_CFG0 0x0
+#define PLL_CFG1 0x4
+
+#define PLL_LOCK_STATUS (0x1 << 31)
+#define PLL_CLKE 21
+#define PLL_PD 19
+#define PLL_BYPASS 14
+#define PLL_NEWDIV_VAL (1 << 12)
+#define PLL_NEWDIV_ACK (1 << 11)
+#define PLL_FRAC_DIV_MASK 0xffffff
+#define PLL_INT_DIV_MASK 0x7f
+#define PLL_FRAC_DENOM 0x1000000
+
+struct clk_frac_pll {
+ struct clk clk;
+ void __iomem *base;
+ const char *parent;
+};
+
+#define to_clk_frac_pll(_clk) container_of(_clk, struct clk_frac_pll, clk)
+
+static int clk_wait_lock(struct clk_frac_pll *pll)
+{
+ unsigned long timeout = 100000;
+
+ /* Wait for PLL to lock */
+ while (timeout--) {
+ if (readl(pll->base) & PLL_LOCK_STATUS)
+ break;
+ }
+
+ return readl(pll->base) & PLL_LOCK_STATUS ? 0 : -ETIMEDOUT;
+}
+
+static int clk_wait_ack(struct clk_frac_pll *pll)
+{
+ unsigned long timeout = 100000;
+
+ /* return directly if the pll is in powerdown or in bypass */
+ if (readl(pll->base) & ((1 << PLL_PD) | (1 << PLL_BYPASS)))
+ return 0;
+
+ /* Wait for the pll's divfi and divff to be reloaded */
+ while (timeout--) {
+ if (readl(pll->base) & PLL_NEWDIV_ACK)
+ break;
+ }
+
+ return readl(pll->base) & PLL_NEWDIV_ACK ? 0 : ETIMEDOUT;
+}
+
+static int clk_pll_enable(struct clk *clk)
+{
+ struct clk_frac_pll *pll = to_clk_frac_pll(clk);
+ u32 val;
+
+ val = readl(pll->base + PLL_CFG0);
+ val &= ~(1 << PLL_PD);
+ writel(val, pll->base + PLL_CFG0);
+
+ return clk_wait_lock(pll);
+}
+
+static void clk_pll_disable(struct clk *clk)
+{
+ struct clk_frac_pll *pll = to_clk_frac_pll(clk);
+ u32 val;
+
+ val = readl(pll->base + PLL_CFG0);
+ val |= (1 << PLL_PD);
+ writel(val, pll->base + PLL_CFG0);
+}
+
+static int clk_pll_is_enabled(struct clk *clk)
+{
+ struct clk_frac_pll *pll = to_clk_frac_pll(clk);
+ u32 val;
+
+ val = readl(pll->base + PLL_CFG0);
+ return (val & (1 << PLL_PD)) ? 0 : 1;
+}
+
+static unsigned long clk_pll_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_frac_pll *pll = to_clk_frac_pll(clk);
+ u32 val, divff, divfi, divq;
+ u64 temp64;
+
+ val = readl(pll->base + PLL_CFG0);
+ divq = ((val & 0x1f) + 1) * 2;
+ val = readl(pll->base + PLL_CFG1);
+ divff = (val >> 7) & PLL_FRAC_DIV_MASK;
+ divfi = (val & PLL_INT_DIV_MASK);
+
+ temp64 = (u64)parent_rate * 8;
+ temp64 *= divff;
+ do_div(temp64, PLL_FRAC_DENOM);
+ temp64 /= divq;
+
+ return parent_rate * 8 * (divfi + 1) / divq + (unsigned long)temp64;
+}
+
+static long clk_pll_round_rate(struct clk *clk, unsigned long rate,
+ unsigned long *prate)
+{
+ u32 divff, divfi;
+ u64 temp64;
+ unsigned long parent_rate = *prate;
+
+ parent_rate *= 8;
+ rate *= 2;
+ divfi = rate / parent_rate;
+ temp64 = (u64)(rate - divfi * parent_rate);
+ temp64 *= PLL_FRAC_DENOM;
+ do_div(temp64, parent_rate);
+ divff = temp64;
+
+ temp64 = (u64)parent_rate;
+ temp64 *= divff;
+ do_div(temp64, PLL_FRAC_DENOM);
+
+ return (parent_rate * divfi + (unsigned long)temp64) / 2;
+}
+
+/*
+ * To simplify the clock calculation, we can keep the 'PLL_OUTPUT_VAL' at zero
+ * (means the PLL output will be divided by 2). So the PLL output can use
+ * the below formula:
+ * pllout = parent_rate * 8 / 2 * DIVF_VAL;
+ * where DIVF_VAL = 1 + DIVFI + DIVFF / 2^24.
+ */
+static int clk_pll_set_rate(struct clk *clk, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_frac_pll *pll = to_clk_frac_pll(clk);
+ u32 val, divfi, divff;
+ u64 temp64;
+ int ret;
+
+ parent_rate *= 8;
+ rate *= 2;
+ divfi = rate / parent_rate;
+ temp64 = (u64) (rate - divfi * parent_rate);
+ temp64 *= PLL_FRAC_DENOM;
+ do_div(temp64, parent_rate);
+ divff = temp64;
+
+ val = readl(pll->base + PLL_CFG1);
+ val &= ~((PLL_FRAC_DIV_MASK << 7) | (PLL_INT_DIV_MASK));
+ val |= ((divff << 7) | (divfi - 1));
+ writel(val, pll->base + PLL_CFG1);
+
+ val = readl(pll->base + PLL_CFG0);
+ val &= ~0x1f;
+ writel(val, pll->base + PLL_CFG0);
+
+ /* Set the NEV_DIV_VAL to reload the DIVFI and DIVFF */
+ val = readl(pll->base + PLL_CFG0);
+ val |= PLL_NEWDIV_VAL;
+ writel(val, pll->base + PLL_CFG0);
+
+ ret = clk_wait_ack(pll);
+
+ /* clear the NEV_DIV_VAL */
+ val = readl(pll->base + PLL_CFG0);
+ val &= ~PLL_NEWDIV_VAL;
+ writel(val, pll->base + PLL_CFG0);
+
+ return ret;
+}
+
+static const struct clk_ops clk_frac_pll_ops = {
+ .enable = clk_pll_enable,
+ .disable = clk_pll_disable,
+ .is_enabled = clk_pll_is_enabled,
+ .recalc_rate = clk_pll_recalc_rate,
+ .round_rate = clk_pll_round_rate,
+ .set_rate = clk_pll_set_rate,
+};
+
+struct clk *imx_clk_frac_pll(const char *name, const char *parent,
+ void __iomem *base)
+{
+ struct clk_frac_pll *pll;
+ int ret;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pll->base = base;
+ pll->parent = parent;
+ pll->clk.ops = &clk_frac_pll_ops;
+ pll->clk.name = name;
+ pll->clk.parent_names = &pll->parent;
+ pll->clk.num_parents = 1;
+
+ ret = clk_register(&pll->clk);
+ if (ret) {
+ free(pll);
+ return ERR_PTR(ret);
+ }
+
+ return &pll->clk;
+}
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
new file mode 100644
index 000000000..92d49d44e
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -0,0 +1,580 @@
+/*
+ * Copyright 2017 NXP.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <of.h>
+#include <of_address.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <mach/revision.h>
+#include <dt-bindings/clock/imx8mq-clock.h>
+
+#include "clk.h"
+
+static struct clk *clks[IMX8MQ_CLK_END];
+
+static const char *pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", };
+static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
+static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
+static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
+static const char *audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
+static const char *audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
+static const char *video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
+
+static const char *sys1_pll1_out_sels[] = {"sys1_pll1", "sys1_pll1_ref_sel", };
+static const char *sys2_pll1_out_sels[] = {"sys2_pll1", "sys1_pll1_ref_sel", };
+static const char *sys3_pll1_out_sels[] = {"sys3_pll1", "sys3_pll1_ref_sel", };
+static const char *dram_pll1_out_sels[] = {"dram_pll1", "dram_pll1_ref_sel", };
+static const char *video2_pll1_out_sels[] = {"video2_pll1", "video2_pll1_ref_sel", };
+
+static const char *sys1_pll2_out_sels[] = {"sys1_pll2_div", "sys1_pll1_ref_sel", };
+static const char *sys2_pll2_out_sels[] = {"sys2_pll2_div", "sys2_pll1_ref_sel", };
+static const char *sys3_pll2_out_sels[] = {"sys3_pll2_div", "sys2_pll1_ref_sel", };
+static const char *dram_pll2_out_sels[] = {"dram_pll2_div", "dram_pll1_ref_sel", };
+static const char *video2_pll2_out_sels[] = {"video2_pll2_div", "video2_pll1_ref_sel", };
+
+/* CCM ROOT */
+static const char *imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
+ "sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll2_out", };
+
+static const char *imx8mq_main_axi_sels[] = {"osc_25m", "sys2_pll_333m", "sys1_pll_800m", "sys2_pll_250m",
+ "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "sys1_pll_100m",};
+
+static const char *imx8mq_enet_axi_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_250m",
+ "sys2_pll_200m", "audio_pll1_out", "video_pll1_out", "sys3_pll2_out", };
+
+static const char *imx8mq_nand_usdhc_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_200m",
+ "sys1_pll_133m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll1_out", };
+
+static const char *imx8mq_usb_bus_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_100m",
+ "sys2_pll_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
+
+static const char *imx8mq_noc_sels[] = {"osc_25m", "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_500m",
+ "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+
+static const char *imx8mq_noc_apb_sels[] = {"osc_25m", "sys1_pll_400m", "sys3_pll2_out", "sys2_pll_333m", "sys2_pll_200m",
+ "sys1_pll_800m", "audio_pll1_out", "video_pll1_out", };
+
+static const char *imx8mq_ahb_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_800m", "sys1_pll_400m",
+ "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", };
+
+static const char *imx8mq_dram_alt_sels[] = {"osc_25m", "sys1_pll_800m", "sys1_pll_100m", "sys2_pll_500m",
+ "sys2_pll_250m", "sys1_pll_400m", "audio_pll1_out", "sys1_pll_266m", };
+
+static const char *imx8mq_dram_apb_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
+ "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
+
+static const char *imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
+ "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll2_out", };
+
+static const char *imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4", };
+
+static const char *imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll2_out",
+ "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
+
+static const char *imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", };
+
+static const char *imx8mq_lcdif_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", };
+
+static const char *imx8mq_enet_ref_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_500m", "sys2_pll_100m",
+ "sys1_pll_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
+
+static const char *imx8mq_enet_timer_sels[] = {"osc_25m", "sys2_pll_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4", "video_pll1_out", };
+
+static const char *imx8mq_enet_phy_sels[] = {"osc_25m", "sys2_pll_50m", "sys2_pll_125m", "sys2_pll_500m",
+ "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+
+static const char *imx8mq_nand_sels[] = {"osc_25m", "sys2_pll_500m", "audio_pll1_out", "sys1_pll_400m",
+ "audio_pll2_out", "sys3_pll2_out", "sys2_pll_250m", "video_pll1_out", };
+
+static const char *imx8mq_qspi_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
+ "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", };
+
+static const char *imx8mq_usdhc1_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
+ "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", };
+
+static const char *imx8mq_usdhc2_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
+ "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", };
+
+static const char *imx8mq_i2c1_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
+ "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
+
+static const char *imx8mq_i2c2_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
+ "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
+
+static const char *imx8mq_i2c3_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
+ "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
+
+static const char *imx8mq_i2c4_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
+ "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
+
+static const char *imx8mq_uart1_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
+ "sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
+
+static const char *imx8mq_uart2_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
+ "sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mq_uart3_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
+ "sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
+
+static const char *imx8mq_uart4_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
+ "sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mq_usb_core_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m",
+ "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mq_usb_phy_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m",
+ "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mq_ecspi1_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
+ "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
+
+static const char *imx8mq_ecspi2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
+ "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
+
+static const char *imx8mq_pwm1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
+ "sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
+
+static const char *imx8mq_pwm2_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
+ "sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
+
+static const char *imx8mq_pwm3_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
+ "sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
+
+static const char *imx8mq_pwm4_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
+ "sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
+
+static const char *imx8mq_gpt1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_400m", "sys1_pll_40m",
+ "sys1_pll_80m", "audio_pll1_out", "clk_ext1", };
+
+static const char *imx8mq_wdog_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_160m", "vpu_pll_out",
+ "sys2_pll_125m", "sys3_pll2_out", "sys1_pll_80m", "sys2_pll_166m", };
+
+static const char *imx8mq_wrclk_sels[] = {"osc_25m", "sys1_pll_40m", "vpu_pll_out", "sys3_pll2_out", "sys2_pll_200m",
+ "sys1_pll_266m", "sys2_pll_500m", "sys1_pll_100m", };
+
+static const char *imx8mq_pcie2_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
+ "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll2_out", };
+
+static const char *imx8mq_pcie2_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1",
+ "clk_ext2", "clk_ext3", "clk_ext4", "sys1_pll_400m", };
+
+static const char *imx8mq_pcie2_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll2_out",
+ "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
+
+static const char *imx8mq_ecspi3_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
+ "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
+static const char *imx8mq_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
+
+static const char *imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m", "audio_pll1_out",
+ "video_pll1_out", "ckil", };
+
+static struct clk_onecell_data clk_data;
+
+static void __init imx8mq_clocks_init(struct device_node *ccm_node)
+{
+ struct device_node *np;
+ void __iomem *base;
+ int i;
+
+ clks[IMX8MQ_CLK_DUMMY] = clk_fixed("dummy", 0);
+ clks[IMX8MQ_CLK_32K] = of_clk_get_by_name(ccm_node, "ckil");
+ clks[IMX8MQ_CLK_25M] = of_clk_get_by_name(ccm_node, "osc_25m");
+ clks[IMX8MQ_CLK_27M] = of_clk_get_by_name(ccm_node, "osc_27m");
+ clks[IMX8MQ_CLK_EXT1] = of_clk_get_by_name(ccm_node, "clk_ext1");
+ clks[IMX8MQ_CLK_EXT2] = of_clk_get_by_name(ccm_node, "clk_ext2");
+ clks[IMX8MQ_CLK_EXT3] = of_clk_get_by_name(ccm_node, "clk_ext3");
+ clks[IMX8MQ_CLK_EXT4] = of_clk_get_by_name(ccm_node, "clk_ext4");
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop");
+ base = of_iomap(np, 0);
+ WARN_ON(!base);
+
+ clks[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_SYS1_PLL1_REF_SEL] = imx_clk_mux("sys1_pll1_ref_sel", base + 0x30, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_SYS2_PLL1_REF_SEL] = imx_clk_mux("sys2_pll1_ref_sel", base + 0x3c, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_VIDEO2_PLL1_REF_SEL] = imx_clk_mux("video2_pll1_ref_sel", base + 0x54, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+
+ clks[IMX8MQ_ARM_PLL_REF_DIV] = imx_clk_divider("arm_pll_ref_div", "arm_pll_ref_sel", base + 0x28, 5, 6);
+ clks[IMX8MQ_GPU_PLL_REF_DIV] = imx_clk_divider("gpu_pll_ref_div", "gpu_pll_ref_sel", base + 0x18, 5, 6);
+ clks[IMX8MQ_VPU_PLL_REF_DIV] = imx_clk_divider("vpu_pll_ref_div", "vpu_pll_ref_sel", base + 0x20, 5, 6);
+ clks[IMX8MQ_AUDIO_PLL1_REF_DIV] = imx_clk_divider("audio_pll1_ref_div", "audio_pll1_ref_sel", base + 0x0, 5, 6);
+ clks[IMX8MQ_AUDIO_PLL2_REF_DIV] = imx_clk_divider("audio_pll2_ref_div", "audio_pll2_ref_sel", base + 0x8, 5, 6);
+ clks[IMX8MQ_VIDEO_PLL1_REF_DIV] = imx_clk_divider("video_pll1_ref_div", "video_pll1_ref_sel", base + 0x10, 5, 6);
+ clks[IMX8MQ_SYS1_PLL1_REF_DIV] = imx_clk_divider("sys1_pll1_ref_div", "sys1_pll1_ref_sel", base + 0x38, 25, 3);
+ clks[IMX8MQ_SYS2_PLL1_REF_DIV] = imx_clk_divider("sys2_pll1_ref_div", "sys2_pll1_ref_sel", base + 0x44, 25, 3);
+ clks[IMX8MQ_SYS3_PLL1_REF_DIV] = imx_clk_divider("sys3_pll1_ref_div", "sys3_pll1_ref_sel", base + 0x50, 25, 3);
+ clks[IMX8MQ_DRAM_PLL1_REF_DIV] = imx_clk_divider("dram_pll1_ref_div", "dram_pll1_ref_sel", base + 0x68, 25, 3);
+ clks[IMX8MQ_VIDEO2_PLL1_REF_DIV] = imx_clk_divider("video2_pll1_ref_div", "video2_pll1_ref_sel", base + 0x5c, 25, 3);
+
+ clks[IMX8MQ_ARM_PLL] = imx_clk_frac_pll("arm_pll", "arm_pll_ref_div", base + 0x28);
+ clks[IMX8MQ_GPU_PLL] = imx_clk_frac_pll("gpu_pll", "gpu_pll_ref_div", base + 0x18);
+ clks[IMX8MQ_VPU_PLL] = imx_clk_frac_pll("vpu_pll", "vpu_pll_ref_div", base + 0x20);
+ clks[IMX8MQ_AUDIO_PLL1] = imx_clk_frac_pll("audio_pll1", "audio_pll1_ref_div", base + 0x0);
+ clks[IMX8MQ_AUDIO_PLL2] = imx_clk_frac_pll("audio_pll2", "audio_pll2_ref_div", base + 0x8);
+ clks[IMX8MQ_VIDEO_PLL1] = imx_clk_frac_pll("video_pll1", "video_pll1_ref_div", base + 0x10);
+ clks[IMX8MQ_SYS1_PLL1] = imx_clk_sccg_pll("sys1_pll1", "sys1_pll1_ref_div", base + 0x30, SCCG_PLL1);
+ clks[IMX8MQ_SYS2_PLL1] = imx_clk_sccg_pll("sys2_pll1", "sys2_pll1_ref_div", base + 0x3c, SCCG_PLL1);
+ clks[IMX8MQ_SYS3_PLL1] = imx_clk_sccg_pll("sys3_pll1", "sys3_pll1_ref_div", base + 0x48, SCCG_PLL1);
+ clks[IMX8MQ_DRAM_PLL1] = imx_clk_sccg_pll("dram_pll1", "dram_pll1_ref_div", base + 0x60, SCCG_PLL1);
+ clks[IMX8MQ_VIDEO2_PLL1] = imx_clk_sccg_pll("video2_pll1", "video2_pll1_ref_div", base + 0x5c, SCCG_PLL1);
+
+ clks[IMX8MQ_SYS1_PLL2] = imx_clk_sccg_pll("sys1_pll2", "sys1_pll1_out_div", base + 0x30, SCCG_PLL2);
+ clks[IMX8MQ_SYS2_PLL2] = imx_clk_sccg_pll("sys2_pll2", "sys2_pll1_out_div", base + 0x3c, SCCG_PLL2);
+ clks[IMX8MQ_SYS3_PLL2] = imx_clk_sccg_pll("sys3_pll2", "sys3_pll1_out_div", base + 0x48, SCCG_PLL2);
+ clks[IMX8MQ_DRAM_PLL2] = imx_clk_sccg_pll("dram_pll2", "dram_pll1_out_div", base + 0x60, SCCG_PLL2);
+ clks[IMX8MQ_VIDEO2_PLL2] = imx_clk_sccg_pll("video2_pll2", "video2_pll1_out_div", base + 0x54, SCCG_PLL2);
+
+ /* PLL divs */
+ clks[IMX8MQ_SYS1_PLL1_OUT_DIV] = imx_clk_divider("sys1_pll1_out_div", "sys1_pll1_out", base + 0x38, 19, 6);
+ clks[IMX8MQ_SYS2_PLL1_OUT_DIV] = imx_clk_divider("sys2_pll1_out_div", "sys2_pll1_out", base + 0x44, 19, 6);
+ clks[IMX8MQ_SYS3_PLL1_OUT_DIV] = imx_clk_divider("sys3_pll1_out_div", "sys3_pll1_out", base + 0x50, 19, 6);
+ clks[IMX8MQ_DRAM_PLL1_OUT_DIV] = imx_clk_divider("dram_pll1_out_div", "dram_pll1_out", base + 0x68, 19, 6);
+ clks[IMX8MQ_VIDEO2_PLL1_OUT_DIV] = imx_clk_divider("video2_pll1_out_div", "video2_pll1_out", base + 0x5c, 19, 6);
+ clks[IMX8MQ_SYS1_PLL2_DIV] = imx_clk_divider("sys1_pll2_div", "sys1_pll2", base + 0x38, 1, 6);
+ clks[IMX8MQ_SYS2_PLL2_DIV] = imx_clk_divider("sys2_pll2_div", "sys2_pll2", base + 0x44, 1, 6);
+ clks[IMX8MQ_SYS3_PLL2_DIV] = imx_clk_divider("sys3_pll2_div", "sys3_pll2", base + 0x50, 1, 6);
+ clks[IMX8MQ_DRAM_PLL2_DIV] = imx_clk_divider("dram_pll2_div", "dram_pll2", base + 0x68, 1, 6);
+ clks[IMX8MQ_VIDEO2_PLL2_DIV] = imx_clk_divider("video2_pll2_div", "video2_pll2", base + 0x5c, 1, 6);
+
+ /* PLL bypass out */
+ clks[IMX8MQ_ARM_PLL_BYPASS] = imx_clk_mux("arm_pll_bypass", base + 0x28, 14, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels));
+ clks[IMX8MQ_GPU_PLL_BYPASS] = imx_clk_mux("gpu_pll_bypass", base + 0x18, 14, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels));
+ clks[IMX8MQ_VPU_PLL_BYPASS] = imx_clk_mux("vpu_pll_bypass", base + 0x20, 14, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels));
+ clks[IMX8MQ_AUDIO_PLL1_BYPASS] = imx_clk_mux("audio_pll1_bypass", base + 0x0, 14, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels));
+ clks[IMX8MQ_AUDIO_PLL2_BYPASS] = imx_clk_mux("audio_pll2_bypass", base + 0x8, 14, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels));
+ clks[IMX8MQ_VIDEO_PLL1_BYPASS] = imx_clk_mux("video_pll1_bypass", base + 0x10, 14, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels));
+
+ clks[IMX8MQ_SYS1_PLL1_OUT] = imx_clk_mux("sys1_pll1_out", base + 0x30, 5, 1, sys1_pll1_out_sels, ARRAY_SIZE(sys1_pll1_out_sels));
+ clks[IMX8MQ_SYS2_PLL1_OUT] = imx_clk_mux("sys2_pll1_out", base + 0x3c, 5, 1, sys2_pll1_out_sels, ARRAY_SIZE(sys2_pll1_out_sels));
+ clks[IMX8MQ_SYS3_PLL1_OUT] = imx_clk_mux("sys3_pll1_out", base + 0x48, 5, 1, sys3_pll1_out_sels, ARRAY_SIZE(sys3_pll1_out_sels));
+ clks[IMX8MQ_DRAM_PLL1_OUT] = imx_clk_mux("dram_pll1_out", base + 0x60, 5, 1, dram_pll1_out_sels, ARRAY_SIZE(dram_pll1_out_sels));
+ clks[IMX8MQ_VIDEO2_PLL1_OUT] = imx_clk_mux("video2_pll1_out", base + 0x54, 5, 1, video2_pll1_out_sels, ARRAY_SIZE(video2_pll1_out_sels));
+ clks[IMX8MQ_SYS1_PLL2_OUT] = imx_clk_mux("sys1_pll2_out", base + 0x30, 4, 1, sys1_pll2_out_sels, ARRAY_SIZE(sys1_pll2_out_sels));
+ clks[IMX8MQ_SYS2_PLL2_OUT] = imx_clk_mux("sys2_pll2_out", base + 0x3c, 4, 1, sys2_pll2_out_sels, ARRAY_SIZE(sys2_pll2_out_sels));
+ clks[IMX8MQ_SYS3_PLL2_OUT] = imx_clk_mux("sys3_pll2_out", base + 0x48, 4, 1, sys3_pll2_out_sels, ARRAY_SIZE(sys3_pll2_out_sels));
+ clks[IMX8MQ_DRAM_PLL2_OUT] = imx_clk_mux("dram_pll2_out", base + 0x60, 4, 1, dram_pll2_out_sels, ARRAY_SIZE(dram_pll2_out_sels));
+ clks[IMX8MQ_VIDEO2_PLL2_OUT] = imx_clk_mux("video2_pll2_out", base + 0x54, 4, 1, video2_pll2_out_sels, ARRAY_SIZE(video2_pll2_out_sels));
+
+ /* unbypass all the plls */
+ clk_set_parent(clks[IMX8MQ_GPU_PLL_BYPASS], clks[IMX8MQ_GPU_PLL]);
+ clk_set_parent(clks[IMX8MQ_VPU_PLL_BYPASS], clks[IMX8MQ_VPU_PLL]);
+ clk_set_parent(clks[IMX8MQ_AUDIO_PLL1_BYPASS], clks[IMX8MQ_AUDIO_PLL1]);
+ clk_set_parent(clks[IMX8MQ_AUDIO_PLL2_BYPASS], clks[IMX8MQ_AUDIO_PLL2]);
+ clk_set_parent(clks[IMX8MQ_VIDEO_PLL1_BYPASS], clks[IMX8MQ_VIDEO_PLL1]);
+ clk_set_parent(clks[IMX8MQ_SYS3_PLL1_OUT], clks[IMX8MQ_SYS3_PLL1]);
+ clk_set_parent(clks[IMX8MQ_SYS3_PLL2_OUT], clks[IMX8MQ_SYS3_PLL2_DIV]);
+
+ /* PLL OUT GATE */
+ clks[IMX8MQ_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x28, 21);
+ clks[IMX8MQ_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x18, 21);
+ clks[IMX8MQ_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x20, 21);
+ clks[IMX8MQ_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base + 0x0, 21);
+ clks[IMX8MQ_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x8, 21);
+ clks[IMX8MQ_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x10, 21);
+ clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_gate("sys1_pll_out", "sys1_pll2_out", base + 0x30, 9);
+ clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_gate("sys2_pll_out", "sys2_pll2_out", base + 0x3c, 9);
+ clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_gate("sys3_pll_out", "sys3_pll2_out", base + 0x48, 9);
+ clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll2_out", base + 0x60, 9);
+ clks[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_gate("video2_pll_out", "video2_pll2_out", base + 0x54, 9);
+
+ /* SYS PLL fixed output */
+ clks[IMX8MQ_SYS1_PLL_40M] = imx_clk_fixed_factor("sys1_pll_40m", "sys1_pll_out", 1, 20);
+ clks[IMX8MQ_SYS1_PLL_80M] = imx_clk_fixed_factor("sys1_pll_80m", "sys1_pll_out", 1, 10);
+ clks[IMX8MQ_SYS1_PLL_100M] = imx_clk_fixed_factor("sys1_pll_100m", "sys1_pll_out", 1, 8);
+ clks[IMX8MQ_SYS1_PLL_133M] = imx_clk_fixed_factor("sys1_pll_133m", "sys1_pll_out", 1, 6);
+ clks[IMX8MQ_SYS1_PLL_160M] = imx_clk_fixed_factor("sys1_pll_160m", "sys1_pll_out", 1, 5);
+ clks[IMX8MQ_SYS1_PLL_200M] = imx_clk_fixed_factor("sys1_pll_200m", "sys1_pll_out", 1, 4);
+ clks[IMX8MQ_SYS1_PLL_266M] = imx_clk_fixed_factor("sys1_pll_266m", "sys1_pll_out", 1, 3);
+ clks[IMX8MQ_SYS1_PLL_400M] = imx_clk_fixed_factor("sys1_pll_400m", "sys1_pll_out", 1, 2);
+ clks[IMX8MQ_SYS1_PLL_800M] = imx_clk_fixed_factor("sys1_pll_800m", "sys1_pll_out", 1, 1);
+
+ clks[IMX8MQ_SYS2_PLL_50M] = imx_clk_fixed_factor("sys2_pll_50m", "sys2_pll_out", 1, 20);
+ clks[IMX8MQ_SYS2_PLL_100M] = imx_clk_fixed_factor("sys2_pll_100m", "sys2_pll_out", 1, 10);
+ clks[IMX8MQ_SYS2_PLL_125M] = imx_clk_fixed_factor("sys2_pll_125m", "sys2_pll_out", 1, 8);
+ clks[IMX8MQ_SYS2_PLL_166M] = imx_clk_fixed_factor("sys2_pll_166m", "sys2_pll_out", 1, 6);
+ clks[IMX8MQ_SYS2_PLL_200M] = imx_clk_fixed_factor("sys2_pll_200m", "sys2_pll_out", 1, 5);
+ clks[IMX8MQ_SYS2_PLL_250M] = imx_clk_fixed_factor("sys2_pll_250m", "sys2_pll_out", 1, 4);
+ clks[IMX8MQ_SYS2_PLL_333M] = imx_clk_fixed_factor("sys2_pll_333m", "sys2_pll_out", 1, 3);
+ clks[IMX8MQ_SYS2_PLL_500M] = imx_clk_fixed_factor("sys2_pll_500m", "sys2_pll_out", 1, 2);
+ clks[IMX8MQ_SYS2_PLL_1000M] = imx_clk_fixed_factor("sys2_pll_1000m", "sys2_pll_out", 1, 1);
+
+ np = ccm_node;
+ base = of_iomap(np, 0);
+ WARN_ON(!base);
+ /* CORE */
+ clks[IMX8MQ_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));
+ clks[IMX8MQ_CLK_A53_CG] = imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
+ clks[IMX8MQ_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
+
+ /* BUS */
+ clks[IMX8MQ_CLK_MAIN_AXI_SRC] = imx_clk_mux2("main_axi_src", base + 0x8800, 24, 3, imx8mq_main_axi_sels, ARRAY_SIZE(imx8mq_main_axi_sels));
+ clks[IMX8MQ_CLK_ENET_AXI_SRC] = imx_clk_mux2("enet_axi_src", base + 0x8880, 24, 3, imx8mq_enet_axi_sels, ARRAY_SIZE(imx8mq_enet_axi_sels));
+ clks[IMX8MQ_CLK_NAND_USDHC_BUS_SRC] = imx_clk_mux2("nand_usdhc_bus_src", base + 0x8900, 24, 3, imx8mq_nand_usdhc_sels, ARRAY_SIZE(imx8mq_nand_usdhc_sels));
+ clks[IMX8MQ_CLK_USB_BUS_SRC] = imx_clk_mux2("usb_bus_src", base + 0x8b80, 24, 3, imx8mq_usb_bus_sels, ARRAY_SIZE(imx8mq_usb_bus_sels));
+ clks[IMX8MQ_CLK_NOC_SRC] = imx_clk_mux2("noc_src", base + 0x8d00, 24, 3, imx8mq_noc_sels, ARRAY_SIZE(imx8mq_noc_sels));
+ clks[IMX8MQ_CLK_NOC_APB_SRC] = imx_clk_mux2("noc_apb_src", base + 0x8d80, 24, 3, imx8mq_noc_apb_sels, ARRAY_SIZE(imx8mq_noc_apb_sels));
+
+ clks[IMX8MQ_CLK_MAIN_AXI_CG] = imx_clk_gate3("main_axi_cg", "main_axi_src", base + 0x8800, 28);
+ clks[IMX8MQ_CLK_ENET_AXI_CG] = imx_clk_gate3("enet_axi_cg", "enet_axi_src", base + 0x8880, 28);
+ clks[IMX8MQ_CLK_NAND_USDHC_BUS_CG] = imx_clk_gate3("nand_usdhc_bus_cg", "nand_usdhc_bus_src", base + 0x8900, 28);
+ clks[IMX8MQ_CLK_USB_BUS_CG] = imx_clk_gate3("usb_bus_cg", "usb_bus_src", base + 0x8b80, 28);
+ clks[IMX8MQ_CLK_NOC_CG] = imx_clk_gate3("noc_cg", "noc_src", base + 0x8d00, 28);
+ clks[IMX8MQ_CLK_NOC_APB_CG] = imx_clk_gate3("noc_apb_cg", "noc_apb_src", base + 0x8d80, 28);
+
+ clks[IMX8MQ_CLK_MAIN_AXI_PRE_DIV] = imx_clk_divider2("main_axi_pre_div", "main_axi_cg", base + 0x8800, 16, 3);
+ clks[IMX8MQ_CLK_ENET_AXI_PRE_DIV] = imx_clk_divider2("enet_axi_pre_div", "enet_axi_cg", base + 0x8880, 16, 3);
+ clks[IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV] = imx_clk_divider2("nand_usdhc_bus_pre_div", "nand_usdhc_bus_cg", base + 0x8900, 16, 3);
+ clks[IMX8MQ_CLK_DISP_AXI_PRE_DIV] = imx_clk_divider2("disp_axi_pre_div", "disp_axi_cg", base + 0x8a00, 16, 3);
+ clks[IMX8MQ_CLK_DISP_APB_PRE_DIV] = imx_clk_divider2("disp_apb_pre_div", "disp_apb_cg", base + 0x8a80, 16, 3);
+ clks[IMX8MQ_CLK_DISP_RTRM_PRE_DIV] = imx_clk_divider2("disp_rtrm_pre_div", "disp_rtrm_cg", base + 0x8b00, 16, 3);
+ clks[IMX8MQ_CLK_USB_BUS_PRE_DIV] = imx_clk_divider2("usb_bus_pre_div", "usb_bus_cg", base + 0x8b80, 16, 3);
+ clks[IMX8MQ_CLK_GPU_AXI_PRE_DIV] = imx_clk_divider2("gpu_axi_pre_div", "gpu_axi_cg", base + 0x8c00, 16, 3);
+ clks[IMX8MQ_CLK_GPU_AHB_PRE_DIV] = imx_clk_divider2("gpu_ahb_pre_div", "gpu_ahb_cg", base + 0x8c80, 16, 3);
+ clks[IMX8MQ_CLK_NOC_PRE_DIV] = imx_clk_divider2("noc_pre_div", "noc_cg", base + 0x8d00, 16, 3);
+ clks[IMX8MQ_CLK_NOC_APB_PRE_DIV] = imx_clk_divider2("noc_apb_pre_div", "noc_apb_cg", base + 0x8d80, 16, 3);
+
+ clks[IMX8MQ_CLK_MAIN_AXI_DIV] = imx_clk_divider2("main_axi_div", "main_axi_pre_div", base + 0x8800, 0, 6);
+ clks[IMX8MQ_CLK_ENET_AXI_DIV] = imx_clk_divider2("enet_axi_div", "enet_axi_pre_div", base + 0x8880, 0, 6);
+ clks[IMX8MQ_CLK_NAND_USDHC_BUS_DIV] = imx_clk_divider2("nand_usdhc_bus_div", "nand_usdhc_bus_pre_div", base + 0x8900, 0, 6);
+ clks[IMX8MQ_CLK_USB_BUS_DIV] = imx_clk_divider2("usb_bus_div", "usb_bus_pre_div", base + 0x8b80, 0, 6);
+ clks[IMX8MQ_CLK_NOC_DIV] = imx_clk_divider2("noc_div", "noc_pre_div", base + 0x8d00, 0, 6);
+ clks[IMX8MQ_CLK_NOC_APB_DIV] = imx_clk_divider2("noc_apb_div", "noc_apb_pre_div", base + 0x8d80, 0, 6);
+
+ /* AHB */
+ clks[IMX8MQ_CLK_AHB_SRC] = imx_clk_mux2("ahb_src", base + 0x9000, 24, 3, imx8mq_ahb_sels, ARRAY_SIZE(imx8mq_ahb_sels));
+ clks[IMX8MQ_CLK_AHB_CG] = imx_clk_gate3("ahb_cg", "ahb_src", base + 0x9000, 28);
+ clks[IMX8MQ_CLK_AHB_PRE_DIV] = imx_clk_divider2("ahb_pre_div", "ahb_cg", base + 0x9000, 16, 3);
+ clks[IMX8MQ_CLK_AHB_DIV] = imx_clk_divider_flags("ahb_div", "ahb_pre_div", base + 0x9000, 0, 6, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
+
+ /* IPG */
+ clks[IMX8MQ_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb_div", base + 0x9080, 0, 1);
+
+ /* IP */
+ clks[IMX8MQ_CLK_DRAM_ALT_SRC] = imx_clk_mux2("dram_alt_src", base + 0xa000, 24, 3, imx8mq_dram_alt_sels, ARRAY_SIZE(imx8mq_dram_alt_sels));
+ clks[IMX8MQ_CLK_DRAM_CORE] = imx_clk_mux2("dram_core_clk", base + 0x9800, 24, 1, imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels));
+ clks[IMX8MQ_CLK_DRAM_APB_SRC] = imx_clk_mux2("dram_apb_src", base + 0xa080, 24, 3, imx8mq_dram_apb_sels, ARRAY_SIZE(imx8mq_dram_apb_sels));
+ clks[IMX8MQ_CLK_PCIE1_CTRL_SRC] = imx_clk_mux2("pcie1_ctrl_src", base + 0xa300, 24, 3, imx8mq_pcie1_ctrl_sels, ARRAY_SIZE(imx8mq_pcie1_ctrl_sels));
+ clks[IMX8MQ_CLK_PCIE1_PHY_SRC] = imx_clk_mux2("pcie1_phy_src", base + 0xa380, 24, 3, imx8mq_pcie1_phy_sels, ARRAY_SIZE(imx8mq_pcie1_phy_sels));
+ clks[IMX8MQ_CLK_PCIE1_AUX_SRC] = imx_clk_mux2("pcie1_aux_src", base + 0xa400, 24, 3, imx8mq_pcie1_aux_sels, ARRAY_SIZE(imx8mq_pcie1_aux_sels));
+ clks[IMX8MQ_CLK_DC_PIXEL_SRC] = imx_clk_mux2("dc_pixel_src", base + 0xa480, 24, 3, imx8mq_dc_pixel_sels, ARRAY_SIZE(imx8mq_dc_pixel_sels));
+ clks[IMX8MQ_CLK_LCDIF_PIXEL_SRC] = imx_clk_mux2("lcdif_pixel_src", base + 0xa500, 24, 3, imx8mq_lcdif_pixel_sels, ARRAY_SIZE(imx8mq_lcdif_pixel_sels));
+ clks[IMX8MQ_CLK_ENET_REF_SRC] = imx_clk_mux2("enet_ref_src", base + 0xa980, 24, 3, imx8mq_enet_ref_sels, ARRAY_SIZE(imx8mq_enet_ref_sels));
+ clks[IMX8MQ_CLK_ENET_TIMER_SRC] = imx_clk_mux2("enet_timer_src", base + 0xaa00, 24, 3, imx8mq_enet_timer_sels, ARRAY_SIZE(imx8mq_enet_timer_sels));
+ clks[IMX8MQ_CLK_ENET_PHY_REF_SRC] = imx_clk_mux2("enet_phy_src", base + 0xaa80, 24, 3, imx8mq_enet_phy_sels, ARRAY_SIZE(imx8mq_enet_phy_sels));
+ clks[IMX8MQ_CLK_NAND_SRC] = imx_clk_mux2("nand_src", base + 0xab00, 24, 3, imx8mq_nand_sels, ARRAY_SIZE(imx8mq_nand_sels));
+ clks[IMX8MQ_CLK_QSPI_SRC] = imx_clk_mux2("qspi_src", base + 0xab80, 24, 3, imx8mq_qspi_sels, ARRAY_SIZE(imx8mq_qspi_sels));
+ clks[IMX8MQ_CLK_USDHC1_SRC] = imx_clk_mux2("usdhc1_src", base + 0xac00, 24, 3, imx8mq_usdhc1_sels, ARRAY_SIZE(imx8mq_usdhc1_sels));
+ clks[IMX8MQ_CLK_USDHC2_SRC] = imx_clk_mux2("usdhc2_src", base + 0xac80, 24, 3, imx8mq_usdhc2_sels, ARRAY_SIZE(imx8mq_usdhc2_sels));
+ clks[IMX8MQ_CLK_I2C1_SRC] = imx_clk_mux2("i2c1_src", base + 0xad00, 24, 3, imx8mq_i2c1_sels, ARRAY_SIZE(imx8mq_i2c1_sels));
+ clks[IMX8MQ_CLK_I2C2_SRC] = imx_clk_mux2("i2c2_src", base + 0xad80, 24, 3, imx8mq_i2c2_sels, ARRAY_SIZE(imx8mq_i2c2_sels));
+ clks[IMX8MQ_CLK_I2C3_SRC] = imx_clk_mux2("i2c3_src", base + 0xae00, 24, 3, imx8mq_i2c3_sels, ARRAY_SIZE(imx8mq_i2c3_sels));
+ clks[IMX8MQ_CLK_I2C4_SRC] = imx_clk_mux2("i2c4_src", base + 0xae80, 24, 3, imx8mq_i2c4_sels, ARRAY_SIZE(imx8mq_i2c4_sels));
+ clks[IMX8MQ_CLK_UART1_SRC] = imx_clk_mux2("uart1_src", base + 0xaf00, 24, 3, imx8mq_uart1_sels, ARRAY_SIZE(imx8mq_uart1_sels));
+ clks[IMX8MQ_CLK_UART2_SRC] = imx_clk_mux2("uart2_src", base + 0xaf80, 24, 3, imx8mq_uart2_sels, ARRAY_SIZE(imx8mq_uart2_sels));
+ clks[IMX8MQ_CLK_UART3_SRC] = imx_clk_mux2("uart3_src", base + 0xb000, 24, 3, imx8mq_uart3_sels, ARRAY_SIZE(imx8mq_uart3_sels));
+ clks[IMX8MQ_CLK_UART4_SRC] = imx_clk_mux2("uart4_src", base + 0xb080, 24, 3, imx8mq_uart4_sels, ARRAY_SIZE(imx8mq_uart4_sels));
+ clks[IMX8MQ_CLK_USB_CORE_REF_SRC] = imx_clk_mux2("usb_core_ref_src", base + 0xb100, 24, 3, imx8mq_usb_core_sels, ARRAY_SIZE(imx8mq_usb_core_sels));
+ clks[IMX8MQ_CLK_USB_PHY_REF_SRC] = imx_clk_mux2("usb_phy_ref_src", base + 0xb180, 24, 3, imx8mq_usb_phy_sels, ARRAY_SIZE(imx8mq_usb_phy_sels));
+ clks[IMX8MQ_CLK_ECSPI1_SRC] = imx_clk_mux2("ecspi1_src", base + 0xb280, 24, 3, imx8mq_ecspi1_sels, ARRAY_SIZE(imx8mq_ecspi1_sels));
+ clks[IMX8MQ_CLK_ECSPI2_SRC] = imx_clk_mux2("ecspi2_src", base + 0xb300, 24, 3, imx8mq_ecspi2_sels, ARRAY_SIZE(imx8mq_ecspi2_sels));
+ clks[IMX8MQ_CLK_PWM1_SRC] = imx_clk_mux2("pwm1_src", base + 0xb380, 24, 3, imx8mq_pwm1_sels, ARRAY_SIZE(imx8mq_pwm1_sels));
+ clks[IMX8MQ_CLK_PWM2_SRC] = imx_clk_mux2("pwm2_src", base + 0xb400, 24, 3, imx8mq_pwm2_sels, ARRAY_SIZE(imx8mq_pwm2_sels));
+ clks[IMX8MQ_CLK_PWM3_SRC] = imx_clk_mux2("pwm3_src", base + 0xb480, 24, 3, imx8mq_pwm3_sels, ARRAY_SIZE(imx8mq_pwm3_sels));
+ clks[IMX8MQ_CLK_PWM4_SRC] = imx_clk_mux2("pwm4_src", base + 0xb500, 24, 3, imx8mq_pwm4_sels, ARRAY_SIZE(imx8mq_pwm4_sels));
+ clks[IMX8MQ_CLK_GPT1_SRC] = imx_clk_mux2("gpt1_src", base + 0xb580, 24, 3, imx8mq_gpt1_sels, ARRAY_SIZE(imx8mq_gpt1_sels));
+ clks[IMX8MQ_CLK_WDOG_SRC] = imx_clk_mux2("wdog_src", base + 0xb900, 24, 3, imx8mq_wdog_sels, ARRAY_SIZE(imx8mq_wdog_sels));
+ clks[IMX8MQ_CLK_WRCLK_SRC] = imx_clk_mux2("wrclk_src", base + 0xb980, 24, 3, imx8mq_wrclk_sels, ARRAY_SIZE(imx8mq_wrclk_sels));
+ clks[IMX8MQ_CLK_CLKO2_SRC] = imx_clk_mux2("clko2_src", base + 0xba80, 24, 3, imx8mq_clko2_sels, ARRAY_SIZE(imx8mq_clko2_sels));
+ clks[IMX8MQ_CLK_PCIE2_CTRL_SRC] = imx_clk_mux2("pcie2_ctrl_src", base + 0xc000, 24, 3, imx8mq_pcie2_ctrl_sels, ARRAY_SIZE(imx8mq_pcie2_ctrl_sels));
+ clks[IMX8MQ_CLK_PCIE2_PHY_SRC] = imx_clk_mux2("pcie2_phy_src", base + 0xc080, 24, 3, imx8mq_pcie2_phy_sels, ARRAY_SIZE(imx8mq_pcie2_phy_sels));
+ clks[IMX8MQ_CLK_PCIE2_AUX_SRC] = imx_clk_mux2("pcie2_aux_src", base + 0xc100, 24, 3, imx8mq_pcie2_aux_sels, ARRAY_SIZE(imx8mq_pcie2_aux_sels));
+ clks[IMX8MQ_CLK_ECSPI3_SRC] = imx_clk_mux2("ecspi3_src", base + 0xc180, 24, 3, imx8mq_ecspi3_sels, ARRAY_SIZE(imx8mq_ecspi3_sels));
+
+ clks[IMX8MQ_CLK_DRAM_ALT_CG] = imx_clk_gate3("dram_alt_cg", "dram_alt_src", base + 0xa000, 28);
+ clks[IMX8MQ_CLK_DRAM_APB_CG] = imx_clk_gate3("dram_apb_cg", "dram_apb_src", base + 0xa080, 28);
+ clks[IMX8MQ_CLK_PCIE1_CTRL_CG] = imx_clk_gate3("pcie1_ctrl_cg", "pcie1_ctrl_src", base + 0xa300, 28);
+ clks[IMX8MQ_CLK_PCIE1_PHY_CG] = imx_clk_gate3("pcie1_phy_cg", "pcie1_phy_src", base + 0xa380, 28);
+ clks[IMX8MQ_CLK_PCIE1_AUX_CG] = imx_clk_gate3("pcie1_aux_cg", "pcie1_aux_src", base + 0xa400, 28);
+ clks[IMX8MQ_CLK_ENET_REF_CG] = imx_clk_gate3("enet_ref_cg", "enet_ref_src", base + 0xa980, 28);
+ clks[IMX8MQ_CLK_ENET_TIMER_CG] = imx_clk_gate3("enet_timer_cg", "enet_timer_src", base + 0xaa00, 28);
+ clks[IMX8MQ_CLK_ENET_PHY_REF_CG] = imx_clk_gate3("enet_phy_cg", "enet_phy_src", base + 0xaa80, 28);
+ clks[IMX8MQ_CLK_NAND_CG] = imx_clk_gate3("nand_cg", "nand_src", base + 0xab00, 28);
+ clks[IMX8MQ_CLK_QSPI_CG] = imx_clk_gate3("qspi_cg", "qspi_src", base + 0xab80, 28);
+ clks[IMX8MQ_CLK_USDHC1_CG] = imx_clk_gate3("usdhc1_cg", "usdhc1_src", base + 0xac00, 28);
+ clks[IMX8MQ_CLK_USDHC2_CG] = imx_clk_gate3("usdhc2_cg", "usdhc2_src", base + 0xac80, 28);
+ clks[IMX8MQ_CLK_I2C1_CG] = imx_clk_gate3("i2c1_cg", "i2c1_src", base + 0xad00, 28);
+ clks[IMX8MQ_CLK_I2C2_CG] = imx_clk_gate3("i2c2_cg", "i2c2_src", base + 0xad80, 28);
+ clks[IMX8MQ_CLK_I2C3_CG] = imx_clk_gate3("i2c3_cg", "i2c3_src", base + 0xae00, 28);
+ clks[IMX8MQ_CLK_I2C4_CG] = imx_clk_gate3("i2c4_cg", "i2c4_src", base + 0xae80, 28);
+ clks[IMX8MQ_CLK_UART1_CG] = imx_clk_gate3("uart1_cg", "uart1_src", base + 0xaf00, 28);
+ clks[IMX8MQ_CLK_UART2_CG] = imx_clk_gate3("uart2_cg", "uart2_src", base + 0xaf80, 28);
+ clks[IMX8MQ_CLK_UART3_CG] = imx_clk_gate3("uart3_cg", "uart3_src", base + 0xb000, 28);
+ clks[IMX8MQ_CLK_UART4_CG] = imx_clk_gate3("uart4_cg", "uart4_src", base + 0xb080, 28);
+ clks[IMX8MQ_CLK_USB_CORE_REF_CG] = imx_clk_gate3("usb_core_ref_cg", "usb_core_ref_src", base + 0xb100, 28);
+ clks[IMX8MQ_CLK_USB_PHY_REF_CG] = imx_clk_gate3("usb_phy_ref_cg", "usb_phy_ref_src", base + 0xb180, 28);
+ clks[IMX8MQ_CLK_ECSPI1_CG] = imx_clk_gate3("ecspi1_cg", "ecspi1_src", base + 0xb280, 28);
+ clks[IMX8MQ_CLK_ECSPI2_CG] = imx_clk_gate3("ecspi2_cg", "ecspi2_src", base + 0xb300, 28);
+ clks[IMX8MQ_CLK_PWM1_CG] = imx_clk_gate3("pwm1_cg", "pwm1_src", base + 0xb380, 28);
+ clks[IMX8MQ_CLK_PWM2_CG] = imx_clk_gate3("pwm2_cg", "pwm2_src", base + 0xb400, 28);
+ clks[IMX8MQ_CLK_PWM3_CG] = imx_clk_gate3("pwm3_cg", "pwm3_src", base + 0xb480, 28);
+ clks[IMX8MQ_CLK_PWM4_CG] = imx_clk_gate3("pwm4_cg", "pwm4_src", base + 0xb500, 28);
+ clks[IMX8MQ_CLK_GPT1_CG] = imx_clk_gate3("gpt1_cg", "gpt1_src", base + 0xb580, 28);
+ clks[IMX8MQ_CLK_WDOG_CG] = imx_clk_gate3("wdog_cg", "wdog_src", base + 0xb900, 28);
+ clks[IMX8MQ_CLK_WRCLK_CG] = imx_clk_gate3("wrclk_cg", "wrclk_src", base + 0xb980, 28);
+ clks[IMX8MQ_CLK_CLKO2_CG] = imx_clk_gate3("clko2_cg", "clko2_src", base + 0xba80, 28);
+ clks[IMX8MQ_CLK_PCIE2_CTRL_CG] = imx_clk_gate3("pcie2_ctrl_cg", "pcie2_ctrl_src", base + 0xc000, 28);
+ clks[IMX8MQ_CLK_PCIE2_PHY_CG] = imx_clk_gate3("pcie2_phy_cg", "pcie2_phy_src", base + 0xc080, 28);
+ clks[IMX8MQ_CLK_PCIE2_AUX_CG] = imx_clk_gate3("pcie2_aux_cg", "pcie2_aux_src", base + 0xc100, 28);
+ clks[IMX8MQ_CLK_ECSPI3_CG] = imx_clk_gate3("ecspi3_cg", "ecspi3_src", base + 0xc180, 28);
+
+ clks[IMX8MQ_CLK_DRAM_ALT_PRE_DIV] = imx_clk_divider2("dram_alt_pre_div", "dram_alt_cg", base + 0xa000, 16, 3);
+ clks[IMX8MQ_CLK_DRAM_APB_PRE_DIV] = imx_clk_divider_flags("dram_apb_pre_div", "dram_apb_cg", base + 0xa080, 16, 3, CLK_OPS_PARENT_ENABLE);
+ clks[IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV] = imx_clk_divider2("pcie1_ctrl_pre_div", "pcie1_ctrl_cg", base + 0xa300, 16, 3);
+ clks[IMX8MQ_CLK_PCIE1_PHY_PRE_DIV] = imx_clk_divider2("pcie1_phy_pre_div", "pcie1_phy_cg", base + 0xa380, 16, 3);
+ clks[IMX8MQ_CLK_PCIE1_AUX_PRE_DIV] = imx_clk_divider2("pcie1_aux_pre_div", "pcie1_aux_cg", base + 0xa400, 16, 3);
+ clks[IMX8MQ_CLK_DC_PIXEL_PRE_DIV] = imx_clk_divider2("dc_pixel_pre_div", "dc_pixel_cg", base + 0xa480, 16, 3);
+ clks[IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV] = imx_clk_divider2("lcdif_pixel_pre_div", "lcdif_pixel_cg", base + 0xa500, 16, 3);
+ clks[IMX8MQ_CLK_SPDIF1_PRE_DIV] = imx_clk_divider2("spdif1_pre_div", "spdif1_cg", base + 0xa880, 16, 3);
+ clks[IMX8MQ_CLK_SPDIF2_PRE_DIV] = imx_clk_divider2("spdif2_pre_div", "spdif2_cg", base + 0xa900, 16, 3);
+ clks[IMX8MQ_CLK_ENET_REF_PRE_DIV] = imx_clk_divider2("enet_ref_pre_div", "enet_ref_cg", base + 0xa980, 16, 3);
+ clks[IMX8MQ_CLK_ENET_TIMER_PRE_DIV] = imx_clk_divider2("enet_timer_pre_div", "enet_timer_cg", base + 0xaa00, 16, 3);
+ clks[IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV] = imx_clk_divider2("enet_phy_pre_div", "enet_phy_cg", base + 0xaa80, 16, 3);
+ clks[IMX8MQ_CLK_NAND_PRE_DIV] = imx_clk_divider2("nand_pre_div", "nand_cg", base + 0xab00, 16, 3);
+ clks[IMX8MQ_CLK_QSPI_PRE_DIV] = imx_clk_divider2("qspi_pre_div", "qspi_cg", base + 0xab80, 16, 3);
+ clks[IMX8MQ_CLK_USDHC1_PRE_DIV] = imx_clk_divider2("usdhc1_pre_div", "usdhc1_cg", base + 0xac00, 16, 3);
+ clks[IMX8MQ_CLK_USDHC2_PRE_DIV] = imx_clk_divider2("usdhc2_pre_div", "usdhc2_cg", base + 0xac80, 16, 3);
+ clks[IMX8MQ_CLK_I2C1_PRE_DIV] = imx_clk_divider2("i2c1_pre_div", "i2c1_cg", base + 0xad00, 16, 3);
+ clks[IMX8MQ_CLK_I2C2_PRE_DIV] = imx_clk_divider2("i2c2_pre_div", "i2c2_cg", base + 0xad80, 16, 3);
+ clks[IMX8MQ_CLK_I2C3_PRE_DIV] = imx_clk_divider2("i2c3_pre_div", "i2c3_cg", base + 0xae00, 16, 3);
+ clks[IMX8MQ_CLK_I2C4_PRE_DIV] = imx_clk_divider2("i2c4_pre_div", "i2c4_cg", base + 0xae80, 16, 3);
+ clks[IMX8MQ_CLK_UART1_PRE_DIV] = imx_clk_divider2("uart1_pre_div", "uart1_cg", base + 0xaf00, 16, 3);
+ clks[IMX8MQ_CLK_UART2_PRE_DIV] = imx_clk_divider2("uart2_pre_div", "uart2_cg", base + 0xaf80, 16, 3);
+ clks[IMX8MQ_CLK_UART3_PRE_DIV] = imx_clk_divider2("uart3_pre_div", "uart3_cg", base + 0xb000, 16, 3);
+ clks[IMX8MQ_CLK_UART4_PRE_DIV] = imx_clk_divider2("uart4_pre_div", "uart4_cg", base + 0xb080, 16, 3);
+ clks[IMX8MQ_CLK_USB_CORE_REF_PRE_DIV] = imx_clk_divider2("usb_core_ref_pre_div", "usb_core_ref_cg", base + 0xb100, 16, 3);
+ clks[IMX8MQ_CLK_USB_PHY_REF_PRE_DIV] = imx_clk_divider2("usb_phy_ref_pre_div", "usb_phy_ref_cg", base + 0xb180, 16, 3);
+ clks[IMX8MQ_CLK_ECSPI1_PRE_DIV] = imx_clk_divider2("ecspi1_pre_div", "ecspi1_cg", base + 0xb280, 16, 3);
+ clks[IMX8MQ_CLK_ECSPI2_PRE_DIV] = imx_clk_divider2("ecspi2_pre_div", "ecspi2_cg", base + 0xb300, 16, 3);
+ clks[IMX8MQ_CLK_PWM1_PRE_DIV] = imx_clk_divider2("pwm1_pre_div", "pwm1_cg", base + 0xb380, 16, 3);
+ clks[IMX8MQ_CLK_PWM2_PRE_DIV] = imx_clk_divider2("pwm2_pre_div", "pwm2_cg", base + 0xb400, 16, 3);
+ clks[IMX8MQ_CLK_PWM3_PRE_DIV] = imx_clk_divider2("pwm3_pre_div", "pwm3_cg", base + 0xb480, 16, 3);
+ clks[IMX8MQ_CLK_PWM4_PRE_DIV] = imx_clk_divider2("pwm4_pre_div", "pwm4_cg", base + 0xb500, 16, 3);
+ clks[IMX8MQ_CLK_GPT1_PRE_DIV] = imx_clk_divider2("gpt1_pre_div", "gpt1_cg", base + 0xb580, 16, 3);
+ clks[IMX8MQ_CLK_WDOG_PRE_DIV] = imx_clk_divider2("wdog_pre_div", "wdog_cg", base + 0xb900, 16, 3);
+ clks[IMX8MQ_CLK_WRCLK_PRE_DIV] = imx_clk_divider2("wrclk_pre_div", "wrclk_cg", base + 0xb980, 16, 3);
+ clks[IMX8MQ_CLK_CLKO2_PRE_DIV] = imx_clk_divider2("clko2_pre_div", "clko2_cg", base + 0xba80, 16, 3);
+ clks[IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV] = imx_clk_divider2("pcie2_ctrl_pre_div", "pcie2_ctrl_cg", base + 0xc000, 16, 3);
+ clks[IMX8MQ_CLK_PCIE2_PHY_PRE_DIV] = imx_clk_divider2("pcie2_phy_pre_div", "pcie2_phy_cg", base + 0xc080, 16, 3);
+ clks[IMX8MQ_CLK_PCIE2_AUX_PRE_DIV] = imx_clk_divider2("pcie2_aux_pre_div", "pcie2_aux_cg", base + 0xc100, 16, 3);
+ clks[IMX8MQ_CLK_ECSPI3_PRE_DIV] = imx_clk_divider2("ecspi3_pre_div", "ecspi3_cg", base + 0xc180, 16, 3);
+
+ clks[IMX8MQ_CLK_DRAM_ALT_DIV] = imx_clk_divider2("dram_alt_div", "dram_alt_pre_div", base + 0xa000, 0, 6);
+ clks[IMX8MQ_CLK_DRAM_APB_DIV] = imx_clk_divider2("dram_apb_div", "dram_apb_pre_div", base + 0xa080, 0, 6);
+ clks[IMX8MQ_CLK_PCIE1_CTRL_DIV] = imx_clk_divider2("pcie1_ctrl_div", "pcie1_ctrl_pre_div", base + 0xa300, 0, 6);
+ clks[IMX8MQ_CLK_PCIE1_PHY_DIV] = imx_clk_divider2("pcie1_phy_div", "pcie1_phy_pre_div", base + 0xa380, 0, 6);
+ clks[IMX8MQ_CLK_PCIE1_AUX_DIV] = imx_clk_divider2("pcie1_aux_div", "pcie1_aux_pre_div", base + 0xa400, 0, 6);
+ clks[IMX8MQ_CLK_DC_PIXEL_DIV] = imx_clk_divider2("dc_pixel_div", "dc_pixel_pre_div", base + 0xa480, 0, 6);
+ clks[IMX8MQ_CLK_LCDIF_PIXEL_DIV] = imx_clk_divider2("lcdif_pixel_div", "lcdif_pixel_pre_div", base + 0xa500, 0, 6);
+ clks[IMX8MQ_CLK_ENET_REF_DIV] = imx_clk_divider2("enet_ref_div", "enet_ref_pre_div", base + 0xa980, 0, 6);
+ clks[IMX8MQ_CLK_ENET_TIMER_DIV] = imx_clk_divider2("enet_timer_div", "enet_timer_pre_div", base + 0xaa00, 0, 6);
+ clks[IMX8MQ_CLK_ENET_PHY_REF_DIV] = imx_clk_divider2("enet_phy_div", "enet_phy_pre_div", base + 0xaa80, 0, 6);
+ clks[IMX8MQ_CLK_NAND_DIV] = imx_clk_divider2("nand_div", "nand_pre_div", base + 0xab00, 0, 6);
+ clks[IMX8MQ_CLK_QSPI_DIV] = imx_clk_divider2("qspi_div", "qspi_pre_div", base + 0xab80, 0, 6);
+ clks[IMX8MQ_CLK_USDHC1_DIV] = imx_clk_divider2("usdhc1_div", "usdhc1_pre_div", base + 0xac00, 0, 6);
+ clks[IMX8MQ_CLK_USDHC2_DIV] = imx_clk_divider2("usdhc2_div", "usdhc2_pre_div", base + 0xac80, 0, 6);
+ clks[IMX8MQ_CLK_I2C1_DIV] = imx_clk_divider2("i2c1_div", "i2c1_pre_div", base + 0xad00, 0, 6);
+ clks[IMX8MQ_CLK_I2C2_DIV] = imx_clk_divider2("i2c2_div", "i2c2_pre_div", base + 0xad80, 0, 6);
+ clks[IMX8MQ_CLK_I2C3_DIV] = imx_clk_divider2("i2c3_div", "i2c3_pre_div", base + 0xae00, 0, 6);
+ clks[IMX8MQ_CLK_I2C4_DIV] = imx_clk_divider2("i2c4_div", "i2c4_pre_div", base + 0xae80, 0, 6);
+ clks[IMX8MQ_CLK_UART1_DIV] = imx_clk_divider2("uart1_div", "uart1_pre_div", base + 0xaf00, 0, 6);
+ clks[IMX8MQ_CLK_UART2_DIV] = imx_clk_divider2("uart2_div", "uart2_pre_div", base + 0xaf80, 0, 6);
+ clks[IMX8MQ_CLK_UART3_DIV] = imx_clk_divider2("uart3_div", "uart3_pre_div", base + 0xb000, 0, 6);
+ clks[IMX8MQ_CLK_UART4_DIV] = imx_clk_divider2("uart4_div", "uart4_pre_div", base + 0xb080, 0, 6);
+ clks[IMX8MQ_CLK_USB_CORE_REF_DIV] = imx_clk_divider2("usb_core_ref_div", "usb_core_ref_pre_div", base + 0xb100, 0, 6);
+ clks[IMX8MQ_CLK_USB_PHY_REF_DIV] = imx_clk_divider2("usb_phy_ref_div", "usb_phy_ref_pre_div", base + 0xb180, 0, 6);
+ clks[IMX8MQ_CLK_ECSPI1_DIV] = imx_clk_divider2("ecspi1_div", "ecspi1_pre_div", base + 0xb280, 0, 6);
+ clks[IMX8MQ_CLK_ECSPI2_DIV] = imx_clk_divider2("ecspi2_div", "ecspi2_pre_div", base + 0xb300, 0, 6);
+ clks[IMX8MQ_CLK_PWM1_DIV] = imx_clk_divider2("pwm1_div", "pwm1_pre_div", base + 0xb380, 0, 6);
+ clks[IMX8MQ_CLK_PWM2_DIV] = imx_clk_divider2("pwm2_div", "pwm2_pre_div", base + 0xb400, 0, 6);
+ clks[IMX8MQ_CLK_PWM3_DIV] = imx_clk_divider2("pwm3_div", "pwm3_pre_div", base + 0xb480, 0, 6);
+ clks[IMX8MQ_CLK_PWM4_DIV] = imx_clk_divider2("pwm4_div", "pwm4_pre_div", base + 0xb500, 0, 6);
+ clks[IMX8MQ_CLK_GPT1_DIV] = imx_clk_divider2("gpt1_div", "gpt1_pre_div", base + 0xb580, 0, 6);
+ clks[IMX8MQ_CLK_WDOG_DIV] = imx_clk_divider2("wdog_div", "wdog_pre_div", base + 0xb900, 0, 6);
+ clks[IMX8MQ_CLK_WRCLK_DIV] = imx_clk_divider2("wrclk_div", "wrclk_pre_div", base + 0xb980, 0, 6);
+ clks[IMX8MQ_CLK_CLKO2_DIV] = imx_clk_divider2("clko2_div", "clko2_pre_div", base + 0xba80, 0, 6);
+ clks[IMX8MQ_CLK_PCIE2_CTRL_DIV] = imx_clk_divider2("pcie2_ctrl_div", "pcie2_ctrl_pre_div", base + 0xc000, 0, 6);
+ clks[IMX8MQ_CLK_PCIE2_PHY_DIV] = imx_clk_divider2("pcie2_phy_div", "pcie2_phy_pre_div", base + 0xc080, 0, 6);
+ clks[IMX8MQ_CLK_PCIE2_AUX_DIV] = imx_clk_divider2("pcie2_aux_div", "pcie2_aux_pre_div", base + 0xc100, 0, 6);
+ clks[IMX8MQ_CLK_ECSPI3_DIV] = imx_clk_divider2("ecspi3_div", "ecspi3_pre_div", base + 0xc180, 0, 6);
+
+ /*FIXME, the doc is not ready now */
+ clks[IMX8MQ_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1_div", base + 0x4070, 0);
+ clks[IMX8MQ_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2_div", base + 0x4080, 0);
+ clks[IMX8MQ_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3_div", base + 0x4090, 0);
+ clks[IMX8MQ_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi_div", base + 0x40a0, 0);
+ clks[IMX8MQ_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1_div", base + 0x4100, 0);
+ clks[IMX8MQ_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1_div", base + 0x4170, 0);
+ clks[IMX8MQ_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2_div", base + 0x4180, 0);
+ clks[IMX8MQ_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3_div", base + 0x4190, 0);
+ clks[IMX8MQ_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4_div", base + 0x41a0, 0);
+ clks[IMX8MQ_CLK_MU_ROOT] = imx_clk_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0);
+ clks[IMX8MQ_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0);
+ clks[IMX8MQ_CLK_PCIE1_ROOT] = imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl_div", base + 0x4250, 0);
+ clks[IMX8MQ_CLK_PCIE2_ROOT] = imx_clk_gate4("pcie2_root_clk", "pcie2_ctrl_div", base + 0x4640, 0);
+ clks[IMX8MQ_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1_div", base + 0x4280, 0);
+ clks[IMX8MQ_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2_div", base + 0x4290, 0);
+ clks[IMX8MQ_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3_div", base + 0x42a0, 0);
+ clks[IMX8MQ_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4_div", base + 0x42b0, 0);
+ clks[IMX8MQ_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi_div", base + 0x42f0, 0);
+ clks[IMX8MQ_CLK_RAWNAND_ROOT] = imx_clk_gate4("nand_root_clk", "nand_div", base + 0x4300, 0);
+ clks[IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate_shared("nand_usdhc_rawnand_clk", "nand_usdhc_bus_div", "nand_root_clk");
+ clks[IMX8MQ_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1_div", base + 0x4490, 0);
+ clks[IMX8MQ_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2_div", base + 0x44a0, 0);
+ clks[IMX8MQ_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3_div", base + 0x44b0, 0);
+ clks[IMX8MQ_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4_div", base + 0x44c0, 0);
+ clks[IMX8MQ_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref_div", base + 0x44d0, 0);
+ clks[IMX8MQ_CLK_USB2_CTRL_ROOT] = imx_clk_gate4("usb2_ctrl_root_clk", "usb_core_ref_div", base + 0x44e0, 0);
+ clks[IMX8MQ_CLK_USB1_PHY_ROOT] = imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref_div", base + 0x44f0, 0);
+ clks[IMX8MQ_CLK_USB2_PHY_ROOT] = imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref_div", base + 0x4500, 0);
+ clks[IMX8MQ_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1_div", base + 0x4510, 0);
+ clks[IMX8MQ_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2_div", base + 0x4520, 0);
+ clks[IMX8MQ_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog_div", base + 0x4530, 0);
+ clks[IMX8MQ_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog_div", base + 0x4540, 0);
+ clks[IMX8MQ_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog_div", base + 0x4550, 0);
+
+ clks[IMX8MQ_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc_25m", 1, 8);
+ clks[IMX8MQ_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt_div", 1, 4);
+
+ for (i = 0; i < IMX8MQ_CLK_END; i++)
+ if (IS_ERR(clks[i]))
+ pr_err("i.MX8mq clk %u register failed with %ld\n",
+ i, PTR_ERR(clks[i]));
+
+ clk_data.clks = clks;
+ clk_data.clk_num = ARRAY_SIZE(clks);
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+CLK_OF_DECLARE(imx8mq, "fsl,imx8mq-ccm", imx8mq_clocks_init);
diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c
new file mode 100644
index 000000000..951234367
--- /dev/null
+++ b/drivers/clk/imx/clk-sccg-pll.c
@@ -0,0 +1,242 @@
+/*
+ * Copyright 2017 NXP.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <malloc.h>
+#include <clock.h>
+#include <asm-generic/div64.h>
+
+#include "clk.h"
+
+/* PLL CFGs */
+#define PLL_CFG0 0x0
+#define PLL_CFG1 0x4
+#define PLL_CFG2 0x8
+
+#define PLL_DIVF1_SHIFT 13
+#define PLL_DIVF2_SHIFT 7
+#define PLL_DIVF_MASK 0x3f
+
+#define PLL_DIVR1_SHIFT 25
+#define PLL_DIVR2_SHIFT 19
+#define PLL_DIVR1_MASK 0x3
+#define PLL_DIVR2_MASK 0x3f
+#define PLL_REF_SHIFT 0
+#define PLL_REF_MASK 0x3
+
+#define PLL_LOCK 31
+#define PLL_PD 7
+
+#define OSC_25M 25000000
+#define OSC_27M 27000000
+
+struct clk_sccg_pll {
+ struct clk clk;
+ void __iomem *base;
+ const char *parent;
+};
+
+#define to_clk_sccg_pll(_clk) container_of(_clk, struct clk_sccg_pll, clk)
+
+static int clk_pll1_is_prepared(struct clk *clk)
+{
+ struct clk_sccg_pll *pll = to_clk_sccg_pll(clk);
+ u32 val;
+
+ val = readl(pll->base + PLL_CFG0);
+ return (val & (1 << PLL_PD)) ? 0 : 1;
+}
+
+static unsigned long clk_pll1_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_sccg_pll *pll = to_clk_sccg_pll(clk);
+ u32 val, divf;
+
+ val = readl(pll->base + PLL_CFG2);
+ divf = (val >> PLL_DIVF1_SHIFT) & PLL_DIVF_MASK;
+
+ return parent_rate * 2 * (divf + 1);
+}
+
+static long clk_pll1_round_rate(struct clk *clk, unsigned long rate,
+ unsigned long *prate)
+{
+ unsigned long parent_rate = *prate;
+ u32 div;
+
+ div = rate / (parent_rate * 2);
+
+ return parent_rate * div * 2;
+}
+
+static int clk_pll1_set_rate(struct clk *clk, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_sccg_pll *pll = to_clk_sccg_pll(clk);
+ u32 val;
+ u32 divf;
+
+ divf = rate / (parent_rate * 2);
+
+ val = readl(pll->base + PLL_CFG2);
+ val &= ~(PLL_DIVF_MASK << PLL_DIVF1_SHIFT);
+ val |= (divf - 1) << PLL_DIVF1_SHIFT;
+ writel(val, pll->base + PLL_CFG2);
+
+ /* FIXME: PLL lock check */
+
+ return 0;
+}
+
+static int clk_pll1_prepare(struct clk *clk)
+{
+ struct clk_sccg_pll *pll = to_clk_sccg_pll(clk);
+ u32 val;
+
+ val = readl(pll->base);
+ val &= ~(1 << PLL_PD);
+ writel(val, pll->base);
+
+ /* FIXME: PLL lock check */
+
+ return 0;
+}
+
+static void clk_pll1_unprepare(struct clk *clk)
+{
+ struct clk_sccg_pll *pll = to_clk_sccg_pll(clk);
+ u32 val;
+printf("%s %p\n", __func__, pll);
+ val = readl(pll->base);
+ val |= (1 << PLL_PD);
+ writel(val, pll->base);
+printf("fuschi\n");
+}
+
+static unsigned long clk_pll2_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_sccg_pll *pll = to_clk_sccg_pll(clk);
+ u32 val, ref, divr1, divf1, divr2, divf2;
+ u64 temp64;
+
+ val = readl(pll->base + PLL_CFG0);
+ switch ((val >> PLL_REF_SHIFT) & PLL_REF_MASK) {
+ case 0:
+ ref = OSC_25M;
+ break;
+ case 1:
+ ref = OSC_27M;
+ break;
+ default:
+ ref = OSC_25M;
+ break;
+ }
+
+ val = readl(pll->base + PLL_CFG2);
+ divr1 = (val >> PLL_DIVR1_SHIFT) & PLL_DIVR1_MASK;
+ divr2 = (val >> PLL_DIVR2_SHIFT) & PLL_DIVR2_MASK;
+ divf1 = (val >> PLL_DIVF1_SHIFT) & PLL_DIVF_MASK;
+ divf2 = (val >> PLL_DIVF2_SHIFT) & PLL_DIVF_MASK;
+
+ temp64 = ref * 2;
+ temp64 *= (divf1 + 1) * (divf2 + 1);
+
+ do_div(temp64, (divr1 + 1) * (divr2 + 1));
+
+ return (unsigned long)temp64;
+}
+
+static long clk_pll2_round_rate(struct clk *clk, unsigned long rate,
+ unsigned long *prate)
+{
+ u32 div;
+ unsigned long parent_rate = *prate;
+
+ div = rate / (parent_rate);
+
+ return parent_rate * div;
+}
+
+static int clk_pll2_set_rate(struct clk *clk, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u32 val;
+ u32 divf;
+ struct clk_sccg_pll *pll = to_clk_sccg_pll(clk);
+
+ divf = rate / (parent_rate);
+
+ val = readl(pll->base + PLL_CFG2);
+ val &= ~(PLL_DIVF_MASK << PLL_DIVF2_SHIFT);
+ val |= (divf - 1) << PLL_DIVF2_SHIFT;
+ writel(val, pll->base + PLL_CFG2);
+
+ /* FIXME: PLL lock check */
+
+ return 0;
+}
+
+static const struct clk_ops clk_sccg_pll1_ops = {
+ .is_enabled = clk_pll1_is_prepared,
+ .recalc_rate = clk_pll1_recalc_rate,
+ .round_rate = clk_pll1_round_rate,
+ .set_rate = clk_pll1_set_rate,
+};
+
+static const struct clk_ops clk_sccg_pll2_ops = {
+ .enable = clk_pll1_prepare,
+ .disable = clk_pll1_unprepare,
+ .recalc_rate = clk_pll2_recalc_rate,
+ .round_rate = clk_pll2_round_rate,
+ .set_rate = clk_pll2_set_rate,
+};
+
+struct clk *imx_clk_sccg_pll(const char *name, const char *parent_name,
+ void __iomem *base, enum imx_sccg_pll_type pll_type)
+{
+ struct clk_sccg_pll *pll;
+ int ret;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pll->base = base;
+ pll->clk.name = name;
+ switch (pll_type) {
+ case SCCG_PLL1:
+ pll->clk.ops = &clk_sccg_pll1_ops;
+ break;
+ case SCCG_PLL2:
+ pll->clk.ops = &clk_sccg_pll2_ops;
+ break;
+ }
+
+ pll->parent = parent_name;
+ pll->clk.parent_names = &pll->parent;
+ pll->clk.num_parents = 1;
+
+ ret = clk_register(&pll->clk);
+ if (ret) {
+ free(pll);
+ return ERR_PTR(ret);
+ }
+
+ return &pll->clk;
+}
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 71c6f459a..c6ec0fc40 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -10,6 +10,13 @@ static inline struct clk *imx_clk_divider(const char *name, const char *parent,
return clk_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT);
}
+static inline struct clk *imx_clk_divider_flags(const char *name,
+ const char *parent, void __iomem *reg, u8 shift, u8 width,
+ unsigned long flags)
+{
+ return clk_divider(name, parent, reg, shift, width, flags);
+}
+
static inline struct clk *imx_clk_divider_np(const char *name, const char *parent,
void __iomem *reg, u8 shift, u8 width)
{
@@ -44,6 +51,14 @@ static inline struct clk *imx_clk_mux_flags(const char *name, void __iomem *reg,
return clk_mux(name, reg, shift, width, parents, num_parents, flags);
}
+static inline struct clk *imx_clk_mux2_flags(const char *name,
+ void __iomem *reg, u8 shift, u8 width, const char **parents,
+ int num_parents, unsigned long flags)
+{
+ return clk_mux(name, reg, shift, width, parents, num_parents,
+ flags | CLK_OPS_PARENT_ENABLE);
+}
+
static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
u8 shift, u8 width, const char **parents, u8 num_parents)
{
@@ -133,6 +148,18 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
const char *parent, void __iomem *base,
u32 div_mask);
+struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
+ void __iomem *base);
+
+enum imx_sccg_pll_type {
+ SCCG_PLL1,
+ SCCG_PLL2,
+};
+
+struct clk *imx_clk_sccg_pll(const char *name, const char *parent_name,
+ void __iomem *base,
+ enum imx_sccg_pll_type pll_type);
+
struct clk *imx_clk_pfd(const char *name, const char *parent,
void __iomem *reg, u8 idx);
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 11/48] serial: i.MX: Add i.MX8 support
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (9 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 10/48] clock: Add i.MX8MQ clock driver Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 12/48] mmc: i.MX esdhc: " Andrey Smirnov
` (36 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/serial/serial_imx.c | 5 ++++-
include/serial/imx-uart.h | 5 +++++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c
index c8af995aa..09341af87 100644
--- a/drivers/serial/serial_imx.c
+++ b/drivers/serial/serial_imx.c
@@ -281,9 +281,12 @@ static __maybe_unused struct of_device_id imx_serial_dt_ids[] = {
}, {
.compatible = "fsl,imx6ul-uart",
.data = &imx21_data,
- }, {
+ }, {
.compatible = "fsl,imx7d-uart",
.data = &imx21_data,
+ }, {
+ .compatible = "fsl,imx8mq-uart",
+ .data = &imx21_data,
}, {
/* sentinel */
}
diff --git a/include/serial/imx-uart.h b/include/serial/imx-uart.h
index 9cab32f35..c23606569 100644
--- a/include/serial/imx-uart.h
+++ b/include/serial/imx-uart.h
@@ -180,6 +180,11 @@ static inline void imx7_uart_setup(void __iomem *uartbase)
imx_uart_setup(uartbase, 24000000);
}
+static inline void imx8mq_uart_setup(void __iomem *uartbase)
+{
+ imx_uart_setup(uartbase, 25000000);
+}
+
static inline void imx_uart_putc(void *base, int c)
{
if (!(readl(base + UCR1) & UCR1_UARTEN))
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 12/48] mmc: i.MX esdhc: Add i.MX8 support
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (10 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 11/48] serial: i.MX: Add i.MX8 support Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 13/48] gpio: i.MX: Add i.MX8mq support Andrey Smirnov
` (35 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/mci/imx-esdhc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index 8929901d4..c4daa9d12 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -728,6 +728,7 @@ static __maybe_unused struct of_device_id fsl_esdhc_compatible[] = {
{ .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data },
{ .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data },
{ .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data },
+ { .compatible = "fsl,imx8mq-usdhc", .data = &usdhc_imx6sx_data },
{ /* sentinel */ }
};
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 13/48] gpio: i.MX: Add i.MX8mq support
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (11 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 12/48] mmc: i.MX esdhc: " Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 14/48] ARM: i.MX: ocotp: Add i.MX8MQ support Andrey Smirnov
` (34 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/gpio/gpio-imx.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpio/gpio-imx.c b/drivers/gpio/gpio-imx.c
index d8bcea223..d618e6011 100644
--- a/drivers/gpio/gpio-imx.c
+++ b/drivers/gpio/gpio-imx.c
@@ -190,6 +190,9 @@ static __maybe_unused struct of_device_id imx_gpio_dt_ids[] = {
}, {
.compatible = "fsl,imx6q-gpio",
.data = ®s_imx31,
+ }, {
+ .compatible = "fsl,imx8mq-gpio",
+ .data = ®s_imx31,
}, {
/* sentinel */
}
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 14/48] ARM: i.MX: ocotp: Add i.MX8MQ support
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (12 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 13/48] gpio: i.MX: Add i.MX8mq support Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 15/48] ARM: i.MX: Split shared CCM code into a separate file Andrey Smirnov
` (33 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/Kconfig | 2 +-
arch/arm/mach-imx/ocotp.c | 10 ++++++++++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 85143bd26..020b6fa05 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -736,7 +736,7 @@ config IMX_IIM_FUSE_BLOW
config IMX_OCOTP
tristate "i.MX6 On Chip OTP controller"
- depends on ARCH_IMX6 || ARCH_VF610
+ depends on ARCH_IMX6 || ARCH_VF610 || ARCH_IMX8MQ
depends on OFDEVICE
help
This adds support for the i.MX6 On-Chip OTP controller. Currently the
diff --git a/arch/arm/mach-imx/ocotp.c b/arch/arm/mach-imx/ocotp.c
index 99b365aad..09f8cf4ff 100644
--- a/arch/arm/mach-imx/ocotp.c
+++ b/arch/arm/mach-imx/ocotp.c
@@ -584,6 +584,13 @@ static struct imx_ocotp_data vf610_ocotp_data = {
.mac_offsets = { MAC_OFFSET_0, MAC_OFFSET_1 },
};
+static struct imx_ocotp_data imx8mq_ocotp_data = {
+ .num_regs = 2048,
+ .addr_to_offset = imx6sl_addr_to_offset,
+ .mac_offsets_num = 1,
+ .mac_offsets = { 0x90 },
+};
+
static __maybe_unused struct of_device_id imx_ocotp_dt_ids[] = {
{
.compatible = "fsl,imx6q-ocotp",
@@ -597,6 +604,9 @@ static __maybe_unused struct of_device_id imx_ocotp_dt_ids[] = {
}, {
.compatible = "fsl,imx6ul-ocotp",
.data = &imx6q_ocotp_data,
+ }, {
+ .compatible = "fsl,imx8mq-ocotp",
+ .data = &imx8mq_ocotp_data,
}, {
.compatible = "fsl,vf610-ocotp",
.data = &vf610_ocotp_data,
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 15/48] ARM: i.MX: Split shared CCM code into a separate file
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (13 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 14/48] ARM: i.MX: ocotp: Add i.MX8MQ support Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 16/48] ARM: i.MX: Add IOMUX pad constants for i.MX8 Andrey Smirnov
` (32 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Both i.MX8 and i.MX7 have similar CCMs, so move any code that can be
share into a separate file.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/include/mach/ccm.h | 20 +++++++++++++++++++
.../arm/mach-imx/include/mach/imx7-ccm-regs.h | 16 +--------------
2 files changed, 21 insertions(+), 15 deletions(-)
create mode 100644 arch/arm/mach-imx/include/mach/ccm.h
diff --git a/arch/arm/mach-imx/include/mach/ccm.h b/arch/arm/mach-imx/include/mach/ccm.h
new file mode 100644
index 000000000..32254a85b
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/ccm.h
@@ -0,0 +1,20 @@
+#ifndef __IMX_CCM_H__
+
+/* 0 <= n <= 190 */
+#define CCM_CCGRn_SET(n) (0x4004 + 16 * (n))
+#define CCM_CCGRn_CLR(n) (0x4008 + 16 * (n))
+
+/* 0 <= n <= 120 */
+#define CCM_TARGET_ROOTn(n) (0x8000 + 128 * (n))
+
+#define CCM_TARGET_ROOTn_MUX(x) ((x) << 24)
+#define CCM_TARGET_ROOTn_ENABLE BIT(28)
+
+
+#define CCM_CCGR_SETTINGn(n, s) ((s) << ((n) * 4))
+#define CCM_CCGR_SETTINGn_NOT_NEEDED(n) CCM_CCGR_SETTINGn(n, 0b00)
+#define CCM_CCGR_SETTINGn_NEEDED_RUN(n) CCM_CCGR_SETTINGn(n, 0b01)
+#define CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) CCM_CCGR_SETTINGn(n, 0b10)
+#define CCM_CCGR_SETTINGn_NEEDED(n) CCM_CCGR_SETTINGn(n, 0b11)
+
+#endif
\ No newline at end of file
diff --git a/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h
index 97fe240fc..43b9425df 100644
--- a/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx7-ccm-regs.h
@@ -1,25 +1,11 @@
#ifndef __MACH_IMX7_CCM_REGS_H__
#define __MACH_IMX7_CCM_REGS_H__
-/* 0 <= n <= 190 */
-#define CCM_CCGRn_SET(n) (0x4004 + 16 * (n))
-#define CCM_CCGRn_CLR(n) (0x4008 + 16 * (n))
+#include "ccm.h"
#define CCM_CCGR_UART1 148
#define CCM_CCGR_UART2 149
-#define CCM_CCGR_SETTINGn(n, s) ((s) << ((n) * 4))
-#define CCM_CCGR_SETTINGn_NOT_NEEDED(n) CCM_CCGR_SETTINGn(n, 0b00)
-#define CCM_CCGR_SETTINGn_NEEDED_RUN(n) CCM_CCGR_SETTINGn(n, 0b01)
-#define CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) CCM_CCGR_SETTINGn(n, 0b10)
-#define CCM_CCGR_SETTINGn_NEEDED(n) CCM_CCGR_SETTINGn(n, 0b11)
-
-/* 0 <= n <= 120 */
-#define CCM_TARGET_ROOTn(n) (0x8000 + 128 * (n))
-
-#define CCM_TARGET_ROOTn_MUX(x) ((x) << 24)
-#define CCM_TARGET_ROOTn_ENABLE BIT(28)
-
#define CLOCK_ROOT_INDEX(x) (((x) - 0x8000) / 128)
/*
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 16/48] ARM: i.MX: Add IOMUX pad constants for i.MX8
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (14 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 15/48] ARM: i.MX: Split shared CCM code into a separate file Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 17/48] scripts/imx: Add trivial i.MX8 support Andrey Smirnov
` (31 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Ported from U-Boot
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/include/mach/iomux-mx8.h | 645 +++++++++++++++++++++
1 file changed, 645 insertions(+)
create mode 100644 arch/arm/mach-imx/include/mach/iomux-mx8.h
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8.h b/arch/arm/mach-imx/include/mach/iomux-mx8.h
new file mode 100644
index 000000000..1caa2235b
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/iomux-mx8.h
@@ -0,0 +1,645 @@
+/*
+ * Copyright (C) 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MACH_IOMUX_IMX8MQ_H__
+#define __MACH_IOMUX_IMX8MQ_H__
+
+#include <mach/iomux-v3.h>
+
+#define PAD_CTL_DSE_3P3V_45_OHM 0b110
+
+enum {
+ IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO00__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO00__CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO00__JTAG_FAIL = IOMUX_PAD(0x0290, 0x0028, 7, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO01__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO01__CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO01__JTAG_ACTIVE = IOMUX_PAD(0x0294, 0x002C, 7, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO02__JTAG_DE_B = IOMUX_PAD(0x0298, 0x0030, 7, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO03__USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO03__XTALOSC_XTAL_OK = IOMUX_PAD(0x029C, 0x0034, 6, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO03__JTAG_DONE = IOMUX_PAD(0x029C, 0x0034, 7, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO04__XTALOSC_XTAL_OK_1V = IOMUX_PAD(0x02A0, 0x0038, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO05__ARM_PLATFORM_CM4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO05__CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO05__SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO06__ENET_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO06__USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO06__CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO07__ENET_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO07__USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO07__CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO08__ENET_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO08__USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO08__CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO09__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO09__SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO09__CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO10__USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO11__USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO11__CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0),
+
+ IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO12__USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO12__SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT0 = IOMUX_PAD(0x02C0, 0x0058, 7, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO13__USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO13__PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT1 = IOMUX_PAD(0x02C4, 0x005C, 7, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO14__USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO14__PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO14__CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT2 = IOMUX_PAD(0x02C8, 0x0060, 7, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO15__USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO15__PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO15__CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0),
+ IMX8MQ_PAD_GPIO1_IO15__CSU_CSU_INT_DEB = IOMUX_PAD(0x02CC, 0x0064, 7, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_MDC__GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0),
+ IMX8MQ_PAD_ENET_MDIO__GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_TD3__GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_TD2__ENET_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_TD2__GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_TD1__GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_TD0__GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_TX_CTL__ENET_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_TX_CTL__GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_TXC__ENET_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_TXC__GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_RXC__ENET_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_CLK__GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_CMD__GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_DATA0__GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_DATA1__GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_DATA2__GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_DATA3__GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_DATA4__GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_DATA5__GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_DATA6__GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_DATA7__GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_RESET_B__USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD1_STROBE__GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_CLK__GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_CMD__GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_DATA0__GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_DATA1__GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_DATA1__CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_DATA2__GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_DATA2__CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_DATA3__GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_DATA3__SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_RESET_B__SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SD2_WP__USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SD2_WP__GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_ALE__GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CE0_B__GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CE1_B__QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_CE2_B__RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CE2_B__QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CE2_B__GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_CE3_B__RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CE3_B__QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CLE__QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA00__GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA04__QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA05__QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA06__QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA07__QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DQS__QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_DQS__GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_RE_B__QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI5_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0),
+ IMX8MQ_PAD_SAI5_RXFS__SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI5_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0),
+ IMX8MQ_PAD_SAI5_RXC__SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI5_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD0__SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI5_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD1__SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI5_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0),
+ IMX8MQ_PAD_SAI5_RXD2__SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI5_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0),
+ IMX8MQ_PAD_SAI5_RXD3__SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI5_MCLK__SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0),
+ IMX8MQ_PAD_SAI5_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0),
+ IMX8MQ_PAD_SAI5_MCLK__SAI4_MCLK = IOMUX_PAD(0x03C0, 0x0158, 2, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI5_MCLK__SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXFS__SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0),
+ IMX8MQ_PAD_SAI1_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0),
+ IMX8MQ_PAD_SAI1_RXFS__ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXFS__GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXC__SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0),
+ IMX8MQ_PAD_SAI1_RXC__ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXC__GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXD0__SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD0__SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0),
+ IMX8MQ_PAD_SAI1_RXD0__ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD0__GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD0__SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXD1__SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD1__SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0),
+ IMX8MQ_PAD_SAI1_RXD1__ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD1__GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD1__SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXD2__SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD2__SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0),
+ IMX8MQ_PAD_SAI1_RXD2__ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD2__GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD2__SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXD3__SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x04E0, 1, 0),
+ IMX8MQ_PAD_SAI1_RXD3__SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD3__ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD3__GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD3__SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXD4__SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD4__SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD4__SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD4__ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD4__GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD4__SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0),
+ IMX8MQ_PAD_SAI1_RXD5__ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD5__GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD5__SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXD6__SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD6__SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD6__SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD6__ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD6__GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD6__SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_RXD7__SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD7__SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0),
+ IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD7__ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD7__GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_RXD7__SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXFS__SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0),
+ IMX8MQ_PAD_SAI1_TXFS__SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0),
+ IMX8MQ_PAD_SAI1_TXFS__ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXC__SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0),
+ IMX8MQ_PAD_SAI1_TXC__SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0),
+ IMX8MQ_PAD_SAI1_TXC__ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXD0__SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD0__ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD0__GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD0__SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXD1__SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD1__SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD1__ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD1__GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD1__SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXD2__SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD2__SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD2__ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD2__GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD2__SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXD3__SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD3__SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD3__ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD3__GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD3__SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXD4__SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD4__SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0),
+ IMX8MQ_PAD_SAI1_TXD4__SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0),
+ IMX8MQ_PAD_SAI1_TXD4__ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD4__GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD4__SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXD5__SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD5__SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0),
+ IMX8MQ_PAD_SAI1_TXD5__SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD5__ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD5__GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD5__SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXD6__SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD6__SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0),
+ IMX8MQ_PAD_SAI1_TXD6__SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0),
+ IMX8MQ_PAD_SAI1_TXD6__ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD6__GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD6__SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_TXD7__SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD7__SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0),
+ IMX8MQ_PAD_SAI1_TXD7__ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD7__GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_TXD7__SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI1_MCLK__SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI1_MCLK__SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0),
+ IMX8MQ_PAD_SAI1_MCLK__SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0),
+ IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI2_RXFS__SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_RXFS__SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0),
+ IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI2_RXC__SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_RXC__SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0),
+ IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI2_RXD0__SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_RXD0__SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_RXD0__GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI2_TXFS__SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_TXFS__SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_TXFS__GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_TXC__SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_TXC__GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI2_TXD0__SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_TXD0__SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_TXD0__GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI2_MCLK__SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI2_MCLK__SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0),
+ IMX8MQ_PAD_SAI2_MCLK__GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI3_RXFS__SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_RXFS__GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_RXFS__SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0),
+ IMX8MQ_PAD_SAI3_RXFS__GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI3_RXC__SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_RXC__GPT1_CAPTURE2 = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_RXC__SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0),
+ IMX8MQ_PAD_SAI3_RXC__GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI3_RXD__SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_RXD__SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0),
+ IMX8MQ_PAD_SAI3_RXD__GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI3_TXFS__SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_TXFS__GPT1_CLK = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_TXFS__SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0),
+ IMX8MQ_PAD_SAI3_TXFS__GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI3_TXC__SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_TXC__GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_TXC__SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0),
+ IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI3_TXD__SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_TXD__GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_TXD__SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0),
+ IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SAI3_MCLK__SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_MCLK__PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SAI3_MCLK__SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0),
+ IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SPDIF_TX__SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SPDIF_TX__PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SPDIF_RX__SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SPDIF_RX__PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_SPDIF_EXT_CLK__SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_SPDIF_EXT_CLK__PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_SPDIF_EXT_CLK__GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ECSPI1_SCLK__UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0),
+ IMX8MQ_PAD_ECSPI1_SCLK__GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ECSPI1_MOSI__UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0),
+ IMX8MQ_PAD_ECSPI1_MOSI__GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0),
+ IMX8MQ_PAD_ECSPI1_MISO__GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ECSPI1_SS0__UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0),
+ IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0),
+ IMX8MQ_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0),
+ IMX8MQ_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0),
+ IMX8MQ_PAD_ECSPI2_MISO__GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0),
+ IMX8MQ_PAD_ECSPI2_SS0__GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C1_SCL__ENET_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C1_SDA__ENET_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0),
+ IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C2_SCL__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C2_SDA__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C3_SCL__PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C3_SCL__GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C3_SDA__PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C3_SDA__GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C4_SCL__PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C4_SCL__PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0),
+ IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C4_SDA__PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_I2C4_SDA__PCIE2_CLKREQ_B = IOMUX_PAD(0x0498, 0x0230, 2, 0x0528, 0, 0),
+ IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_UART1_RXD__UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0),
+ IMX8MQ_PAD_UART1_RXD__ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_UART1_RXD__GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_UART1_TXD__UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_UART1_TXD__ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_UART1_TXD__GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_UART2_RXD__UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0),
+ IMX8MQ_PAD_UART2_RXD__ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_UART2_RXD__GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_UART2_TXD__UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_UART2_TXD__ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0),
+ IMX8MQ_PAD_UART2_TXD__GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_UART3_RXD__UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0),
+ IMX8MQ_PAD_UART3_RXD__UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0),
+ IMX8MQ_PAD_UART3_RXD__GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_UART3_TXD__UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_UART3_TXD__UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0),
+ IMX8MQ_PAD_UART3_TXD__GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_UART4_RXD__UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0),
+ IMX8MQ_PAD_UART4_RXD__UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0),
+ IMX8MQ_PAD_UART4_RXD__PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0),
+ IMX8MQ_PAD_UART4_RXD__GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0),
+
+ IMX8MQ_PAD_UART4_TXD__UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0),
+ IMX8MQ_PAD_UART4_TXD__UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0),
+ IMX8MQ_PAD_UART4_TXD__PCIE2_CLKREQ_B = IOMUX_PAD(0x04B8, 0x0250, 2, 0x0528, 1, 0),
+ IMX8MQ_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0),
+};
+
+static inline void mx8_setup_pad(void __iomem *iomux, iomux_v3_cfg_t pad)
+{
+ unsigned int flags = 0;
+ uint32_t mode = IOMUX_MODE(pad);
+
+ if (mode & IOMUX_CONFIG_LPSR) {
+ mode &= ~IOMUX_CONFIG_LPSR;
+ flags = ZERO_OFFSET_VALID | IMX7_PINMUX_LPSR;
+ }
+
+ iomux_v3_setup_pad(iomux, flags,
+ IOMUX_CTRL_OFS(pad),
+ IOMUX_PAD_CTRL_OFS(pad),
+ IOMUX_SEL_INPUT_OFS(pad),
+ mode,
+ IOMUX_PAD_CTRL(pad),
+ IOMUX_SEL_INPUT(pad));
+}
+
+#endif
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 17/48] scripts/imx: Add trivial i.MX8 support
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (15 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 16/48] ARM: i.MX: Add IOMUX pad constants for i.MX8 Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 18/48] ARM: i.MX: Add basic CCM constants for i.MX8 Andrey Smirnov
` (30 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
scripts/imx/imx.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/scripts/imx/imx.c b/scripts/imx/imx.c
index fb6ac001e..d29e57f3d 100644
--- a/scripts/imx/imx.c
+++ b/scripts/imx/imx.c
@@ -233,6 +233,7 @@ static struct soc_type socs[] = {
{ .name = "imx6", .header_version = 2, .cpu_type = IMX_CPU_IMX6 },
{ .name = "imx7", .header_version = 2, .cpu_type = IMX_CPU_IMX7 },
{ .name = "vf610", .header_version = 2, .cpu_type = IMX_CPU_VF610 },
+ { .name = "imx8", .header_version = 2, .cpu_type = IMX_CPU_IMX8MQ },
};
static int do_soc(struct config_data *data, int argc, char *argv[])
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 18/48] ARM: i.MX: Add basic CCM constants for i.MX8
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (16 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 17/48] scripts/imx: Add trivial i.MX8 support Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 19/48] ARM: Add constants and helpers for system counter interface Andrey Smirnov
` (29 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/include/mach/imx8-ccm-regs.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
create mode 100644 arch/arm/mach-imx/include/mach/imx8-ccm-regs.h
diff --git a/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h
new file mode 100644
index 000000000..93b584ebe
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx8-ccm-regs.h
@@ -0,0 +1,15 @@
+#ifndef __MACH_IMX8_CCM_REGS_H__
+#define __MACH_IMX8_CCM_REGS_H__
+
+#include "ccm.h"
+
+#define CCM_CCGR_UART1 73
+
+/*
+ * Taken from "Table 5-1. Clock Root Table" from i.MX8M Quad
+ * Applications Processor Reference Manual
+ */
+#define UART1_CLK_ROOT 94
+#define UART1_CLK_ROOT__25M_REF_CLK CCM_TARGET_ROOTn_MUX(0b000)
+
+#endif
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 19/48] ARM: Add constants and helpers for system counter interface
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (17 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 18/48] ARM: i.MX: Add basic CCM constants for i.MX8 Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 20/48] clocksource: armv8-timer: Convert explicit assembly into helpers Andrey Smirnov
` (28 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Add constants and helpers for system counter interface as can be found
in section "I1.3 Generic Timer registers" of "ARM Architecture
Reference Manual ARMv8, for ARMv8-A architecture"
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/include/asm/syscounter.h | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 arch/arm/include/asm/syscounter.h
diff --git a/arch/arm/include/asm/syscounter.h b/arch/arm/include/asm/syscounter.h
new file mode 100644
index 000000000..a644cfaad
--- /dev/null
+++ b/arch/arm/include/asm/syscounter.h
@@ -0,0 +1,24 @@
+#ifndef _ASM_SYSCNT_H_
+#define _ASM_SYSCNT_H_
+
+#include <io.h>
+
+#define SYSCNT_CNTCR 0x0000
+#define SYSCNT_CNTCR_EN BIT(0)
+#define SYSCNT_CNTCR_HDBG BIT(1)
+#define SYSCNT_CNTCR_FCREQ(n) BIT(8 + (n))
+
+#define SYSCNT_CNTFID(n) (0x0020 + 4 * (n))
+
+static inline void syscnt_enable(void __iomem *syscnt)
+{
+ writel(SYSCNT_CNTCR_EN | SYSCNT_CNTCR_HDBG | SYSCNT_CNTCR_FCREQ(0),
+ syscnt + SYSCNT_CNTCR);
+}
+
+static inline u32 syscnt_get_cntfrq(void __iomem *syscnt)
+{
+ return readl(syscnt + SYSCNT_CNTFID(0));
+}
+
+#endif
\ No newline at end of file
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 20/48] clocksource: armv8-timer: Convert explicit assembly into helpers
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (18 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 19/48] ARM: Add constants and helpers for system counter interface Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 21/48] ARM: i.MX8: Initialize system counter Andrey Smirnov
` (27 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Move inline assembly related to querying and counter value as well as
getting and setting counter frequency register into asm/system.h as
well as converting it inot helper functions. This is done to make the
code availible to other parts of the system.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/include/asm/system.h | 24 ++++++++++++++++++++++++
drivers/clocksource/armv8-timer.c | 13 ++-----------
2 files changed, 26 insertions(+), 11 deletions(-)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 57c76186b..5cf828ea3 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -77,6 +77,30 @@ static inline unsigned long read_mpidr(void)
return val;
}
+
+static inline void set_cntfrq(unsigned long cntfrq)
+{
+ asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
+}
+
+static inline unsigned long get_cntfrq(void)
+{
+ unsigned long cntfrq;
+
+ asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
+ return cntfrq;
+}
+
+static inline unsigned long get_cntpct(void)
+{
+ unsigned long cntpct;
+
+ isb();
+ asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+
+ return cntpct;
+}
+
#endif
static inline unsigned int get_cr(void)
{
diff --git a/drivers/clocksource/armv8-timer.c b/drivers/clocksource/armv8-timer.c
index 57b0b694c..c5306dcd2 100644
--- a/drivers/clocksource/armv8-timer.c
+++ b/drivers/clocksource/armv8-timer.c
@@ -22,12 +22,7 @@
uint64_t armv8_clocksource_read(void)
{
- unsigned long cntpct;
-
- isb();
- asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
-
- return cntpct;
+ return get_cntpct();
}
static struct clocksource cs = {
@@ -38,11 +33,7 @@ static struct clocksource cs = {
static int armv8_timer_probe(struct device_d *dev)
{
- unsigned long cntfrq;
-
- asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
-
- cs.mult = clocksource_hz2mult(cntfrq, cs.shift);
+ cs.mult = clocksource_hz2mult(get_cntfrq(), cs.shift);
return init_clock(&cs);
}
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 21/48] ARM: i.MX8: Initialize system counter
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (19 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 20/48] clocksource: armv8-timer: Convert explicit assembly into helpers Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 22/48] ARM: i.MX: boot: Fix address casting on 64-bit platforms Andrey Smirnov
` (26 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Add code to properly initialize system counter, so it would be posible
to get accurate time delays.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/imx8mq.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/mach-imx/imx8mq.c b/arch/arm/mach-imx/imx8mq.c
index a9bd9f444..6b2a85a55 100644
--- a/arch/arm/mach-imx/imx8mq.c
+++ b/arch/arm/mach-imx/imx8mq.c
@@ -14,6 +14,8 @@
#include <init.h>
#include <common.h>
#include <io.h>
+#include <asm/syscounter.h>
+#include <asm/system.h>
#include <mach/generic.h>
#include <mach/revision.h>
#include <mach/imx8mq-regs.h>
@@ -58,6 +60,23 @@ static void imx8mq_silicon_revision(void)
imx_set_silicon_revision(cputypestr, reg);
}
+static int imx8mq_init_syscnt_frequency(void)
+{
+ void __iomem *syscnt = IOMEM(MX8MQ_SYSCNT_CTRL_BASE_ADDR);
+ /*
+ * Update with accurate clock frequency
+ */
+ set_cntfrq(syscnt_get_cntfrq(syscnt));
+ syscnt_enable(syscnt);
+
+ return 0;
+}
+/*
+ * This call needs to happen before timer driver gets probed and
+ * requests its update frequency via cntfrq_el0
+ */
+core_initcall(imx8mq_init_syscnt_frequency);
+
int imx8mq_init(void)
{
imx8mq_silicon_revision();
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 22/48] ARM: i.MX: boot: Fix address casting on 64-bit platforms
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (20 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 21/48] ARM: i.MX8: Initialize system counter Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 23/48] ARM: boot: Add trivial i.MX8 support Andrey Smirnov
` (25 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Add an intermediary casting step in order to avoid casting 32-bit
integer to 64-bit pointer on 64-bit platforms.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/boot.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
index 22cf08e6a..11105a148 100644
--- a/arch/arm/mach-imx/boot.c
+++ b/arch/arm/mach-imx/boot.c
@@ -485,7 +485,8 @@ void imx7_get_boot_source(enum bootsource *src, int *instance)
*/
const struct imx_boot_sw_info *info;
- info = (const void *)readl(IMX_BOOT_SW_INFO_POINTER_ADDR);
+ info = (const void *)(unsigned long)
+ readl(IMX_BOOT_SW_INFO_POINTER_ADDR);
if (info->boot_device_type == IMX_BOOT_SW_INFO_BDT_SD) {
*src = BOOTSOURCE_MMC;
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 23/48] ARM: boot: Add trivial i.MX8 support
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (21 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 22/48] ARM: i.MX: boot: Fix address casting on 64-bit platforms Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 24/48] ARM: i.MX: xload-esdhc: Rework to make code be less i.MX6-specific Andrey Smirnov
` (24 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
It appears that boot sources for i.MX8 are just a subset of those of
i.MX7 and both can be handled by the same code.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/boot.c | 5 +++++
arch/arm/mach-imx/include/mach/generic.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
index 11105a148..ab25f75b2 100644
--- a/arch/arm/mach-imx/boot.c
+++ b/arch/arm/mach-imx/boot.c
@@ -624,3 +624,8 @@ void vf610_boot_save_loc(void)
{
imx_boot_save_loc(vf610_get_boot_source);
}
+
+void imx8_get_boot_source(enum bootsource *src, int *instance)
+ __alias(imx7_get_boot_source);
+
+void imx8_boot_save_loc(void) __alias(imx7_boot_save_loc);
diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h
index 204bd40f7..ccb04078c 100644
--- a/arch/arm/mach-imx/include/mach/generic.h
+++ b/arch/arm/mach-imx/include/mach/generic.h
@@ -16,6 +16,7 @@ void imx53_boot_save_loc(void);
void imx6_boot_save_loc(void);
void imx7_boot_save_loc(void);
void vf610_boot_save_loc(void);
+void imx8_boot_save_loc(void);
void imx25_get_boot_source(enum bootsource *src, int *instance);
void imx35_get_boot_source(enum bootsource *src, int *instance);
@@ -24,6 +25,7 @@ void imx53_get_boot_source(enum bootsource *src, int *instance);
void imx6_get_boot_source(enum bootsource *src, int *instance);
void imx7_get_boot_source(enum bootsource *src, int *instance);
void vf610_get_boot_source(enum bootsource *src, int *instance);
+void imx8_get_boot_source(enum bootsource *src, int *instance);
int imx1_init(void);
int imx21_init(void);
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 24/48] ARM: i.MX: xload-esdhc: Rework to make code be less i.MX6-specific
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (22 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 23/48] ARM: boot: Add trivial i.MX8 support Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 25/48] ARM: i.MX: xload-esdhc: Allow custom buffer address, device offset Andrey Smirnov
` (23 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Convert imx6_esdhc_start_image() into a generic esdhc_start_image() by
making accept already filled "struct esdhc" as well as use
esdhc_read_blocks().
With that change, create new imx6_esdhc_start_image() whose sole task
is to properly fill a struct esdhc with appropriate offset and to pass
it on to esdhc_start_image().
Both changes are made with a goal of simplifying adding support of new
SoC in mind (see following commits adding support for i.MX8 as example).
NOTE: This commit does not re-implement imx6_esdhc_load_image(),
instead opting for dropping it, due to lack of any users in the
codebase.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/include/mach/xload.h | 1 -
arch/arm/mach-imx/xload-esdhc.c | 87 ++++++++++++--------------
2 files changed, 41 insertions(+), 47 deletions(-)
diff --git a/arch/arm/mach-imx/include/mach/xload.h b/arch/arm/mach-imx/include/mach/xload.h
index 3898d664e..4e38ac7e2 100644
--- a/arch/arm/mach-imx/include/mach/xload.h
+++ b/arch/arm/mach-imx/include/mach/xload.h
@@ -4,7 +4,6 @@
int imx53_nand_start_image(void);
int imx6_spi_load_image(int instance, unsigned int flash_offset, void *buf, int len);
int imx6_spi_start_image(int instance);
-int imx6_esdhc_load_image(int instance, void *buf, int len);
int imx6_esdhc_start_image(int instance);
int imx_image_size(void);
diff --git a/arch/arm/mach-imx/xload-esdhc.c b/arch/arm/mach-imx/xload-esdhc.c
index bd58bdc64..4580f53cd 100644
--- a/arch/arm/mach-imx/xload-esdhc.c
+++ b/arch/arm/mach-imx/xload-esdhc.c
@@ -216,50 +216,7 @@ static int esdhc_read_blocks(struct esdhc *esdhc, void *dst, size_t len)
return 0;
}
-int imx6_esdhc_load_image(int instance, void *buf, int len)
-{
- struct esdhc esdhc;
- int ret;
-
- switch (instance) {
- case 0:
- esdhc.regs = IOMEM(MX6_USDHC1_BASE_ADDR);
- break;
- case 1:
- esdhc.regs = IOMEM(MX6_USDHC2_BASE_ADDR);
- break;
- case 2:
- esdhc.regs = IOMEM(MX6_USDHC3_BASE_ADDR);
- break;
- case 3:
- esdhc.regs = IOMEM(MX6_USDHC4_BASE_ADDR);
- break;
- default:
- return -EINVAL;
- }
-
- esdhc.is_mx6 = 1;
-
- ret = esdhc_read_blocks(&esdhc, buf, len);
- if (ret)
- return ret;
-
- return 0;
-}
-
-/**
- * imx6_esdhc_start_image - Load and start an image from USDHC controller
- * @instance: The USDHC controller instance (0..4)
- *
- * This uses imx6_esdhc_load_image() to load an image from SD/MMC.
- * It is assumed that the image is the currently running barebox image
- * (This information is used to calculate the length of the image). The
- * image is started afterwards.
- *
- * Return: If successful, this function does not return. A negative error
- * code is returned when this function fails.
- */
-int imx6_esdhc_start_image(int instance)
+static int esdhc_start_image(struct esdhc *esdhc)
{
void *buf = (void *)0x10000000;
u32 *ivt = buf + SZ_1K;
@@ -270,7 +227,7 @@ int imx6_esdhc_start_image(int instance)
len = imx_image_size();
len = ALIGN(len, SECTOR_SIZE);
- ret = imx6_esdhc_load_image(instance, buf, 3 * SECTOR_SIZE);
+ ret = esdhc_read_blocks(esdhc, buf, 3 * SECTOR_SIZE);
if (ret)
return ret;
if (*(u32 *)(ivt) != 0x402000d1) {
@@ -281,7 +238,7 @@ int imx6_esdhc_start_image(int instance)
pr_debug("Check ok, loading image\n");
- ret = imx6_esdhc_load_image(instance, buf, len);
+ ret = esdhc_read_blocks(esdhc, buf, len);
if (ret) {
pr_err("Loading image failed with %d\n", ret);
return ret;
@@ -295,3 +252,41 @@ int imx6_esdhc_start_image(int instance)
bb();
}
+
+/**
+ * imx6_esdhc_start_image - Load and start an image from USDHC controller
+ * @instance: The USDHC controller instance (0..4)
+ *
+ * This uses esdhc_start_image() to load an image from SD/MMC. It is
+ * assumed that the image is the currently running barebox image (This
+ * information is used to calculate the length of the image). The
+ * image is started afterwards.
+ *
+ * Return: If successful, this function does not return. A negative error
+ * code is returned when this function fails.
+ */
+int imx6_esdhc_start_image(int instance)
+{
+ struct esdhc esdhc;
+
+ switch (instance) {
+ case 0:
+ esdhc.regs = IOMEM(MX6_USDHC1_BASE_ADDR);
+ break;
+ case 1:
+ esdhc.regs = IOMEM(MX6_USDHC2_BASE_ADDR);
+ break;
+ case 2:
+ esdhc.regs = IOMEM(MX6_USDHC3_BASE_ADDR);
+ break;
+ case 3:
+ esdhc.regs = IOMEM(MX6_USDHC4_BASE_ADDR);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ esdhc.is_mx6 = 1;
+
+ return esdhc_start_image(&esdhc);
+}
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 25/48] ARM: i.MX: xload-esdhc: Allow custom buffer address, device offset
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (23 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 24/48] ARM: i.MX: xload-esdhc: Rework to make code be less i.MX6-specific Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 26/48] ARM: i.MX: xload-esdhc: Add support for i.MX8 Andrey Smirnov
` (22 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Add code to support specifying different buffer address and SD/MMC
device offset to read it from in esdhc_start_image(). This change is
needed to support i.MX8.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/xload-esdhc.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-imx/xload-esdhc.c b/arch/arm/mach-imx/xload-esdhc.c
index 4580f53cd..d4c1dfa28 100644
--- a/arch/arm/mach-imx/xload-esdhc.c
+++ b/arch/arm/mach-imx/xload-esdhc.c
@@ -176,7 +176,7 @@ esdhc_send_cmd(struct esdhc *esdhc, struct mci_cmd *cmd, struct mci_data *data)
return 0;
}
-static int esdhc_read_blocks(struct esdhc *esdhc, void *dst, size_t len)
+static int esdhc_read_blocks(struct esdhc *esdhc, u32 offset, void *dst, size_t len)
{
struct mci_cmd cmd;
struct mci_data data;
@@ -193,7 +193,7 @@ static int esdhc_read_blocks(struct esdhc *esdhc, void *dst, size_t len)
writel(val, esdhc->regs + SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET);
cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
- cmd.cmdarg = 0;
+ cmd.cmdarg = offset;
cmd.resp_type = MMC_RSP_R1;
data.dest = dst;
@@ -216,9 +216,9 @@ static int esdhc_read_blocks(struct esdhc *esdhc, void *dst, size_t len)
return 0;
}
-static int esdhc_start_image(struct esdhc *esdhc)
+static int esdhc_start_image(struct esdhc *esdhc, ptrdiff_t address, u32 offset)
{
- void *buf = (void *)0x10000000;
+ void *buf = (void *)address;
u32 *ivt = buf + SZ_1K;
int ret, len;
void __noreturn (*bb)(void);
@@ -227,7 +227,7 @@ static int esdhc_start_image(struct esdhc *esdhc)
len = imx_image_size();
len = ALIGN(len, SECTOR_SIZE);
- ret = esdhc_read_blocks(esdhc, buf, 3 * SECTOR_SIZE);
+ ret = esdhc_read_blocks(esdhc, offset, buf, 3 * SECTOR_SIZE);
if (ret)
return ret;
if (*(u32 *)(ivt) != 0x402000d1) {
@@ -238,7 +238,7 @@ static int esdhc_start_image(struct esdhc *esdhc)
pr_debug("Check ok, loading image\n");
- ret = esdhc_read_blocks(esdhc, buf, len);
+ ret = esdhc_read_blocks(esdhc, offset, buf, len);
if (ret) {
pr_err("Loading image failed with %d\n", ret);
return ret;
@@ -288,5 +288,5 @@ int imx6_esdhc_start_image(int instance)
esdhc.is_mx6 = 1;
- return esdhc_start_image(&esdhc);
+ return esdhc_start_image(&esdhc, 0x10000000, 0);
}
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 26/48] ARM: i.MX: xload-esdhc: Add support for i.MX8
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (24 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 25/48] ARM: i.MX: xload-esdhc: Allow custom buffer address, device offset Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 27/48] pinctrl: i.MX: " Andrey Smirnov
` (21 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/include/mach/xload.h | 1 +
arch/arm/mach-imx/xload-esdhc.c | 34 ++++++++++++++++++++++++++
2 files changed, 35 insertions(+)
diff --git a/arch/arm/mach-imx/include/mach/xload.h b/arch/arm/mach-imx/include/mach/xload.h
index 4e38ac7e2..8f141bc37 100644
--- a/arch/arm/mach-imx/include/mach/xload.h
+++ b/arch/arm/mach-imx/include/mach/xload.h
@@ -5,6 +5,7 @@ int imx53_nand_start_image(void);
int imx6_spi_load_image(int instance, unsigned int flash_offset, void *buf, int len);
int imx6_spi_start_image(int instance);
int imx6_esdhc_start_image(int instance);
+int imx8_esdhc_start_image(int instance);
int imx_image_size(void);
diff --git a/arch/arm/mach-imx/xload-esdhc.c b/arch/arm/mach-imx/xload-esdhc.c
index d4c1dfa28..28f4fdcf2 100644
--- a/arch/arm/mach-imx/xload-esdhc.c
+++ b/arch/arm/mach-imx/xload-esdhc.c
@@ -15,6 +15,7 @@
#include <io.h>
#include <mci.h>
#include <mach/imx6-regs.h>
+#include <mach/imx8mq-regs.h>
#include <mach/xload.h>
#include <linux/sizes.h>
#include "../../../drivers/mci/sdhci.h"
@@ -290,3 +291,36 @@ int imx6_esdhc_start_image(int instance)
return esdhc_start_image(&esdhc, 0x10000000, 0);
}
+
+/**
+ * imx8_esdhc_start_image - Load and start an image from USDHC controller
+ * @instance: The USDHC controller instance (0..2)
+ *
+ * This uses esdhc_start_image() to load an image from SD/MMC. It is
+ * assumed that the image is the currently running barebox image (This
+ * information is used to calculate the length of the image). The
+ * image is started afterwards.
+ *
+ * Return: If successful, this function does not return. A negative error
+ * code is returned when this function fails.
+ */
+int imx8_esdhc_start_image(int instance)
+{
+ struct esdhc esdhc;
+
+ switch (instance) {
+ case 0:
+ esdhc.regs = IOMEM(MX8MQ_USDHC1_BASE_ADDR);
+ break;
+ case 1:
+ esdhc.regs = IOMEM(MX8MQ_USDHC2_BASE_ADDR);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ esdhc.is_mx6 = 1;
+
+ return esdhc_start_image(&esdhc, MX8MQ_DDR_CSD1_BASE_ADDR,
+ 32 * 2 * SECTOR_SIZE);
+}
\ No newline at end of file
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 27/48] pinctrl: i.MX: Add support for i.MX8
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (25 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 26/48] ARM: i.MX: xload-esdhc: Add support for i.MX8 Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 28/48] Documentation: imx: Change block size for 'dd' to 1024 Andrey Smirnov
` (20 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/include/mach/iomux-v3.h | 9 ++++
drivers/pinctrl/imx-iomux-v3.c | 56 ++++++++++++++++++++---
2 files changed, 59 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-imx/include/mach/iomux-v3.h b/arch/arm/mach-imx/include/mach/iomux-v3.h
index 40f6e5999..994c15c04 100644
--- a/arch/arm/mach-imx/include/mach/iomux-v3.h
+++ b/arch/arm/mach-imx/include/mach/iomux-v3.h
@@ -17,6 +17,7 @@
#define __MACH_IOMUX_V3_H__
#include <io.h>
+#include <linux/bitfield.h>
/*
* build IOMUX_PAD structure
@@ -95,6 +96,13 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_DVS (1 << 13)
#define PAD_CTL_HYS (1 << 8)
+#define SHARE_CONF_PAD_CTL_DSE GENMASK(2, 0)
+#define SHARE_CONF_PAD_CTL_SRE GENMASK(4, 3)
+
+#define SHARE_CONF_PAD_CTL_ODE BIT(5)
+#define SHARE_CONF_PAD_CTL_PUE BIT(6)
+#define SHARE_CONF_PAD_CTL_HYS BIT(7)
+
#define PAD_CTL_PKE (1 << 7)
#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
@@ -118,6 +126,7 @@ typedef u64 iomux_v3_cfg_t;
#define SHARE_MUX_CONF_REG 0x1
#define ZERO_OFFSET_VALID 0x2
#define IMX7_PINMUX_LPSR 0x4
+#define SHARE_CONF BIT(3)
static inline void iomux_v3_setup_pad(void __iomem *iomux, unsigned int flags,
u32 mux_reg, u32 conf_reg, u32 input_reg,
diff --git a/drivers/pinctrl/imx-iomux-v3.c b/drivers/pinctrl/imx-iomux-v3.c
index 50d717736..38451875e 100644
--- a/drivers/pinctrl/imx-iomux-v3.c
+++ b/drivers/pinctrl/imx-iomux-v3.c
@@ -73,6 +73,7 @@ EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
* 1 u32 CONFIG, so 24 types in total for each pin.
*/
#define FSL_PIN_SIZE 24
+#define SHARE_CONF_FSL_PIN_SIZE (FSL_PIN_SIZE - 1 * sizeof(u32))
#define IMX_DT_NO_PAD_CTL (1 << 31)
#define IMX_PAD_SION (1 << 30)
@@ -83,22 +84,57 @@ static int imx_iomux_v3_set_state(struct pinctrl_device *pdev, struct device_nod
{
struct imx_iomux_v3 *iomux = container_of(pdev, struct imx_iomux_v3, pinctrl);
const __be32 *list;
- int npins, size, i;
+ const bool share_conf = iomux->flags & SHARE_CONF;
+ int npins, size, i, fsl_pin_size;
+ const char *name;
+ u32 share_conf_val;
dev_dbg(iomux->pinctrl.dev, "set state: %s\n", np->full_name);
- list = of_get_property(np, "fsl,pins", &size);
+ if (share_conf) {
+ u32 drive_strength, slew_rate;
+ int ret;
+
+ fsl_pin_size = SHARE_CONF_FSL_PIN_SIZE;
+ name = "pinmux";
+
+ ret = of_property_read_u32(np, "drive-strength",
+ &drive_strength);
+ if (ret)
+ return ret;
+
+ ret = of_property_read_u32(np, "slew-rate", &slew_rate);
+ if (ret)
+ return ret;
+
+ share_conf_val =
+ FIELD_PREP(SHARE_CONF_PAD_CTL_DSE, drive_strength) |
+ FIELD_PREP(SHARE_CONF_PAD_CTL_SRE, slew_rate);
+
+ if (of_get_property(np, "drive-open-drain", NULL))
+ share_conf_val |= SHARE_CONF_PAD_CTL_ODE;
+
+ if (of_get_property(np, "input-schmitt-enable", NULL))
+ share_conf_val |= SHARE_CONF_PAD_CTL_HYS;
+
+ if (of_get_property(np, "bias-pull-up", NULL))
+ share_conf_val |= SHARE_CONF_PAD_CTL_PUE;
+ } else {
+ fsl_pin_size = FSL_PIN_SIZE;
+ name = "fsl,pins";
+ }
+
+ list = of_get_property(np, name, &size);
if (!list)
return -EINVAL;
-
- if (!size || size % FSL_PIN_SIZE) {
+ if (!size || size % fsl_pin_size) {
dev_err(iomux->pinctrl.dev, "Invalid fsl,pins property in %s\n",
np->full_name);
return -EINVAL;
}
- npins = size / FSL_PIN_SIZE;
+ npins = size / fsl_pin_size;
for (i = 0; i < npins; i++) {
u32 mux_reg = be32_to_cpu(*list++);
@@ -106,7 +142,8 @@ static int imx_iomux_v3_set_state(struct pinctrl_device *pdev, struct device_nod
u32 input_reg = be32_to_cpu(*list++);
u32 mux_val = be32_to_cpu(*list++);
u32 input_val = be32_to_cpu(*list++);
- u32 conf_val = be32_to_cpu(*list++);
+ u32 conf_val = share_conf ?
+ share_conf_val : be32_to_cpu(*list++);
if (conf_val & IMX_PAD_SION) {
mux_val |= IOMUXC_CONFIG_SION;
@@ -180,6 +217,10 @@ static struct imx_iomux_v3_data imx_iomux_imx7_lpsr_data = {
.flags = ZERO_OFFSET_VALID | IMX7_PINMUX_LPSR,
};
+static struct imx_iomux_v3_data imx_iomux_imx8_data = {
+ .flags = SHARE_CONF,
+};
+
static __maybe_unused struct of_device_id imx_iomux_v3_dt_ids[] = {
{
.compatible = "fsl,imx25-iomuxc",
@@ -204,6 +245,9 @@ static __maybe_unused struct of_device_id imx_iomux_v3_dt_ids[] = {
}, {
.compatible = "fsl,imx7d-iomuxc-lpsr",
.data = &imx_iomux_imx7_lpsr_data,
+ }, {
+ .compatible = "fsl,imx8mq-iomuxc",
+ .data = &imx_iomux_imx8_data,
}, {
/* sentinel */
}
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 28/48] Documentation: imx: Change block size for 'dd' to 1024
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (26 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 27/48] pinctrl: i.MX: " Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 29/48] Documentation: i.MX: Add missing <soctype> Andrey Smirnov
` (19 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Real image start at offset 0x400 (1024), so we can skip copying extra
512 bytes of zeros.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
Documentation/boards/imx.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/boards/imx.rst b/Documentation/boards/imx.rst
index 9b1eb82d4..de389456e 100644
--- a/Documentation/boards/imx.rst
+++ b/Documentation/boards/imx.rst
@@ -42,7 +42,7 @@ The above will overwrite the MBR (and consequently the partition table)
on the destination SD card. To preserve the MBR while writing the rest
of the image to the card, use::
- dd if=images/barebox-freescale-imx51-babbage.img of=/dev/sdd bs=512 skip=1 seek=1
+ dd if=images/barebox-freescale-imx51-babbage.img of=/dev/sdd bs=1024 skip=1 seek=1
The images can also always be started second stage::
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 29/48] Documentation: i.MX: Add missing <soctype>
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (27 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 28/48] Documentation: imx: Change block size for 'dd' to 1024 Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-28 15:23 ` Sascha Hauer
2018-05-26 20:44 ` [PATCH v2 30/48] clocksource: armv8-timer: Make armv8_clocksource_read() static Andrey Smirnov
` (18 subsequent siblings)
47 siblings, 1 reply; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
Documentation/boards/imx.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/boards/imx.rst b/Documentation/boards/imx.rst
index de389456e..196513520 100644
--- a/Documentation/boards/imx.rst
+++ b/Documentation/boards/imx.rst
@@ -59,7 +59,7 @@ options in this file are:
Header:
+----------------+--------------------------------------------------------------+
-| soc <soctype> | soctype can be one of imx35, imx51, imx53, imx6 |
+| soc <soctype> | soctype can be one of imx35, imx51, imx53, imx6, imx7, vf610 |
+----------------+--------------------------------------------------------------+
| loadaddr <adr> | The address the binary is uploaded to |
+----------------+--------------------------------------------------------------+
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* Re: [PATCH v2 29/48] Documentation: i.MX: Add missing <soctype>
2018-05-26 20:44 ` [PATCH v2 29/48] Documentation: i.MX: Add missing <soctype> Andrey Smirnov
@ 2018-05-28 15:23 ` Sascha Hauer
2018-05-28 18:02 ` Andrey Smirnov
0 siblings, 1 reply; 57+ messages in thread
From: Sascha Hauer @ 2018-05-28 15:23 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: barebox
On Sat, May 26, 2018 at 01:44:32PM -0700, Andrey Smirnov wrote:
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
> Documentation/boards/imx.rst | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/boards/imx.rst b/Documentation/boards/imx.rst
> index de389456e..196513520 100644
> --- a/Documentation/boards/imx.rst
> +++ b/Documentation/boards/imx.rst
> @@ -59,7 +59,7 @@ options in this file are:
> Header:
>
> +----------------+--------------------------------------------------------------+
> -| soc <soctype> | soctype can be one of imx35, imx51, imx53, imx6 |
> +| soc <soctype> | soctype can be one of imx35, imx51, imx53, imx6, imx7, vf610 |
> +----------------+--------------------------------------------------------------+
i.MX8 aswell?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v2 29/48] Documentation: i.MX: Add missing <soctype>
2018-05-28 15:23 ` Sascha Hauer
@ 2018-05-28 18:02 ` Andrey Smirnov
0 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-28 18:02 UTC (permalink / raw)
To: Sascha Hauer; +Cc: Barebox List
On Mon, May 28, 2018 at 8:23 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Sat, May 26, 2018 at 01:44:32PM -0700, Andrey Smirnov wrote:
>> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
>> ---
>> Documentation/boards/imx.rst | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/Documentation/boards/imx.rst b/Documentation/boards/imx.rst
>> index de389456e..196513520 100644
>> --- a/Documentation/boards/imx.rst
>> +++ b/Documentation/boards/imx.rst
>> @@ -59,7 +59,7 @@ options in this file are:
>> Header:
>>
>> +----------------+--------------------------------------------------------------+
>> -| soc <soctype> | soctype can be one of imx35, imx51, imx53, imx6 |
>> +| soc <soctype> | soctype can be one of imx35, imx51, imx53, imx6, imx7, vf610 |
>> +----------------+--------------------------------------------------------------+
>
> i.MX8 aswell?
>
Added in 47/48 since it seem like a more appropriate place, do you
want me to move it here?
Thanks,
Andrey Smirnov
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH v2 30/48] clocksource: armv8-timer: Make armv8_clocksource_read() static
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (28 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 29/48] Documentation: i.MX: Add missing <soctype> Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 31/48] clocksource: armv8-timer: Make use of postcore_platform_driver() Andrey Smirnov
` (17 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
There are no users of that function outside of the driver itself, so
re-declare it as static.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/clocksource/armv8-timer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clocksource/armv8-timer.c b/drivers/clocksource/armv8-timer.c
index c5306dcd2..5e0b9ef3c 100644
--- a/drivers/clocksource/armv8-timer.c
+++ b/drivers/clocksource/armv8-timer.c
@@ -20,7 +20,7 @@
#include <io.h>
#include <asm/system.h>
-uint64_t armv8_clocksource_read(void)
+static uint64_t armv8_clocksource_read(void)
{
return get_cntpct();
}
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 31/48] clocksource: armv8-timer: Make use of postcore_platform_driver()
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (29 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 30/48] clocksource: armv8-timer: Make armv8_clocksource_read() static Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 32/48] Port <linux/iopoll.h> from U-Boot Andrey Smirnov
` (16 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/clocksource/armv8-timer.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/clocksource/armv8-timer.c b/drivers/clocksource/armv8-timer.c
index 5e0b9ef3c..918232e0e 100644
--- a/drivers/clocksource/armv8-timer.c
+++ b/drivers/clocksource/armv8-timer.c
@@ -48,9 +48,5 @@ static struct driver_d armv8_timer_driver = {
.probe = armv8_timer_probe,
.of_compatible = DRV_OF_COMPAT(armv8_timer_dt_ids),
};
+postcore_platform_driver(armv8_timer_driver);
-static int armv8_timer_init(void)
-{
- return platform_driver_register(&armv8_timer_driver);
-}
-postcore_initcall(armv8_timer_init);
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 32/48] Port <linux/iopoll.h> from U-Boot
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (30 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 31/48] clocksource: armv8-timer: Make use of postcore_platform_driver() Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 33/48] common/clock: Move delay and timeout functions to clock.h Andrey Smirnov
` (15 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
include/linux/iopoll.h | 69 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/linux/iopoll.h
diff --git a/include/linux/iopoll.h b/include/linux/iopoll.h
new file mode 100644
index 000000000..6e8a6fd71
--- /dev/null
+++ b/include/linux/iopoll.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2012-2014 The Linux Foundation. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _LINUX_IOPOLL_H
+#define _LINUX_IOPOLL_H
+
+#include <errno.h>
+#include <io.h>
+#include <clock.h>
+
+/**
+ * readx_poll_timeout - Periodically poll an address until a condition is met or a timeout occurs
+ * @op: accessor function (takes @addr as its only argument)
+ * @addr: Address to poll
+ * @val: Variable to read the value into
+ * @cond: Break condition (usually involving @val)
+ * @timeout_ns: Timeout in ns, 0 means never timeout
+ *
+ * Returns 0 on success and -ETIMEDOUT upon a timeout. In either
+ * case, the last read value at @addr is stored in @val.
+ *
+ * When available, you'll probably want to use one of the specialized
+ * macros defined below rather than this macro directly.
+ */
+#define readx_poll_timeout(op, addr, val, cond, timeout_ns) \
+({ \
+ uint64_t start = get_time_ns(); \
+ for (;;) { \
+ (val) = op(addr); \
+ if (cond) \
+ break; \
+ if (timeout_ns && \
+ is_timeout(start, (timeout_ns))) { \
+ (val) = op(addr); \
+ break; \
+ } \
+ } \
+ (cond) ? 0 : -ETIMEDOUT; \
+})
+
+
+#define readb_poll_timeout(addr, val, cond, timeout_us) \
+ readx_poll_timeout(readb, addr, val, cond, timeout_us)
+
+#define readw_poll_timeout(addr, val, cond, timeout_us) \
+ readx_poll_timeout(readw, addr, val, cond, timeout_us)
+
+#define readl_poll_timeout(addr, val, cond, timeout_us) \
+ readx_poll_timeout(readl, addr, val, cond, timeout_us)
+
+#define readq_poll_timeout(addr, val, cond, timeout_us) \
+ readx_poll_timeout(readq, addr, val, cond, timeout_us)
+
+#define readb_relaxed_poll_timeout(addr, val, cond, timeout_us) \
+ readx_poll_timeout(readb_relaxed, addr, val, cond, timeout_us)
+
+#define readw_relaxed_poll_timeout(addr, val, cond, timeout_us) \
+ readx_poll_timeout(readw_relaxed, addr, val, cond, timeout_us)
+
+#define readl_relaxed_poll_timeout(addr, val, cond, timeout_us) \
+ readx_poll_timeout(readl_relaxed, addr, val, cond, timeout_us)
+
+#define readq_relaxed_poll_timeout(addr, val, cond, timeout_us) \
+ readx_poll_timeout(readq_relaxed, addr, val, cond, timeout_us)
+
+#endif /* _LINUX_IOPOLL_H */
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 33/48] common/clock: Move delay and timeout functions to clock.h
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (31 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 32/48] Port <linux/iopoll.h> from U-Boot Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 34/48] clock: Use udelay() to implement mdelay() Andrey Smirnov
` (14 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Move delay and timeout functions to clock.h and add necessary
preprocessor code in order to make them availible in PBL. The header
is written such that by providing a pre-define get_time_ns
macro (before the inclusion point of clock.h) user can make use of all
of the timeout/delay functionality without having to have a
functioning clock source.
An example of simple use-case would be using any variant of
readx_poll_timeout with timeout of zero (infinite timeout) by
providing the following trivial definition:
\#define get_time_ns() 0
before <linux/iopoll.h> is included.
More sophisticated use-case would be providing a definition for a very
simplistic get_time_ns() function and using actual timekeeping
functionality such as is_timeout() or udelay().
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
common/clock.c | 52 ------------------------------------
include/clock.h | 70 +++++++++++++++++++++++++++++++++++++++++++------
2 files changed, 62 insertions(+), 60 deletions(-)
diff --git a/common/clock.c b/common/clock.c
index f98176dd5..c356a88b5 100644
--- a/common/clock.c
+++ b/common/clock.c
@@ -25,7 +25,6 @@
#include <init.h>
#include <asm-generic/div64.h>
#include <clock.h>
-#include <poller.h>
static uint64_t time_ns;
@@ -170,57 +169,6 @@ uint32_t clocksource_hz2mult(uint32_t hz, uint32_t shift_constant)
return (uint32_t)tmp;
}
-int is_timeout_non_interruptible(uint64_t start_ns, uint64_t time_offset_ns)
-{
- if ((int64_t)(start_ns + time_offset_ns - get_time_ns()) < 0)
- return 1;
- else
- return 0;
-}
-EXPORT_SYMBOL(is_timeout_non_interruptible);
-
-int is_timeout(uint64_t start_ns, uint64_t time_offset_ns)
-{
- if (time_offset_ns >= 100 * USECOND)
- poller_call();
-
- return is_timeout_non_interruptible(start_ns, time_offset_ns);
-}
-EXPORT_SYMBOL(is_timeout);
-
-void ndelay(unsigned long nsecs)
-{
- uint64_t start = get_time_ns();
-
- while(!is_timeout_non_interruptible(start, nsecs));
-}
-EXPORT_SYMBOL(ndelay);
-
-void udelay(unsigned long usecs)
-{
- uint64_t start = get_time_ns();
-
- while(!is_timeout(start, usecs * USECOND));
-}
-EXPORT_SYMBOL(udelay);
-
-void mdelay(unsigned long msecs)
-{
- uint64_t start = get_time_ns();
-
- while(!is_timeout(start, msecs * MSECOND));
-}
-EXPORT_SYMBOL(mdelay);
-
-void mdelay_non_interruptible(unsigned long msecs)
-{
- uint64_t start = get_time_ns();
-
- while (!is_timeout_non_interruptible(start, msecs * MSECOND))
- ;
-}
-EXPORT_SYMBOL(mdelay_non_interruptible);
-
int init_clock(struct clocksource *cs)
{
if (current_clock && cs->priority <= current_clock->priority)
diff --git a/include/clock.h b/include/clock.h
index 5f2f53ab6..38b335c2c 100644
--- a/include/clock.h
+++ b/include/clock.h
@@ -25,26 +25,80 @@ static inline uint32_t cyc2ns(struct clocksource *cs, uint64_t cycles)
int init_clock(struct clocksource *);
+#ifndef get_time_ns
+#define get_time_ns get_time_ns
+
uint64_t get_time_ns(void);
+#endif
void clocks_calc_mult_shift(uint32_t *mult, uint32_t *shift, uint32_t from, uint32_t to, uint32_t maxsec);
uint32_t clocksource_hz2mult(uint32_t hz, uint32_t shift_constant);
-int is_timeout(uint64_t start_ns, uint64_t time_offset_ns);
-int is_timeout_non_interruptible(uint64_t start_ns, uint64_t time_offset_ns);
-
-void ndelay(unsigned long nsecs);
-void udelay(unsigned long usecs);
-void mdelay(unsigned long msecs);
-void mdelay_non_interruptible(unsigned long msecs);
-
#define SECOND ((uint64_t)(1000 * 1000 * 1000))
#define MSECOND ((uint64_t)(1000 * 1000))
#define USECOND ((uint64_t)(1000))
extern uint64_t time_beginning;
+static inline int
+is_timeout_non_interruptible(uint64_t start_ns, uint64_t time_offset_ns)
+{
+ if ((int64_t)(start_ns + time_offset_ns - get_time_ns()) < 0)
+ return 1;
+ else
+ return 0;
+}
+
+#if defined(__PBL__)
+/*
+ * Poller infrastructure is not available in PBL, so we just define
+ * is_timeout to be a synonym for is_timeout_non_interruptible
+ */
+static inline int is_timeout(uint64_t start_ns, uint64_t time_offset_ns)
+ __alias(is_timeout_non_interruptible);
+#else
+#include <poller.h>
+
+static inline int is_timeout(uint64_t start_ns, uint64_t time_offset_ns)
+{
+
+ if (time_offset_ns >= 100 * USECOND)
+ poller_call();
+
+ return is_timeout_non_interruptible(start_ns, time_offset_ns);
+}
+#endif
+
+static inline void ndelay(unsigned long nsecs)
+{
+ uint64_t start = get_time_ns();
+
+ while(!is_timeout_non_interruptible(start, nsecs));
+}
+
+static inline void udelay(unsigned long usecs)
+{
+ uint64_t start = get_time_ns();
+
+ while(!is_timeout(start, usecs * USECOND));
+}
+
+static inline void mdelay(unsigned long msecs)
+{
+ uint64_t start = get_time_ns();
+
+ while(!is_timeout(start, msecs * MSECOND));
+}
+
+static inline void mdelay_non_interruptible(unsigned long msecs)
+{
+ uint64_t start = get_time_ns();
+
+ while (!is_timeout_non_interruptible(start, msecs * MSECOND))
+ ;
+}
+
/*
* Convenience wrapper to implement a typical polling loop with
* timeout. returns 0 if the condition became true within the
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 34/48] clock: Use udelay() to implement mdelay()
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (32 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 33/48] common/clock: Move delay and timeout functions to clock.h Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 35/48] ARM: i.MX8: Add DDRC PHY and DDR CTL base addresses Andrey Smirnov
` (13 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
include/clock.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/include/clock.h b/include/clock.h
index 38b335c2c..8e40451a3 100644
--- a/include/clock.h
+++ b/include/clock.h
@@ -86,9 +86,7 @@ static inline void udelay(unsigned long usecs)
static inline void mdelay(unsigned long msecs)
{
- uint64_t start = get_time_ns();
-
- while(!is_timeout(start, msecs * MSECOND));
+ udelay(msecs * MSECOND / USECOND);
}
static inline void mdelay_non_interruptible(unsigned long msecs)
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 35/48] ARM: i.MX8: Add DDRC PHY and DDR CTL base addresses
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (33 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 34/48] clock: Use udelay() to implement mdelay() Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 36/48] ARM: i.MX8: Add DDRC PHY support code Andrey Smirnov
` (12 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/include/mach/imx8mq-regs.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/include/mach/imx8mq-regs.h b/arch/arm/mach-imx/include/mach/imx8mq-regs.h
index 6dac00107..51936f526 100644
--- a/arch/arm/mach-imx/include/mach/imx8mq-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx8mq-regs.h
@@ -114,8 +114,10 @@
#define MX8MQ_SRC_DDRC_RCR_ADDR 0x30391000
#define MX8MQ_SRC_DDRC2_RCR_ADDR 0x30391004
-#define MX8MQ_DDRC_DDR_SS_GPR0 0x3d000000
+#define MX8MQ_DDRC_PHY_BASE_ADDR 0x3c000000
+#define MX8MQ_DDRC_DDR_SS_GPR0 (MX8MQ_DDRC_PHY_BASE_ADDR + 0x01000000)
#define MX8MQ_DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
+#define MX8MQ_DDRC_CTL_BASE_ADDR MX8MQ_DDRC_IPS_BASE_ADDR(0)
#define MX8MQ_DDR_CSD1_BASE_ADDR 0x40000000
#endif /* __MACH_IMX8MQ_REGS_H */
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 36/48] ARM: i.MX8: Add DDRC PHY support code
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (34 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 35/48] ARM: i.MX8: Add DDRC PHY and DDR CTL base addresses Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 37/48] ARM: Specify HAVE_PBL_IMAGE for CPU_64 Andrey Smirnov
` (11 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Add DDRC PHY support code needed to upload DDR training firwmare as
well as to wait for the training process to complete.
Those are needed to support board specific DDR initialization code.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/imx8-ddrc.c | 114 +++++++++++++++++++++
arch/arm/mach-imx/include/mach/imx8-ddrc.h | 35 +++++++
3 files changed, 150 insertions(+)
create mode 100644 arch/arm/mach-imx/imx8-ddrc.c
create mode 100644 arch/arm/mach-imx/include/mach/imx8-ddrc.h
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index a6385ff90..621062e47 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -16,6 +16,7 @@ CFLAGS_imx6.o := -march=armv7-a
lwl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o
obj-$(CONFIG_ARCH_IMX7) += imx7.o
obj-$(CONFIG_ARCH_IMX8MQ) += imx8mq.o
+lwl-$(CONFIG_ARCH_IMX8MQ) += imx8-ddrc.o
obj-$(CONFIG_ARCH_IMX_XLOAD) += xload.o
obj-$(CONFIG_IMX_IIM) += iim.o
obj-$(CONFIG_IMX_OCOTP) += ocotp.o
diff --git a/arch/arm/mach-imx/imx8-ddrc.c b/arch/arm/mach-imx/imx8-ddrc.c
new file mode 100644
index 000000000..5a9a78876
--- /dev/null
+++ b/arch/arm/mach-imx/imx8-ddrc.c
@@ -0,0 +1,114 @@
+/*
+ * Define dummy get_time_ns() in order to be able to use
+ * readl_poll_timeout(). This has to happen before inclusion of
+ * <clock.h> which will happen in <common.h>
+ */
+#define get_time_ns() 0
+
+#include <common.h>
+#include <linux/iopoll.h>
+#include <mach/imx8-ddrc.h>
+#include <debug_ll.h>
+
+void ddrc_phy_load_firmware(void __iomem *phy,
+ enum ddrc_phy_firmware_offset offset,
+ const u16 *blob, size_t size)
+{
+ while (size) {
+ writew(*blob++, phy + DDRC_PHY_REG(offset));
+ offset++;
+ size -= sizeof(*blob);
+ }
+}
+
+enum pmc_constants {
+ PMC_MESSAGE_ID,
+ PMC_MESSAGE_STREAM,
+
+ PMC_TRAIN_SUCCESS = 0x07,
+ PMC_TRAIN_STREAM_START = 0x08,
+ PMC_TRAIN_FAIL = 0xff,
+};
+
+static u32 ddrc_phy_get_message(void __iomem *phy, int type)
+{
+ u32 r, message;
+
+ /*
+ * When BIT0 set to 0, the PMU has a message for the user
+ * 10ms seems not enough for poll message, so use 1s here.
+ */
+ readl_poll_timeout(phy + DDRC_PHY_REG(0xd0004),
+ r, !(r & BIT(0)), 0);
+
+ switch (type) {
+ case PMC_MESSAGE_ID:
+ /*
+ * Get the major message ID
+ */
+ message = readl(phy + DDRC_PHY_REG(0xd0032));
+ break;
+ case PMC_MESSAGE_STREAM:
+ message = readl(phy + DDRC_PHY_REG(0xd0034));
+ message <<= 16;
+ message |= readl(phy + DDRC_PHY_REG(0xd0032));
+ break;
+ }
+
+ /*
+ * By setting this register to 0, the user acknowledges the
+ * receipt of the message.
+ */
+ writel(0x00000000, phy + DDRC_PHY_REG(0xd0031));
+ /*
+ * When BIT0 set to 0, the PMU has a message for the user
+ */
+ readl_poll_timeout(phy + DDRC_PHY_REG(0xd0004),
+ r, r & BIT(0), 0);
+
+ writel(0x00000001, phy + DDRC_PHY_REG(0xd0031));
+
+ return message;
+}
+
+static void ddrc_phy_fetch_streaming_message(void __iomem *phy)
+{
+ const u16 index = ddrc_phy_get_message(phy, PMC_MESSAGE_STREAM);
+ u16 i;
+
+ putc_ll('|');
+ puthex_ll(index);
+
+ for (i = 0; i < index; i++) {
+ const u32 arg = ddrc_phy_get_message(phy, PMC_MESSAGE_STREAM);
+
+ putc_ll('|');
+ puthex_ll(arg);
+ }
+}
+
+void ddrc_phy_wait_training_complete(void __iomem *phy)
+{
+ for (;;) {
+ const u32 m = ddrc_phy_get_message(phy, PMC_MESSAGE_ID);
+
+ puthex_ll(m);
+
+ switch (m) {
+ case PMC_TRAIN_STREAM_START:
+ ddrc_phy_fetch_streaming_message(phy);
+ break;
+ case PMC_TRAIN_SUCCESS:
+ putc_ll('P');
+ putc_ll('\r');
+ putc_ll('\n');
+ return;
+ case PMC_TRAIN_FAIL:
+ putc_ll('F');
+ hang();
+ }
+
+ putc_ll('\r');
+ putc_ll('\n');
+ }
+}
\ No newline at end of file
diff --git a/arch/arm/mach-imx/include/mach/imx8-ddrc.h b/arch/arm/mach-imx/include/mach/imx8-ddrc.h
new file mode 100644
index 000000000..8342d903e
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx8-ddrc.h
@@ -0,0 +1,35 @@
+#ifndef __IMX8_DDRC_H__
+#define __IMX8_DDRC_H__
+
+#include <linux/compiler.h>
+
+enum ddrc_phy_firmware_offset {
+ DDRC_PHY_IMEM = 0x00050000U,
+ DDRC_PHY_DMEM = 0x00054000U,
+};
+
+void ddrc_phy_load_firmware(void __iomem *,
+ enum ddrc_phy_firmware_offset,
+ const u16 *, size_t);
+
+#define __DDRC_PHY_FIRMWARE_PAIR(f) \
+ __ddr_phy_fw_##f##_start, __ddr_phy_fw_##f##_end
+
+#define ___DDRC_PHY_FIRMWARE(s, e) \
+ s, ((size_t)((ptrdiff_t)e - (ptrdiff_t)s))
+#define __DDRC_PHY_FIRMWARE(f) ___DDRC_PHY_FIRMWARE(f)
+#define DDRC_PHY_FIRMWARE(f) \
+ __DDRC_PHY_FIRMWARE(__DDRC_PHY_FIRMWARE_PAIR(f))
+
+#define ___DDRC_PHY_FIRMWARE_DECLARE(s, e) \
+ extern const u16 s[]; \
+ extern const u16 e[]
+#define __DDRC_PHY_FIRMWARE_DECLARE(f) ___DDRC_PHY_FIRMWARE_DECLARE(f)
+#define DDRC_PHY_FIRMWARE_DECLARE(f) \
+ __DDRC_PHY_FIRMWARE_DECLARE(__DDRC_PHY_FIRMWARE_PAIR(f))
+
+#define DDRC_PHY_REG(x) ((x) * 4)
+
+void ddrc_phy_wait_training_complete(void __iomem *phy);
+
+#endif
\ No newline at end of file
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 37/48] ARM: Specify HAVE_PBL_IMAGE for CPU_64
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (35 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 36/48] ARM: i.MX8: Add DDRC PHY support code Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 38/48] ARM: lib64: Make string functions aware of MMU configuration Andrey Smirnov
` (10 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/cpu/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/Kconfig b/arch/arm/cpu/Kconfig
index d889e9afb..2359c56b3 100644
--- a/arch/arm/cpu/Kconfig
+++ b/arch/arm/cpu/Kconfig
@@ -12,6 +12,7 @@ config CPU_32
config CPU_64
bool
select PHYS_ADDR_T_64BIT
+ select HAVE_PBL_IMAGE
# Select CPU types depending on the architecture selected. This selects
# which CPUs we support in the kernel image, and the compiler instruction
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 38/48] ARM: lib64: Make string functions aware of MMU configuration
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (36 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 37/48] ARM: Specify HAVE_PBL_IMAGE for CPU_64 Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 39/48] ARM: mmu: Make use of dsb() and isb() helpers Andrey Smirnov
` (9 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Optimized version of memset() in memset.S if called as:
memset(foo, 0, size)
will try to explicitly zero out data cache with:
dc zva, dst
which will result in Alignement Exception (DABT) if MMU is not
enabled.
For more info see:
- C4.4.8 "DC ZVA, Data Cache Zero by VA"
- D5.2.8 "The effects of disabling a stage of address translation"
in "ARM Architecture Reference Manual. ARMv8, for ARMv8-A architecture
profile"
In similar vein, using optimized version of memcpy() could lead to a
unaligned 16-byte write (using 'stp'), which is not allowed for
Device-nGnRnE type of memory (see D5.2.8) and would liead to
Alignement Exception.
To fix both problems expose non-optimized and optimzied versions of
the function and created a wrapper to dispatch the call to either one
based on if MMU is enabled or not.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/Kconfig | 7 +++++++
arch/arm/lib64/Makefile | 2 +-
arch/arm/lib64/memcpy.S | 6 +++---
arch/arm/lib64/memset.S | 4 ++--
arch/arm/lib64/string.c | 22 ++++++++++++++++++++++
include/string.h | 3 +++
lib/string.c | 18 ++++++++++++------
7 files changed, 50 insertions(+), 12 deletions(-)
create mode 100644 arch/arm/lib64/string.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 37cde0c0c..c6a4cadb3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -353,6 +353,13 @@ menu "ARM specific settings"
config ARM_OPTIMZED_STRING_FUNCTIONS
bool "use assembler optimized string functions"
+ #
+ # memset() and memcpy() in arm/lib64/mem[set|cpy].S are
+ # written with assumption of enabled MMU and cache. Depending
+ # on the inputs in may fail with Alignement exception if used
+ # without MMU
+ #
+ depends on !CPU_V8 || MMU
help
Say yes here to use assembler optimized memcpy / memset functions.
These functions work much faster than the normal versions but
diff --git a/arch/arm/lib64/Makefile b/arch/arm/lib64/Makefile
index 77647128a..4c0019fab 100644
--- a/arch/arm/lib64/Makefile
+++ b/arch/arm/lib64/Makefile
@@ -2,7 +2,7 @@ obj-y += stacktrace.o
obj-$(CONFIG_ARM_LINUX) += armlinux.o
obj-y += div0.o
obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memcpy.o
-obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memset.o
+obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memset.o string.o
extra-y += barebox.lds
obj-pbl-y += runtime-offset.o
diff --git a/arch/arm/lib64/memcpy.S b/arch/arm/lib64/memcpy.S
index cfed3191c..a70e96ca2 100644
--- a/arch/arm/lib64/memcpy.S
+++ b/arch/arm/lib64/memcpy.S
@@ -67,8 +67,8 @@
stp \ptr, \regB, [\regC], \val
.endm
- .weak memcpy
-ENTRY(memcpy)
+ .weak __arch_memcpy
+ENTRY(__arch_memcpy)
#include "copy_template.S"
ret
-ENDPROC(memcpy)
+ENDPROC(__arch_memcpy)
diff --git a/arch/arm/lib64/memset.S b/arch/arm/lib64/memset.S
index 380a54097..d17bcc612 100644
--- a/arch/arm/lib64/memset.S
+++ b/arch/arm/lib64/memset.S
@@ -54,7 +54,7 @@ tmp3w .req w9
tmp3 .req x9
.weak memset
-ENTRY(memset)
+ENTRY(__arch_memset)
mov dst, dstin /* Preserve return value. */
and A_lw, val, #255
orr A_lw, A_lw, A_lw, lsl #8
@@ -212,4 +212,4 @@ ENTRY(memset)
ands count, count, zva_bits_x
b.ne .Ltail_maybe_long
ret
-ENDPROC(memset)
+ENDPROC(__arch_memset)
diff --git a/arch/arm/lib64/string.c b/arch/arm/lib64/string.c
new file mode 100644
index 000000000..cb2633152
--- /dev/null
+++ b/arch/arm/lib64/string.c
@@ -0,0 +1,22 @@
+#include <common.h>
+#include <asm/system.h>
+#include <string.h>
+
+void *__arch_memset(void *dst, int c, __kernel_size_t size);
+void *__arch_memcpy(void * dest, const void *src, size_t count);
+
+void *memset(void *dst, int c, __kernel_size_t size)
+{
+ if (likely(get_cr() & CR_M))
+ return __arch_memset(dst, c, size);
+
+ return __default_memset(dst, c, size);
+}
+
+void *memcpy(void * dest, const void *src, size_t count)
+{
+ if (likely(get_cr() & CR_M))
+ return __arch_memcpy(dest, src, count);
+
+ return __default_memcpy(dest, src, count);
+}
\ No newline at end of file
diff --git a/include/string.h b/include/string.h
index 0c557d6f1..6ceb33224 100644
--- a/include/string.h
+++ b/include/string.h
@@ -6,4 +6,7 @@
void *memdup(const void *, size_t);
int strtobool(const char *str, int *val);
+void *__default_memset(void *, int, __kernel_size_t);
+void *__default_memcpy(void * dest,const void *src,size_t count);
+
#endif /* __STRING_H */
diff --git a/lib/string.c b/lib/string.c
index f588933e8..717b59aa5 100644
--- a/lib/string.c
+++ b/lib/string.c
@@ -479,7 +479,6 @@ char *strswab(const char *s)
}
#endif
-#ifndef __HAVE_ARCH_MEMSET
/**
* memset - Fill a region of memory with the given value
* @s: Pointer to the start of the area.
@@ -488,7 +487,7 @@ char *strswab(const char *s)
*
* Do not use memset() to access IO space, use memset_io() instead.
*/
-void * memset(void * s,int c,size_t count)
+void *__default_memset(void * s,int c,size_t count)
{
char *xs = (char *) s;
@@ -497,10 +496,12 @@ void * memset(void * s,int c,size_t count)
return s;
}
+EXPORT_SYMBOL(__default_memset);
+
+#ifndef __HAVE_ARCH_MEMSET
+void *memset(void *s, int c, size_t count) __alias(__default_memset);
#endif
-EXPORT_SYMBOL(memset);
-#ifndef __HAVE_ARCH_MEMCPY
/**
* memcpy - Copy one area of memory to another
* @dest: Where to copy to
@@ -510,7 +511,7 @@ EXPORT_SYMBOL(memset);
* You should not use this function to access IO space, use memcpy_toio()
* or memcpy_fromio() instead.
*/
-void * memcpy(void * dest,const void *src,size_t count)
+void *__default_memcpy(void * dest,const void *src,size_t count)
{
char *tmp = (char *) dest, *s = (char *) src;
@@ -519,9 +520,14 @@ void * memcpy(void * dest,const void *src,size_t count)
return dest;
}
-#endif
EXPORT_SYMBOL(memcpy);
+#ifndef __HAVE_ARCH_MEMCPY
+void *memcpy(void * dest, const void *src, size_t count)
+ __alias(__default_memcpy);
+#endif
+
+
#ifndef __HAVE_ARCH_MEMMOVE
/**
* memmove - Copy one area of memory to another
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 39/48] ARM: mmu: Make use of dsb() and isb() helpers
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (37 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 38/48] ARM: lib64: Make string functions aware of MMU configuration Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 40/48] ARM: cache: Remove unused cache ops struct Andrey Smirnov
` (8 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/cpu/mmu_64.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h
index c280d2ced..2cbe72062 100644
--- a/arch/arm/cpu/mmu_64.h
+++ b/arch/arm/cpu/mmu_64.h
@@ -28,7 +28,7 @@ static inline void tlb_invalidate(void)
static inline void set_ttbr_tcr_mair(int el, uint64_t table, uint64_t tcr, uint64_t attr)
{
- asm volatile("dsb sy");
+ dsb();
if (el == 1) {
asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
@@ -44,7 +44,7 @@ static inline void set_ttbr_tcr_mair(int el, uint64_t table, uint64_t tcr, uint6
} else {
hang();
}
- asm volatile("isb");
+ isb();
}
static inline uint64_t get_ttbr(int el)
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 40/48] ARM: cache: Remove unused cache ops struct
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (38 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 39/48] ARM: mmu: Make use of dsb() and isb() helpers Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 41/48] ARM: no-mmu: Disable building for ARMv8 Andrey Smirnov
` (7 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Remove what appears to be a leftover from moving ARMv8 cache function
into a separate file that happened in 4b57aae26 ("ARM: Create own
cache.c file for aarch64")
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/cpu/cache.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/cpu/cache.c b/arch/arm/cpu/cache.c
index 7047470f0..f4781fe3b 100644
--- a/arch/arm/cpu/cache.c
+++ b/arch/arm/cpu/cache.c
@@ -36,7 +36,6 @@ DEFINE_CPU_FNS(v4)
DEFINE_CPU_FNS(v5)
DEFINE_CPU_FNS(v6)
DEFINE_CPU_FNS(v7)
-DEFINE_CPU_FNS(v8)
void __dma_clean_range(unsigned long start, unsigned long end)
{
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 41/48] ARM: no-mmu: Disable building for ARMv8
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (39 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 40/48] ARM: cache: Remove unused cache ops struct Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 42/48] ARM: interrupts64: Include ESR value in exception traceback Andrey Smirnov
` (6 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Disable building for ARMv8 since no-mmu.c only supports ARMv7
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/cpu/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index 0316d251c..5b4b832e8 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -17,7 +17,7 @@ obj-$(CONFIG_CMD_ARM_MMUINFO) += mmuinfo.o
obj-$(CONFIG_OFDEVICE) += dtb.o
ifeq ($(CONFIG_MMU),)
-obj-y += no-mmu.o
+obj-$(CONFIG_CPU_32v7) += no-mmu.o
endif
obj-$(CONFIG_ARM_PSCI) += psci.o
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 42/48] ARM: interrupts64: Include ESR value in exception traceback
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (40 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 41/48] ARM: no-mmu: Disable building for ARMv8 Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 43/48] ARM: mmu64: Trivial code simplification Andrey Smirnov
` (5 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Oftentimes knowing the class of exception is not enough and full ESR
value is needed to decode the specifics. Add code to print ESR as a
part of excpetion traceback to provide that information.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/cpu/interrupts_64.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/interrupts_64.c b/arch/arm/cpu/interrupts_64.c
index 32c8dfcb2..f6f0c9d09 100644
--- a/arch/arm/cpu/interrupts_64.c
+++ b/arch/arm/cpu/interrupts_64.c
@@ -155,7 +155,8 @@ void do_sync(struct pt_regs *pt_regs, unsigned int esr, unsigned long far)
return;
}
- printf("%s exception at 0x%016lx\n", esr_get_class_string(esr), far);
+ printf("%s exception (ESR 0x%08x) at 0x%016lx\n", esr_get_class_string(esr),
+ esr, far);
do_exception(pt_regs);
}
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 43/48] ARM: mmu64: Trivial code simplification
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (41 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 42/48] ARM: interrupts64: Include ESR value in exception traceback Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 44/48] ARM: mmu64: Make use of create_table() Andrey Smirnov
` (4 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/cpu/mmu_64.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index d5a3d2223..80cf240d3 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -126,6 +126,7 @@ static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t att
uint64_t idx;
uint64_t addr;
uint64_t *table;
+ uint64_t type;
int level;
if (!ttb)
@@ -145,11 +146,9 @@ static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t att
pte = table + idx;
if (size >= block_size && IS_ALIGNED(addr, block_size)) {
- if (level == 3)
- *pte = phys | attr | PTE_TYPE_PAGE;
- else
- *pte = phys | attr | PTE_TYPE_BLOCK;
-
+ type = (level == 3) ?
+ PTE_TYPE_PAGE : PTE_TYPE_BLOCK;
+ *pte = phys | attr | type;
addr += block_size;
phys += block_size;
size -= block_size;
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 44/48] ARM: mmu64: Make use of create_table()
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (42 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 43/48] ARM: mmu64: Trivial code simplification Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 45/48] ARM: mmu64: Convert flags in arch_remap_range() Andrey Smirnov
` (3 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Make use of create_table() instead of calling xmemalign() and memset()
explicitly.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/cpu/mmu_64.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 80cf240d3..820d8cf75 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -203,10 +203,7 @@ static int mmu_init(void)
if (get_cr() & CR_M)
mmu_disable();
- ttb = xmemalign(GRANULE_SIZE, GRANULE_SIZE);
-
- memset(ttb, 0, GRANULE_SIZE);
-
+ ttb = create_table();
el = current_el();
set_ttbr_tcr_mair(el, (uint64_t)ttb, calc_tcr(el), MEMORY_ATTRIBUTES);
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 45/48] ARM: mmu64: Convert flags in arch_remap_range()
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (43 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 44/48] ARM: mmu64: Make use of create_table() Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 46/48] ARM: include: dma: Add missing no-MMU stubs Andrey Smirnov
` (2 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Flags passed to arch_remap_range() are architecture independent, so it
can't be passed as is to map_region(). Add code to do the proper
conversion to avoid subtle bugs that this confusion brings.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/cpu/mmu_64.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 820d8cf75..11928352b 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -171,6 +171,17 @@ static void create_sections(uint64_t virt, uint64_t phys, uint64_t size, uint64_
int arch_remap_range(void *_start, size_t size, unsigned flags)
{
+ switch (flags) {
+ case MAP_CACHED:
+ flags = CACHED_MEM;
+ break;
+ case MAP_UNCACHED:
+ flags = UNCACHED_MEM;
+ break;
+ default:
+ return -EINVAL;
+ }
+
map_region((uint64_t)_start, (uint64_t)_start, (uint64_t)size, flags);
tlb_invalidate();
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 46/48] ARM: include: dma: Add missing no-MMU stubs
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (44 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 45/48] ARM: mmu64: Convert flags in arch_remap_range() Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 47/48] ARM: i.MX8: Add i.MX8mq EVK support Andrey Smirnov
2018-05-26 20:44 ` [PATCH v2 48/48] ARM: Introduce imx_v8_defconfig Andrey Smirnov
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Add stubs for dma_map_single() and dma_unmap_single() that were needed
for no-MMU build for ARM64 to succeed.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/include/asm/dma.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index a68886b16..bb7e62af0 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -34,6 +34,17 @@ static inline void dma_free_coherent(void *mem, dma_addr_t dma_handle,
free(mem);
}
+static inline dma_addr_t dma_map_single(struct device_d *dev, void *ptr, size_t size,
+ enum dma_data_direction dir)
+{
+ return (dma_addr_t)ptr;
+}
+
+static inline void dma_unmap_single(struct device_d *dev, dma_addr_t addr, size_t size,
+ enum dma_data_direction dir)
+{
+}
+
static inline void dma_sync_single_for_cpu(dma_addr_t address, size_t size,
enum dma_data_direction dir)
{
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* [PATCH v2 47/48] ARM: i.MX8: Add i.MX8mq EVK support
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (45 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 46/48] ARM: include: dma: Add missing no-MMU stubs Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
2018-05-28 15:51 ` Sascha Hauer
2018-05-28 16:04 ` Sascha Hauer
2018-05-26 20:44 ` [PATCH v2 48/48] ARM: Introduce imx_v8_defconfig Andrey Smirnov
47 siblings, 2 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
From: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
Documentation/boards/imx.rst | 10 +-
Documentation/boards/imx/nxp-imx8mq-evk.rst | 124 ++
arch/arm/boards/Makefile | 1 +
arch/arm/boards/nxp-imx8mq-evk/.gitignore | 1 +
arch/arm/boards/nxp-imx8mq-evk/Makefile | 10 +
arch/arm/boards/nxp-imx8mq-evk/board.c | 44 +
arch/arm/boards/nxp-imx8mq-evk/ddr.h | 559 +++++++++
arch/arm/boards/nxp-imx8mq-evk/ddr_init.c | 223 ++++
arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c | 1026 +++++++++++++++++
.../flash-header-imx8mq-evk.imxcfg | 4 +
arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 81 ++
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx8mq-evk.dts | 444 +++++++
arch/arm/mach-imx/Kconfig | 4 +
images/Makefile.imx | 7 +
scripts/Makefile.lib | 22 +
16 files changed, 2560 insertions(+), 1 deletion(-)
create mode 100644 Documentation/boards/imx/nxp-imx8mq-evk.rst
create mode 100644 arch/arm/boards/nxp-imx8mq-evk/.gitignore
create mode 100644 arch/arm/boards/nxp-imx8mq-evk/Makefile
create mode 100644 arch/arm/boards/nxp-imx8mq-evk/board.c
create mode 100644 arch/arm/boards/nxp-imx8mq-evk/ddr.h
create mode 100644 arch/arm/boards/nxp-imx8mq-evk/ddr_init.c
create mode 100644 arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c
create mode 100644 arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg
create mode 100644 arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
create mode 100644 arch/arm/dts/imx8mq-evk.dts
diff --git a/Documentation/boards/imx.rst b/Documentation/boards/imx.rst
index 196513520..9ceb68bef 100644
--- a/Documentation/boards/imx.rst
+++ b/Documentation/boards/imx.rst
@@ -38,12 +38,19 @@ SD card::
# otherwise:
cat barebox-flash-image > /dev/sdd
+NOTE: Commands above will not work on i.MX8
+
The above will overwrite the MBR (and consequently the partition table)
on the destination SD card. To preserve the MBR while writing the rest
of the image to the card, use::
dd if=images/barebox-freescale-imx51-babbage.img of=/dev/sdd bs=1024 skip=1 seek=1
+NOTE: MaskROM on i.MX8 expects image to start at +33KiB mark, so the
+following command has to be used instead:
+
+ dd if=images/barebox-nxp-imx8mq-evk.img of=/dev/sdd bs=1024 skip=1 seek=33
+
The images can also always be started second stage::
bootm /mnt/tftp/barebox-freescale-imx51-babbage.img
@@ -59,7 +66,8 @@ options in this file are:
Header:
+----------------+--------------------------------------------------------------+
-| soc <soctype> | soctype can be one of imx35, imx51, imx53, imx6, imx7, vf610 |
+| soc <soctype> |soctype can be one of imx35, imx51, imx53, imx6, imx7, vf610, |
+| | imx8 |
+----------------+--------------------------------------------------------------+
| loadaddr <adr> | The address the binary is uploaded to |
+----------------+--------------------------------------------------------------+
diff --git a/Documentation/boards/imx/nxp-imx8mq-evk.rst b/Documentation/boards/imx/nxp-imx8mq-evk.rst
new file mode 100644
index 000000000..bf9008061
--- /dev/null
+++ b/Documentation/boards/imx/nxp-imx8mq-evk.rst
@@ -0,0 +1,124 @@
+NXP i.MX8MQ EVK Evaluation Board
+================================
+
+Board comes with:
+
+* 3GiB of LPDDR4 RAM
+* 16GiB eMMC
+
+Not including booting via serial, the device can boot from either SD or eMMC.
+
+Downloading DDR PHY Firmware
+----------------------------
+
+As a part of DDR intialization routine NXP i.MX8MQ EVK requires and
+uses several binary firmware blobs that are distributed under a
+separate EULA and cannot be included in Barebox. In order to obtain
+the do the following::
+
+ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.2.bin
+ chmod +x firmware-imx-7.2.bin
+ ./firmware-imx-7.2.bin
+
+Executing that file should produce a EULA acceptance dialog as well as
+result int the following files:
+
+- lpddr4_pmu_train_1d_dmem.bin
+- lpddr4_pmu_train_1d_imem.bin
+- lpddr4_pmu_train_2d_dmem.bin
+- lpddr4_pmu_train_2d_imem.bin
+
+As a last step of this process those files need to be placed in
+"arch/arm/boards/nxp-imx8mq-evk"::
+
+ for f in lpddr4_pmu_train_1d_dmem \
+ lpddr4_pmu_train_1d_imem \
+ lpddr4_pmu_train_2d_dmem \
+ lpddr4_pmu_train_2d_imem; \
+ do \
+ cp firmware-imx-7.2/firmware/ddr/synopsys/${f}.bin \
+ arch/arm/boards/nxp-imx8mq-evk/${f}.ddr-phy-fw; \
+ done
+
+DDR Configuration Code
+======================
+
+The following two files:
+
+ - ddr_init.c
+ - ddrphy_train.c
+
+were obtained by running i.MX 8M DDR Tool that can be found here:
+
+https://community.nxp.com/docs/DOC-340179
+
+Only minimal amount of necessary changes were made to those files.
+All of the "impedance matching" code is located in "ddr.h".
+
+Build Barebox
+=============
+
+ make imv_v8_defconfig
+ make
+
+Flashing the binary onto the SD card
+====================================
+
+Due to changes to MaskROM behaviour, i.MX8 deviates in this procedure
+slighty and command for placing barebox onto an SD card is as follows::
+
+ dd if=images/barebox-nxp-imx8mq-evk.img of=/dev/sdb bs=1024 skip=1 seek=33
+
+Boot Configuration
+==================
+
+The NXM i.MX8MQ EVK Evaluation Board has has two switches responsible
+for configuring bootsource/boot mode:
+
+ * SW802 for selecting appropriate BMOD
+ * SW801 for selecting appropriate boot medium
+
+In order to select internal boot set SW802 as follows::
+
+ +-----+
+ | |
+ | O | | <--- on = high level
+ | | | |
+ | | O | <--- off = low level
+ | |
+ | 1 2 |
+ +-----+
+
+Bootsource is the internal eMMC::
+
+ +---------+
+ | |
+ | | | O | |
+ | | | | | | <---- eMMC
+ | O O O O |
+ | |
+ | 1 2 3 4 |
+ +---------+
+
+Bootsource is the SD2 slot::
+
+ +---------+
+ | |
+ | O O | | |
+ | | | | | | <---- SD2
+ | | | O O |
+ | |
+ | 1 2 3 4 |
+ +---------+
+
+
+Serial boot SW802 setting needed for i.MX8 DDR Tool is as follows::
+
+ +-----+
+ | |
+ | | O | <--- on = high level
+ | | | |
+ | O | | <--- off = low level
+ | |
+ | 1 2 |
+ +-----+
\ No newline at end of file
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index b2fea4a40..711f9548f 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -80,6 +80,7 @@ obj-$(CONFIG_MACH_NVIDIA_BEAVER) += nvidia-beaver/
obj-$(CONFIG_MACH_NVIDIA_JETSON) += nvidia-jetson-tk1/
obj-$(CONFIG_MACH_NXDB500) += netx/
obj-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += nxp-imx6ull-evk/
+obj-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += nxp-imx8mq-evk/
obj-$(CONFIG_MACH_OMAP343xSDP) += omap343xdsp/
obj-$(CONFIG_MACH_OMAP3EVM) += omap3evm/
obj-$(CONFIG_MACH_PANDA) += panda/
diff --git a/arch/arm/boards/nxp-imx8mq-evk/.gitignore b/arch/arm/boards/nxp-imx8mq-evk/.gitignore
new file mode 100644
index 000000000..ef13747c9
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mq-evk/.gitignore
@@ -0,0 +1 @@
+*.ddr-phy-fw*
diff --git a/arch/arm/boards/nxp-imx8mq-evk/Makefile b/arch/arm/boards/nxp-imx8mq-evk/Makefile
new file mode 100644
index 000000000..c94a10dec
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mq-evk/Makefile
@@ -0,0 +1,10 @@
+obj-y += board.o
+lwl-y += lowlevel.o ddr_init.o ddrphy_train.o
+
+pbl-y += lpddr4_pmu_train_1d_dmem.ddr-phy-fw.o
+pbl-y += lpddr4_pmu_train_1d_imem.ddr-phy-fw.o
+pbl-y += lpddr4_pmu_train_2d_dmem.ddr-phy-fw.o
+pbl-y += lpddr4_pmu_train_2d_imem.ddr-phy-fw.o
+
+
+
diff --git a/arch/arm/boards/nxp-imx8mq-evk/board.c b/arch/arm/boards/nxp-imx8mq-evk/board.c
new file mode 100644
index 000000000..d93e21da1
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mq-evk/board.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2018 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/memory.h>
+#include <linux/sizes.h>
+
+static int imx8mq_evk_mem_init(void)
+{
+ arm_add_mem_device("ram0", 0x40000000, SZ_2G);
+
+ request_sdram_region("ATF", 0x40000000, SZ_128K);
+
+ return 0;
+}
+mem_initcall(imx8mq_evk_mem_init);
+
+static int nxp_imx8mq_evk_init(void)
+{
+ if (!of_machine_is_compatible("fsl,imx8mq-evk"))
+ return 0;
+
+ barebox_set_hostname("imx8mq-evk");
+
+ return 0;
+}
+device_initcall(nxp_imx8mq_evk_init);
diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddr.h b/arch/arm/boards/nxp-imx8mq-evk/ddr.h
new file mode 100644
index 000000000..056dcbd0c
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mq-evk/ddr.h
@@ -0,0 +1,559 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Zodiac Inflight Innovation
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ *
+ * Varios wrappers and macros needed to intgrate code generated by
+ * i.MX8M DDR Tool into rest of Barebox
+ */
+#include <common.h>
+#include <io.h>
+#include <mach/imx8mq-regs.h>
+#include <mach/imx8-ddrc.h>
+
+/*
+ * Code generated by i.MX8 M DDT Tool doesn't have any prefixes in the
+ * global identifiers below, so in order to avoid symbol name
+ * collisions with other boards we re-name them via a #define
+ */
+#define ddr_init nxp_imx8mq_evk_ddr_init
+#define ddr_cfg_phy nxp_imx8mq_evk_ddr_cfg_phy
+
+void nxp_imx8mq_evk_ddr_init(void);
+
+DDRC_PHY_FIRMWARE_DECLARE(lpddr4_pmu_train_1d_dmem);
+DDRC_PHY_FIRMWARE_DECLARE(lpddr4_pmu_train_1d_imem);
+DDRC_PHY_FIRMWARE_DECLARE(lpddr4_pmu_train_2d_dmem);
+DDRC_PHY_FIRMWARE_DECLARE(lpddr4_pmu_train_2d_imem);
+
+#define FW_1D_IMAGE \
+ DDRC_PHY_FIRMWARE(lpddr4_pmu_train_1d_imem), \
+ DDRC_PHY_FIRMWARE(lpddr4_pmu_train_1d_dmem)
+
+#define FW_2D_IMAGE \
+ DDRC_PHY_FIRMWARE(lpddr4_pmu_train_2d_imem), \
+ DDRC_PHY_FIRMWARE(lpddr4_pmu_train_2d_dmem)
+
+static inline void wait_ddrphy_training_complete(void)
+{
+ ddrc_phy_wait_training_complete(IOMEM(MX8MQ_DDRC_PHY_BASE_ADDR));
+}
+
+static inline void ddr_load_train_code(const u16 *imem, size_t imem_size,
+ const u16 *dmem, size_t dmem_size)
+{
+ void __iomem *phy = IOMEM(MX8MQ_DDRC_PHY_BASE_ADDR);
+
+ ddrc_phy_load_firmware(phy, DDRC_PHY_IMEM, imem, imem_size);
+ ddrc_phy_load_firmware(phy, DDRC_PHY_DMEM, dmem, dmem_size);
+}
+
+#define reg32_write(a, v) writel(v, a)
+#define reg32_read(a) readl(a)
+
+#define DDRC_DDR_SS_GPR0 0x3d000000
+
+#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + (X * 0x2000000))
+#define DDRC_IPS_BASE_ADDR_0 0x3f400000
+
+#define DDRC_MSTR_0 0x3d400000
+#define DDRC_STAT_0 0x3d400004
+#define DDRC_MSTR1_0 0x3d400008
+#define DDRC_MRCTRL0_0 0x3d400010
+#define DDRC_MRCTRL1_0 0x3d400014
+#define DDRC_MRSTAT_0 0x3d400018
+#define DDRC_MRCTRL2_0 0x3d40001c
+#define DDRC_DERATEEN_0 0x3d400020
+#define DDRC_DERATEINT_0 0x3d400024
+#define DDRC_MSTR2_0 0x3d400028
+#define DDRC_PWRCTL_0 0x3d400030
+#define DDRC_PWRTMG_0 0x3d400034
+#define DDRC_HWLPCTL_0 0x3d400038
+#define DDRC_HWFFCCTL_0 0x3d40003c
+#define DDRC_HWFFCSTAT_0 0x3d400040
+#define DDRC_RFSHCTL0_0 0x3d400050
+#define DDRC_RFSHCTL1_0 0x3d400054
+#define DDRC_RFSHCTL2_0 0x3d400058
+#define DDRC_RFSHCTL3_0 0x3d400060
+#define DDRC_RFSHTMG_0 0x3d400064
+#define DDRC_ECCCFG0_0 0x3d400070
+#define DDRC_ECCCFG1_0 0x3d400074
+#define DDRC_ECCSTAT_0 0x3d400078
+#define DDRC_ECCCLR_0 0x3d40007c
+#define DDRC_ECCERRCNT_0 0x3d400080
+#define DDRC_ECCCADDR0_0 0x3d400084
+#define DDRC_ECCCADDR1_0 0x3d400088
+#define DDRC_ECCCSYN0_0 0x3d40008c
+#define DDRC_ECCCSYN1_0 0x3d400090
+#define DDRC_ECCCSYN2_0 0x3d400094
+#define DDRC_ECCBITMASK0_0 0x3d400098
+#define DDRC_ECCBITMASK1_0 0x3d40009c
+#define DDRC_ECCBITMASK2_0 0x3d4000a0
+#define DDRC_ECCUADDR0_0 0x3d4000a4
+#define DDRC_ECCUADDR1_0 0x3d4000a8
+#define DDRC_ECCUSYN0_0 0x3d4000ac
+#define DDRC_ECCUSYN1_0 0x3d4000b0
+#define DDRC_ECCUSYN2_0 0x3d4000b4
+#define DDRC_ECCPOISONADDR0_0 0x3d4000b8
+#define DDRC_ECCPOISONADDR1_0 0x3d4000bc
+#define DDRC_CRCPARCTL0_0 0x3d4000c0
+#define DDRC_CRCPARCTL1_0 0x3d4000c4
+#define DDRC_CRCPARCTL2_0 0x3d4000c8
+#define DDRC_CRCPARSTAT_0 0x3d4000cc
+#define DDRC_INIT0_0 0x3d4000d0
+#define DDRC_INIT1_0 0x3d4000d4
+#define DDRC_INIT2_0 0x3d4000d8
+#define DDRC_INIT3_0 0x3d4000dc
+#define DDRC_INIT4_0 0x3d4000e0
+#define DDRC_INIT5_0 0x3d4000e4
+#define DDRC_INIT6_0 0x3d4000e8
+#define DDRC_INIT7_0 0x3d4000ec
+#define DDRC_DIMMCTL_0 0x3d4000f0
+#define DDRC_RANKCTL_0 0x3d4000f4
+#define DDRC_DRAMTMG0_0 0x3d400100
+#define DDRC_DRAMTMG1_0 0x3d400104
+#define DDRC_DRAMTMG2_0 0x3d400108
+#define DDRC_DRAMTMG3_0 0x3d40010c
+#define DDRC_DRAMTMG4_0 0x3d400110
+#define DDRC_DRAMTMG5_0 0x3d400114
+#define DDRC_DRAMTMG6_0 0x3d400118
+#define DDRC_DRAMTMG7_0 0x3d40011c
+#define DDRC_DRAMTMG8_0 0x3d400120
+#define DDRC_DRAMTMG9_0 0x3d400124
+#define DDRC_DRAMTMG10_0 0x3d400128
+#define DDRC_DRAMTMG11_0 0x3d40012c
+#define DDRC_DRAMTMG12_0 0x3d400130
+#define DDRC_DRAMTMG13_0 0x3d400134
+#define DDRC_DRAMTMG14_0 0x3d400138
+#define DDRC_DRAMTMG15_0 0x3d40013C
+#define DDRC_DRAMTMG16_0 0x3d400140
+#define DDRC_DRAMTMG17_0 0x3d400144
+//
+#define DDRC_ZQCTL0_0 0x3d400180
+#define DDRC_ZQCTL1_0 0x3d400184
+#define DDRC_ZQCTL2_0 0x3d400188
+#define DDRC_ZQSTAT_0 0x3d40018c
+#define DDRC_DFITMG0_0 0x3d400190
+#define DDRC_DFITMG1_0 0x3d400194
+#define DDRC_DFILPCFG0_0 0x3d400198
+#define DDRC_DFILPCFG1_0 0x3d40019c
+#define DDRC_DFIUPD0_0 0x3d4001a0
+#define DDRC_DFIUPD1_0 0x3d4001a4
+#define DDRC_DFIUPD2_0 0x3d4001a8
+//#define DDRC_DFIUPD3(X) ( DDRC_IPS_BASE_ADDR(X) + 0x1ac) // iMX8 hasn't it
+#define DDRC_DFIMISC_0 0x3d4001b0
+#define DDRC_DFITMG2_0 0x3d4001b4
+#define DDRC_DFITMG3_0 0x3d4001b8
+#define DDRC_DFISTAT_0 0x3d4001bc
+//
+#define DDRC_DBICTL_0 0x3d4001c0
+#define DDRC_DFIPHYMSTR_0 0x3d4001c4
+#define DDRC_TRAINCTL0_0 0x3d4001d0
+#define DDRC_TRAINCTL1_0 0x3d4001d4
+#define DDRC_TRAINCTL2_0 0x3d4001d8
+#define DDRC_TRAINSTAT_0 0x3d4001dc
+#define DDRC_ADDRMAP0_0 0x3d400200
+#define DDRC_ADDRMAP1_0 0x3d400204
+#define DDRC_ADDRMAP2_0 0x3d400208
+#define DDRC_ADDRMAP3_0 0x3d40020c
+#define DDRC_ADDRMAP4_0 0x3d400210
+#define DDRC_ADDRMAP5_0 0x3d400214
+#define DDRC_ADDRMAP6_0 0x3d400218
+#define DDRC_ADDRMAP7_0 0x3d40021c
+#define DDRC_ADDRMAP8_0 0x3d400220
+#define DDRC_ADDRMAP9_0 0x3d400224
+#define DDRC_ADDRMAP10_0 0x3d400228
+#define DDRC_ADDRMAP11_0 0x3d40022c
+//
+#define DDRC_ODTCFG_0 0x3d400240
+#define DDRC_ODTMAP_0 0x3d400244
+#define DDRC_SCHED_0 0x3d400250
+#define DDRC_SCHED1_0 0x3d400254
+#define DDRC_PERFHPR1_0 0x3d40025c
+#define DDRC_PERFLPR1_0 0x3d400264
+#define DDRC_PERFWR1_0 0x3d40026c
+#define DDRC_PERFVPR1_0 0x3d400274
+//
+#define DDRC_PERFVPW1_0 0x3d400278
+//
+#define DDRC_DQMAP0_0 0x3d400280
+#define DDRC_DQMAP1_0 0x3d400284
+#define DDRC_DQMAP2_0 0x3d400288
+#define DDRC_DQMAP3_0 0x3d40028c
+#define DDRC_DQMAP4_0 0x3d400290
+#define DDRC_DQMAP5_0 0x3d400294
+#define DDRC_DBG0_0 0x3d400300
+#define DDRC_DBG1_0 0x3d400304
+#define DDRC_DBGCAM_0 0x3d400308
+#define DDRC_DBGCMD_0 0x3d40030c
+#define DDRC_DBGSTAT_0 0x3d400310
+//
+#define DDRC_SWCTL_0 0x3d400320
+#define DDRC_SWSTAT_0 0x3d400324
+#define DDRC_OCPARCFG0_0 0x3d400330
+#define DDRC_OCPARCFG1_0 0x3d400334
+#define DDRC_OCPARCFG2_0 0x3d400338
+#define DDRC_OCPARCFG3_0 0x3d40033c
+#define DDRC_OCPARSTAT0_0 0x3d400340
+#define DDRC_OCPARSTAT1_0 0x3d400344
+#define DDRC_OCPARWLOG0_0 0x3d400348
+#define DDRC_OCPARWLOG1_0 0x3d40034c
+#define DDRC_OCPARWLOG2_0 0x3d400350
+#define DDRC_OCPARAWLOG0_0 0x3d400354
+#define DDRC_OCPARAWLOG1_0 0x3d400358
+#define DDRC_OCPARRLOG0_0 0x3d40035c
+#define DDRC_OCPARRLOG1_0 0x3d400360
+#define DDRC_OCPARARLOG0_0 0x3d400364
+#define DDRC_OCPARARLOG1_0 0x3d400368
+#define DDRC_POISONCFG_0 0x3d40036C
+#define DDRC_POISONSTAT_0 0x3d400370
+#define DDRC_ADVECCINDEX_0 0x3d400003
+#define DDRC_ADVECCSTAT_0 0x3d400003
+#define DDRC_ECCPOISONPAT0_0 0x3d400003
+#define DDRC_ECCPOISONPAT1_0 0x3d400003
+#define DDRC_ECCPOISONPAT2_0 0x3d400003
+#define DDRC_HIFCTL_0 0x3d400003
+
+#define DDRC_PSTAT_0 0x3d4003fc
+#define DDRC_PCCFG_0 0x3d400400
+#define DDRC_PCFGR_0_0 0x3d400404
+#define DDRC_PCFGR_1_0 0x3d4004b4
+#define DDRC_PCFGR_2_0 0x3d400564
+#define DDRC_PCFGR_3_0 0x3d400614
+#define DDRC_PCFGW_0_0 0x3d400408
+#define DDRC_PCFGW_1_0 0x3d400408
+#define DDRC_PCFGW_2_0 0x3d400568
+#define DDRC_PCFGW_3_0 0x3d400618
+#define DDRC_PCFGC_0_0 0x3d40040c
+#define DDRC_PCFGIDMASKCH_0 0x3d400410
+#define DDRC_PCFGIDVALUECH_0 0x3d400414
+#define DDRC_PCTRL_0_0 0x3d400490
+#define DDRC_PCTRL_1_0 0x3d400540
+#define DDRC_PCTRL_2_0 0x3d4005f0
+#define DDRC_PCTRL_3_0 0x3d4006a0
+#define DDRC_PCFGQOS0_0_0 0x3d400494
+#define DDRC_PCFGQOS1_0_0 0x3d400498
+#define DDRC_PCFGWQOS0_0_0 0x3d40049c
+#define DDRC_PCFGWQOS1_0_0 0x3d4004a0
+#define DDRC_SARBASE0_0 0x3d400f04
+#define DDRC_SARSIZE0_0 0x3d400f08
+#define DDRC_SBRCTL_0 0x3d400f24
+#define DDRC_SBRSTAT_0 0x3d400f28
+#define DDRC_SBRWDATA0_0 0x3d400f2c
+#define DDRC_SBRWDATA1_0 0x3d400f30
+#define DDRC_PDCH_0 0x3d400f34
+
+/**********************/
+#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00)
+#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04)
+#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08)
+#define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10)
+#define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14)
+#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18)
+#define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c)
+#define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20)
+#define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24)
+#define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28)
+#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30)
+#define DDRC_PWRTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x34)
+#define DDRC_HWLPCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x38)
+#define DDRC_HWFFCCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3c)
+#define DDRC_HWFFCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x40)
+#define DDRC_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x50)
+#define DDRC_RFSHCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x54)
+#define DDRC_RFSHCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x58)
+#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60)
+#define DDRC_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x64)
+#define DDRC_ECCCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x70)
+#define DDRC_ECCCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x74)
+#define DDRC_ECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x78)
+#define DDRC_ECCCLR(X) (DDRC_IPS_BASE_ADDR(X) + 0x7c)
+#define DDRC_ECCERRCNT(X) (DDRC_IPS_BASE_ADDR(X) + 0x80)
+#define DDRC_ECCCADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0x84)
+#define DDRC_ECCCADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x88)
+#define DDRC_ECCCSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0x8c)
+#define DDRC_ECCCSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0x90)
+#define DDRC_ECCCSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0x94)
+#define DDRC_ECCBITMASK0(X) (DDRC_IPS_BASE_ADDR(X) + 0x98)
+#define DDRC_ECCBITMASK1(X) (DDRC_IPS_BASE_ADDR(X) + 0x9c)
+#define DDRC_ECCBITMASK2(X) (DDRC_IPS_BASE_ADDR(X) + 0xa0)
+#define DDRC_ECCUADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xa4)
+#define DDRC_ECCUADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xa8)
+#define DDRC_ECCUSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0xac)
+#define DDRC_ECCUSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0xb0)
+#define DDRC_ECCUSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0xb4)
+#define DDRC_ECCPOISONADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xb8)
+#define DDRC_ECCPOISONADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xbc)
+#define DDRC_CRCPARCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0xc0)
+#define DDRC_CRCPARCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0xc4)
+#define DDRC_CRCPARCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0xc8)
+#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc)
+#define DDRC_INIT0(X) (DDRC_IPS_BASE_ADDR(X) + 0xd0)
+#define DDRC_INIT1(X) (DDRC_IPS_BASE_ADDR(X) + 0xd4)
+#define DDRC_INIT2(X) (DDRC_IPS_BASE_ADDR(X) + 0xd8)
+#define DDRC_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0xdc)
+#define DDRC_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0xe0)
+#define DDRC_INIT5(X) (DDRC_IPS_BASE_ADDR(X) + 0xe4)
+#define DDRC_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0xe8)
+#define DDRC_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0xec)
+#define DDRC_DIMMCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf0)
+#define DDRC_RANKCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf4)
+#define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100)
+#define DDRC_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x104)
+#define DDRC_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x108)
+#define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c)
+#define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110)
+#define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114)
+#define DDRC_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x118)
+#define DDRC_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x11c)
+#define DDRC_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x120)
+#define DDRC_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x124)
+#define DDRC_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x128)
+#define DDRC_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x12c)
+#define DDRC_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x130)
+#define DDRC_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x134)
+#define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138)
+#define DDRC_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x13C)
+#define DDRC_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x140)
+#define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144)
+//
+#define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180)
+#define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184)
+#define DDRC_ZQCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x188)
+#define DDRC_ZQSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18c)
+#define DDRC_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x190)
+#define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194)
+#define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198)
+#define DDRC_DFILPCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x19c)
+#define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0)
+#define DDRC_DFIUPD1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a4)
+#define DDRC_DFIUPD2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a8)
+//#define DDRC_DFIUPD3(X) ( DDRC_IPS_BASE_ADDR(X) + 0x1ac) // iMX8 hasn't it
+#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0)
+#define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4)
+#define DDRC_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b8)
+#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc)
+//
+#define DDRC_DBICTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c0)
+#define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4)
+#define DDRC_TRAINCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d0)
+#define DDRC_TRAINCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d4)
+#define DDRC_TRAINCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d8)
+#define DDRC_TRAINSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1dc)
+#define DDRC_ADDRMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x200)
+#define DDRC_ADDRMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x204)
+#define DDRC_ADDRMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x208)
+#define DDRC_ADDRMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20c)
+#define DDRC_ADDRMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x210)
+#define DDRC_ADDRMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x214)
+#define DDRC_ADDRMAP6(X) (DDRC_IPS_BASE_ADDR(X) + 0x218)
+#define DDRC_ADDRMAP7(X) (DDRC_IPS_BASE_ADDR(X) + 0x21c)
+#define DDRC_ADDRMAP8(X) (DDRC_IPS_BASE_ADDR(X) + 0x220)
+#define DDRC_ADDRMAP9(X) (DDRC_IPS_BASE_ADDR(X) + 0x224)
+#define DDRC_ADDRMAP10(X) (DDRC_IPS_BASE_ADDR(X) + 0x228)
+#define DDRC_ADDRMAP11(X) (DDRC_IPS_BASE_ADDR(X) + 0x22c)
+//
+#define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240)
+#define DDRC_ODTMAP(X) (DDRC_IPS_BASE_ADDR(X) + 0x244)
+#define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250)
+#define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254)
+#define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c)
+#define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264)
+#define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c)
+#define DDRC_PERFVPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x274)
+//
+#define DDRC_PERFVPW1(X) (DDRC_IPS_BASE_ADDR(X) + 0x278)
+//
+#define DDRC_DQMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x280)
+#define DDRC_DQMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x284)
+#define DDRC_DQMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x288)
+#define DDRC_DQMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x28c)
+#define DDRC_DQMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x290)
+#define DDRC_DQMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x294)
+#define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300)
+#define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304)
+#define DDRC_DBGCAM(X) (DDRC_IPS_BASE_ADDR(X) + 0x308)
+#define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c)
+#define DDRC_DBGSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x310)
+//
+#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320)
+#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324)
+#define DDRC_OCPARCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x330)
+#define DDRC_OCPARCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x334)
+#define DDRC_OCPARCFG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x338)
+#define DDRC_OCPARCFG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x33c)
+#define DDRC_OCPARSTAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x340)
+#define DDRC_OCPARSTAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x344)
+#define DDRC_OCPARWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x348)
+#define DDRC_OCPARWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x34c)
+#define DDRC_OCPARWLOG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x350)
+#define DDRC_OCPARAWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x354)
+#define DDRC_OCPARAWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x358)
+#define DDRC_OCPARRLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x35c)
+#define DDRC_OCPARRLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x360)
+#define DDRC_OCPARARLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x364)
+#define DDRC_OCPARARLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x368)
+#define DDRC_POISONCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x36C)
+#define DDRC_POISONSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x370)
+#define DDRC_ADVECCINDEX(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_ADVECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_ECCPOISONPAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_ECCPOISONPAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_ECCPOISONPAT2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_HIFCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
+
+#define DDRC_PSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3fc)
+#define DDRC_PCCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x400)
+#define DDRC_PCFGR_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x404)
+#define DDRC_PCFGR_1(X) (DDRC_IPS_BASE_ADDR(X) + 1*0xb0+0x404)
+#define DDRC_PCFGR_2(X) (DDRC_IPS_BASE_ADDR(X) + 2*0xb0+0x404)
+#define DDRC_PCFGR_3(X) (DDRC_IPS_BASE_ADDR(X) + 3*0xb0+0x404)
+#define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408)
+#define DDRC_PCFGW_1(X) (DDRC_IPS_BASE_ADDR(X) + 1*0xb0+0x408)
+#define DDRC_PCFGW_2(X) (DDRC_IPS_BASE_ADDR(X) + 2*0xb0+0x408)
+#define DDRC_PCFGW_3(X) (DDRC_IPS_BASE_ADDR(X) + 3*0xb0+0x408)
+#define DDRC_PCFGC_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x40c)
+#define DDRC_PCFGIDMASKCH(X) (DDRC_IPS_BASE_ADDR(X) + 0x410)
+#define DDRC_PCFGIDVALUECH(X) (DDRC_IPS_BASE_ADDR(X) + 0x414)
+#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490)
+#define DDRC_PCTRL_1(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1*0xb0)
+#define DDRC_PCTRL_2(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2*0xb0)
+#define DDRC_PCTRL_3(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3*0xb0)
+#define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494)
+#define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498)
+#define DDRC_PCFGWQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x49c)
+#define DDRC_PCFGWQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4a0)
+#define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04)
+#define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08)
+#define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24)
+#define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28)
+#define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c)
+#define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30)
+#define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34)
+/*
+#define DDRC_PCFGW_0_0_ADDR ((vuint8_t*)&(DDRC_PCFGW_0(0)))
+#define DDRC_PCFGW_0_1_ADDR ((vuint8_t*)&(DDRC_PCFGW_0(1)))
+#define DDRC_PCFGW_0_2_ADDR ((vuint8_t*)&(DDRC_PCFGW_0(2)))
+#define DDRC_PCFGW_0_3_ADDR ((vuint8_t*)&(DDRC_PCFGW_0(3)))
+
+#define DDRC_MRCTRL1_0_ADDR ((vuint8_t*)&(DDRC_MRCTRL1(0)))
+#define DDRC_MRCTRL1_1_ADDR ((vuint8_t*)&(DDRC_MRCTRL1(1)))
+#define DDRC_MRCTRL1_2_ADDR ((vuint8_t*)&(DDRC_MRCTRL1(2)))
+#define DDRC_FREQ1_MRCTRL1_3_ADDR ((vuint8_t*)&(DDRC_MRCTRL1(3)))
+*/
+
+// SHADOW registers
+
+#define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020)
+#define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024)
+#define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050)
+#define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064)
+#define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc)
+#define DDRC_FREQ1_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e0)
+#define DDRC_FREQ1_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e8)
+#define DDRC_FREQ1_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x20ec)
+#define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100)
+#define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104)
+#define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108)
+#define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c)
+#define DDRC_FREQ1_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x2110)
+#define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114)
+#define DDRC_FREQ1_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x2118)
+#define DDRC_FREQ1_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x211c)
+#define DDRC_FREQ1_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x2120)
+#define DDRC_FREQ1_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x2124)
+#define DDRC_FREQ1_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x2128)
+#define DDRC_FREQ1_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x212c)
+#define DDRC_FREQ1_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x2130)
+#define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134)
+#define DDRC_FREQ1_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x2138)
+#define DDRC_FREQ1_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x213C)
+#define DDRC_FREQ1_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x2140)
+#define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144)
+#define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180)
+#define DDRC_FREQ1_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
+#define DDRC_FREQ1_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
+#define DDRC_FREQ1_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
+#define DDRC_FREQ1_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
+#define DDRC_FREQ1_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
+
+#define DDRC_FREQ2_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x3020)
+#define DDRC_FREQ2_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3024)
+#define DDRC_FREQ2_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3050)
+#define DDRC_FREQ2_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3064)
+#define DDRC_FREQ2_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x30dc)
+#define DDRC_FREQ2_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e0)
+#define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8)
+#define DDRC_FREQ2_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x30ec)
+#define DDRC_FREQ2_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3100)
+#define DDRC_FREQ2_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3104)
+#define DDRC_FREQ2_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3108)
+#define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c)
+#define DDRC_FREQ2_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x3110)
+#define DDRC_FREQ2_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x3114)
+#define DDRC_FREQ2_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x3118)
+#define DDRC_FREQ2_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x311c)
+#define DDRC_FREQ2_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x3120)
+#define DDRC_FREQ2_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x3124)
+#define DDRC_FREQ2_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x3128)
+#define DDRC_FREQ2_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x312c)
+#define DDRC_FREQ2_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x3130)
+#define DDRC_FREQ2_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x3134)
+#define DDRC_FREQ2_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x3138)
+#define DDRC_FREQ2_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x313C)
+#define DDRC_FREQ2_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x3140)
+#define DDRC_FREQ2_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x3144)
+#define DDRC_FREQ2_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3180)
+#define DDRC_FREQ2_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3190)
+#define DDRC_FREQ2_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3194)
+#define DDRC_FREQ2_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b4)
+#define DDRC_FREQ2_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b8)
+#define DDRC_FREQ2_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3240)
+
+#define DDRC_FREQ3_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x4020)
+#define DDRC_FREQ3_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x4024)
+#define DDRC_FREQ3_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4050)
+#define DDRC_FREQ3_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4064)
+#define DDRC_FREQ3_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x40dc)
+#define DDRC_FREQ3_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e0)
+#define DDRC_FREQ3_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e8)
+#define DDRC_FREQ3_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x40ec)
+#define DDRC_FREQ3_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4100)
+#define DDRC_FREQ3_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4104)
+#define DDRC_FREQ3_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x4108)
+#define DDRC_FREQ3_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x410c)
+#define DDRC_FREQ3_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x4110)
+#define DDRC_FREQ3_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x4114)
+#define DDRC_FREQ3_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x4118)
+#define DDRC_FREQ3_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x411c)
+#define DDRC_FREQ3_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x4120)
+#define DDRC_FREQ3_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x4124)
+#define DDRC_FREQ3_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x4128)
+#define DDRC_FREQ3_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x412c)
+#define DDRC_FREQ3_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x4130)
+#define DDRC_FREQ3_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x4134)
+#define DDRC_FREQ3_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x4138)
+#define DDRC_FREQ3_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x413C)
+#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140)
+#if 0
+/*todo fix*/
+#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4144)
+#define DDRC_FREQ3_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140)
+#endif
+#define DDRC_FREQ3_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4180)
+#define DDRC_FREQ3_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4190)
+#define DDRC_FREQ3_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4194)
+#define DDRC_FREQ3_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b4)
+#define DDRC_FREQ3_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b8)
+#define DDRC_FREQ3_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4240)
+#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
+#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
+#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
+#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
+#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
+
+//#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) DDRPHY1_IPS_BASE_ADDR - X*0x00030000
+//#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) 0xbc000000 + (X * 0x2000000)
+//#define DDRPHY_MEM(X) 0xbc000000 + (X * 0x2000000) + 0x50000
+#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000))
+#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000)
diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c
new file mode 100644
index 000000000..81691b2fa
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ * Generated code from MX8_DDR_tool
+ */
+
+#include "ddr.h"
+
+void ddr_cfg_phy(void);
+void ddr_init(void)
+{
+ volatile unsigned int tmp, tmp_t;
+
+ /** Initialize DDR clock and DDRC registers **/
+ reg32_write(0x3038a088,0x7070000);
+ reg32_write(0x3038a084,0x4030000);
+ reg32_write(0x303a00ec,0xffff);
+ tmp=reg32_read(0x303a00f8);
+ tmp |= 0x20;
+ reg32_write(0x303a00f8,tmp);
+ reg32_write(0x30391000,0x8f000000);
+ reg32_write(0x30391004,0x8f000000);
+ reg32_write(0x30360068,0xbbe580);
+ tmp=reg32_read(0x30360060);
+ tmp &= ~0x80;
+ reg32_write(0x30360060,tmp);
+ tmp=reg32_read(0x30360060);
+ tmp |= 0x200;
+ reg32_write(0x30360060,tmp);
+ tmp=reg32_read(0x30360060);
+ tmp &= ~0x20;
+ reg32_write(0x30360060,tmp);
+ tmp=reg32_read(0x30360060);
+ tmp &= ~0x10;
+ reg32_write(0x30360060,tmp);
+ do{
+ tmp=reg32_read(0x30360060);
+ if(tmp&0x80000000) break;
+ }while(1);
+ reg32_write(0x30391000,0x8f000006);
+ reg32_write(0x3d400304,0x1);
+ reg32_write(0x3d400030,0x1);
+ reg32_write(0x3d400000,0x83080020);
+ reg32_write(0x3d400064,0x6100e0);
+ reg32_write(0x3d4000d0,0xc003061c);
+ reg32_write(0x3d4000d4,0x9e0000);
+ reg32_write(0x3d4000dc,0xd4002d);
+ reg32_write(0x3d4000e0,0x310008);
+ reg32_write(0x3d4000e8,0x46004d);
+ reg32_write(0x3d4000ec,0x15004d);
+ reg32_write(0x3d4000f4,0x639);
+ reg32_write(0x3d400100,0x1a201b22);
+ reg32_write(0x3d400104,0x60633);
+ reg32_write(0x3d400108,0x70e1214);
+ reg32_write(0x3d40010c,0xc0c000);
+ reg32_write(0x3d400110,0xf04080f);
+ reg32_write(0x3d400114,0x2040c0c);
+ reg32_write(0x3d400118,0x1010007);
+ reg32_write(0x3d40011c,0x401);
+ reg32_write(0x3d400130,0x20600);
+ reg32_write(0x3d400134,0xc100002);
+ reg32_write(0x3d400138,0xe6);
+ reg32_write(0x3d400144,0xa00050);
+ reg32_write(0x3d400180,0x3200018);
+ reg32_write(0x3d400184,0x28061a8);
+ reg32_write(0x3d400190,0x497820a);
+ reg32_write(0x3d400194,0x80303);
+ reg32_write(0x3d4001b4,0x170a);
+ reg32_write(0x3d4001b0,0x11);
+ reg32_write(0x3d4001a0,0xe0400018);
+ reg32_write(0x3d4001a4,0xdf00e4);
+ reg32_write(0x3d4001a8,0x0);
+ reg32_write(0x3d4001c0,0x1);
+ reg32_write(0x3d4001c4,0x1);
+ reg32_write(0x3d400200,0x15);
+ reg32_write(0x3d40020c,0x0);
+ reg32_write(0x3d400210,0x1f1f);
+ reg32_write(0x3d400204,0x80808);
+ reg32_write(0x3d400214,0x7070707);
+ reg32_write(0x3d400218,0x48080707);
+ reg32_write(0x3d400244,0x0);
+ reg32_write(0x3d400490,0x1);
+ reg32_write(0x3d400250,0x29001f01);
+ reg32_write(0x3d400254,0x2c);
+ reg32_write(0x3d400264,0x900093e7);
+ reg32_write(0x3d40026c,0x2005574);
+ reg32_write(0x3d400400,0x400);
+ reg32_write(0x3d400408,0x72ff);
+ reg32_write(0x3d400494,0x10e00);
+ reg32_write(0x3d400498,0x620096);
+ reg32_write(0x3d40049c,0x10e00);
+ reg32_write(0x3d4004a0,0x12c);
+ reg32_write(0x30391000,0x8f000004);
+ reg32_write(0x30391000,0x8f000000);
+ reg32_write(0x3d400304,0x0);
+ reg32_write(0x3d400030,0xa8);
+ reg32_write(0x3d400320,0x0);
+ reg32_write(0x3d000000,0x1);
+ reg32_write(0x3d4001b0,0x10);
+ reg32_write(0x3d402100,0xa040305);
+ reg32_write(0x3d402104,0x30407);
+ reg32_write(0x3d402108,0x203060b);
+ reg32_write(0x3d40210c,0x505000);
+ reg32_write(0x3d402110,0x2040202);
+ reg32_write(0x3d402114,0x2030202);
+ reg32_write(0x3d402118,0x1010004);
+ reg32_write(0x3d40211c,0x301);
+ reg32_write(0x3d402138,0x1d);
+ reg32_write(0x3d402144,0x14000a);
+ reg32_write(0x3d403024,0x30d400);
+ reg32_write(0x3d402050,0x20d040);
+ reg32_write(0x3d402190,0x3818200);
+ reg32_write(0x3d4021b4,0x100);
+ reg32_write(0x3d402064,0xc001c);
+ reg32_write(0x3d4020dc,0x840000);
+ reg32_write(0x3d4020e8,0x46004d);
+ reg32_write(0x3d4020ec,0x15004d);
+ reg32_write(0x3d4020e0,0x310000);
+ reg32_write(0x3d403100,0x6010102);
+ reg32_write(0x3d403104,0x30404);
+ reg32_write(0x3d403108,0x203060b);
+ reg32_write(0x3d40310c,0x505000);
+ reg32_write(0x3d403110,0x2040202);
+ reg32_write(0x3d403114,0x2030202);
+ reg32_write(0x3d403118,0x1010004);
+ reg32_write(0x3d40311c,0x301);
+ reg32_write(0x3d403138,0x8);
+ reg32_write(0x3d403144,0x50003);
+ reg32_write(0x3d403024,0xc3500);
+ reg32_write(0x3d403050,0x20d040);
+ reg32_write(0x3d403190,0x3818200);
+ reg32_write(0x3d4031b4,0x100);
+ reg32_write(0x3d403064,0x30007);
+ reg32_write(0x3d4030dc,0x840000);
+ reg32_write(0x3d4030e8,0x46004d);
+ reg32_write(0x3d4030ec,0x15004d);
+ reg32_write(0x3d4030e0,0x310000);
+ reg32_write(0x3c040280,0x0);
+ reg32_write(0x3c040284,0x1);
+ reg32_write(0x3c040288,0x2);
+ reg32_write(0x3c04028c,0x3);
+ reg32_write(0x3c040290,0x4);
+ reg32_write(0x3c040294,0x5);
+ reg32_write(0x3c040298,0x6);
+ reg32_write(0x3c04029c,0x7);
+ reg32_write(0x3c044280,0x0);
+ reg32_write(0x3c044284,0x1);
+ reg32_write(0x3c044288,0x2);
+ reg32_write(0x3c04428c,0x3);
+ reg32_write(0x3c044290,0x4);
+ reg32_write(0x3c044294,0x5);
+ reg32_write(0x3c044298,0x6);
+ reg32_write(0x3c04429c,0x7);
+ reg32_write(0x3c048280,0x0);
+ reg32_write(0x3c048284,0x1);
+ reg32_write(0x3c048288,0x2);
+ reg32_write(0x3c04828c,0x3);
+ reg32_write(0x3c048290,0x4);
+ reg32_write(0x3c048294,0x5);
+ reg32_write(0x3c048298,0x6);
+ reg32_write(0x3c04829c,0x7);
+ reg32_write(0x3c04c280,0x0);
+ reg32_write(0x3c04c284,0x1);
+ reg32_write(0x3c04c288,0x2);
+ reg32_write(0x3c04c28c,0x3);
+ reg32_write(0x3c04c290,0x4);
+ reg32_write(0x3c04c294,0x5);
+ reg32_write(0x3c04c298,0x6);
+ reg32_write(0x3c04c29c,0x7);
+
+ /* Configure DDR PHY's registers */
+ ddr_cfg_phy();
+
+ reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
+ reg32_write(DDRC_SWCTL(0), 0x0000);
+ /*
+ * ------------------- 9 -------------------
+ * Set DFIMISC.dfi_init_start to 1
+ * -----------------------------------------
+ */
+ reg32_write(DDRC_DFIMISC(0), 0x00000030);
+ reg32_write(DDRC_SWCTL(0), 0x0001);
+
+ /* wait DFISTAT.dfi_init_complete to 1 */
+ tmp_t = 0;
+ while(tmp_t==0){
+ tmp = reg32_read(DDRC_DFISTAT(0));
+ tmp_t = tmp & 0x01;
+ tmp = reg32_read(DDRC_MRSTAT(0));
+ }
+
+ reg32_write(DDRC_SWCTL(0), 0x0000);
+
+ /* clear DFIMISC.dfi_init_complete_en */
+ reg32_write(DDRC_DFIMISC(0), 0x00000010);
+ reg32_write(DDRC_DFIMISC(0), 0x00000011);
+ reg32_write(DDRC_PWRCTL(0), 0x00000088);
+
+ tmp = reg32_read(DDRC_CRCPARSTAT(0));
+ /*
+ * set SWCTL.sw_done to enable quasi-dynamic register
+ * programming outside reset.
+ */
+ reg32_write(DDRC_SWCTL(0), 0x00000001);
+
+ /* wait SWSTAT.sw_done_ack to 1 */
+ while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
+ ;
+
+ /* wait STAT.operating_mode([1:0] for ddr3) to normal state */
+ while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1)
+ ;
+
+ reg32_write(DDRC_PWRCTL(0), 0x00000088);
+ /* reg32_write(DDRC_PWRCTL(0), 0x018a); */
+ tmp = reg32_read(DDRC_CRCPARSTAT(0));
+
+ /* enable port 0 */
+ reg32_write(DDRC_PCTRL_0(0), 0x00000001);
+ tmp = reg32_read(DDRC_CRCPARSTAT(0));
+ reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
+}
\ No newline at end of file
diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c b/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c
new file mode 100644
index 000000000..156d7cf87
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c
@@ -0,0 +1,1026 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "ddr.h"
+
+void ddr_cfg_phy(void) {
+ unsigned int tmp, tmp_t;
+
+ //Init DDRPHY register...
+ reg32_write(0x3c080440,0x2);
+ reg32_write(0x3c080444,0x3);
+ reg32_write(0x3c080448,0x4);
+ reg32_write(0x3c08044c,0x5);
+ reg32_write(0x3c080450,0x0);
+ reg32_write(0x3c080454,0x1);
+ reg32_write(0x3c04017c,0x1ff);
+ reg32_write(0x3c04057c,0x1ff);
+ reg32_write(0x3c04417c,0x1ff);
+ reg32_write(0x3c04457c,0x1ff);
+ reg32_write(0x3c04817c,0x1ff);
+ reg32_write(0x3c04857c,0x1ff);
+ reg32_write(0x3c04c17c,0x1ff);
+ reg32_write(0x3c04c57c,0x1ff);
+ reg32_write(0x3c44017c,0x1ff);
+ reg32_write(0x3c44057c,0x1ff);
+ reg32_write(0x3c44417c,0x1ff);
+ reg32_write(0x3c44457c,0x1ff);
+ reg32_write(0x3c44817c,0x1ff);
+ reg32_write(0x3c44857c,0x1ff);
+ reg32_write(0x3c44c17c,0x1ff);
+ reg32_write(0x3c44c57c,0x1ff);
+ reg32_write(0x3c84017c,0x1ff);
+ reg32_write(0x3c84057c,0x1ff);
+ reg32_write(0x3c84417c,0x1ff);
+ reg32_write(0x3c84457c,0x1ff);
+ reg32_write(0x3c84817c,0x1ff);
+ reg32_write(0x3c84857c,0x1ff);
+ reg32_write(0x3c84c17c,0x1ff);
+ reg32_write(0x3c84c57c,0x1ff);
+ reg32_write(0x3c000154,0x1ff);
+ reg32_write(0x3c004154,0x1ff);
+ reg32_write(0x3c008154,0x1ff);
+ reg32_write(0x3c00c154,0x1ff);
+ reg32_write(0x3c010154,0x1ff);
+ reg32_write(0x3c014154,0x1ff);
+ reg32_write(0x3c018154,0x1ff);
+ reg32_write(0x3c01c154,0x1ff);
+ reg32_write(0x3c020154,0x1ff);
+ reg32_write(0x3c024154,0x1ff);
+ reg32_write(0x3c080314,0x19);
+ reg32_write(0x3c480314,0x7);
+ reg32_write(0x3c880314,0x7);
+ reg32_write(0x3c0800b8,0x2);
+ reg32_write(0x3c4800b8,0x2);
+ reg32_write(0x3c8800b8,0x2);
+ reg32_write(0x3c240810,0x0);
+ reg32_write(0x3c640810,0x0);
+ reg32_write(0x3ca40810,0x0);
+ reg32_write(0x3c080090,0xab);
+ reg32_write(0x3c0800e8,0x0);
+ reg32_write(0x3c480090,0xab);
+ reg32_write(0x3c0800e8,0x0);
+ reg32_write(0x3c880090,0xab);
+ reg32_write(0x3c0800e8,0x0);
+ reg32_write(0x3c080158,0x7);
+ reg32_write(0x3c480158,0xa);
+ reg32_write(0x3c880158,0xa);
+ reg32_write(0x3c040134,0xe00);
+ reg32_write(0x3c040534,0xe00);
+ reg32_write(0x3c044134,0xe00);
+ reg32_write(0x3c044534,0xe00);
+ reg32_write(0x3c048134,0xe00);
+ reg32_write(0x3c048534,0xe00);
+ reg32_write(0x3c04c134,0xe00);
+ reg32_write(0x3c04c534,0xe00);
+ reg32_write(0x3c440134,0xe00);
+ reg32_write(0x3c440534,0xe00);
+ reg32_write(0x3c444134,0xe00);
+ reg32_write(0x3c444534,0xe00);
+ reg32_write(0x3c448134,0xe00);
+ reg32_write(0x3c448534,0xe00);
+ reg32_write(0x3c44c134,0xe00);
+ reg32_write(0x3c44c534,0xe00);
+ reg32_write(0x3c840134,0xe00);
+ reg32_write(0x3c840534,0xe00);
+ reg32_write(0x3c844134,0xe00);
+ reg32_write(0x3c844534,0xe00);
+ reg32_write(0x3c848134,0xe00);
+ reg32_write(0x3c848534,0xe00);
+ reg32_write(0x3c84c134,0xe00);
+ reg32_write(0x3c84c534,0xe00);
+ reg32_write(0x3c040124,0xfbe);
+ reg32_write(0x3c040524,0xfbe);
+ reg32_write(0x3c044124,0xfbe);
+ reg32_write(0x3c044524,0xfbe);
+ reg32_write(0x3c048124,0xfbe);
+ reg32_write(0x3c048524,0xfbe);
+ reg32_write(0x3c04c124,0xfbe);
+ reg32_write(0x3c04c524,0xfbe);
+ reg32_write(0x3c440124,0xfbe);
+ reg32_write(0x3c440524,0xfbe);
+ reg32_write(0x3c444124,0xfbe);
+ reg32_write(0x3c444524,0xfbe);
+ reg32_write(0x3c448124,0xfbe);
+ reg32_write(0x3c448524,0xfbe);
+ reg32_write(0x3c44c124,0xfbe);
+ reg32_write(0x3c44c524,0xfbe);
+ reg32_write(0x3c840124,0xfbe);
+ reg32_write(0x3c840524,0xfbe);
+ reg32_write(0x3c844124,0xfbe);
+ reg32_write(0x3c844524,0xfbe);
+ reg32_write(0x3c848124,0xfbe);
+ reg32_write(0x3c848524,0xfbe);
+ reg32_write(0x3c84c124,0xfbe);
+ reg32_write(0x3c84c524,0xfbe);
+ reg32_write(0x3c00010c,0x63);
+ reg32_write(0x3c00410c,0x63);
+ reg32_write(0x3c00810c,0x63);
+ reg32_write(0x3c00c10c,0x63);
+ reg32_write(0x3c01010c,0x63);
+ reg32_write(0x3c01410c,0x63);
+ reg32_write(0x3c01810c,0x63);
+ reg32_write(0x3c01c10c,0x63);
+ reg32_write(0x3c02010c,0x63);
+ reg32_write(0x3c02410c,0x63);
+ reg32_write(0x3c080060,0x3);
+ reg32_write(0x3c0801d4,0x4);
+ reg32_write(0x3c080140,0x0);
+ reg32_write(0x3c080020,0x320);
+ reg32_write(0x3c480020,0x64);
+ reg32_write(0x3c880020,0x19);
+ reg32_write(0x3c080220,0x9);
+ reg32_write(0x3c0802c8,0xdc);
+ reg32_write(0x3c04010c,0x5a1);
+ reg32_write(0x3c04050c,0x5a1);
+ reg32_write(0x3c04410c,0x5a1);
+ reg32_write(0x3c04450c,0x5a1);
+ reg32_write(0x3c04810c,0x5a1);
+ reg32_write(0x3c04850c,0x5a1);
+ reg32_write(0x3c04c10c,0x5a1);
+ reg32_write(0x3c04c50c,0x5a1);
+ reg32_write(0x3c4802c8,0xdc);
+ reg32_write(0x3c44010c,0x5a1);
+ reg32_write(0x3c44050c,0x5a1);
+ reg32_write(0x3c44410c,0x5a1);
+ reg32_write(0x3c44450c,0x5a1);
+ reg32_write(0x3c44810c,0x5a1);
+ reg32_write(0x3c44850c,0x5a1);
+ reg32_write(0x3c44c10c,0x5a1);
+ reg32_write(0x3c44c50c,0x5a1);
+ reg32_write(0x3c8802c8,0xdc);
+ reg32_write(0x3c84010c,0x5a1);
+ reg32_write(0x3c84050c,0x5a1);
+ reg32_write(0x3c84410c,0x5a1);
+ reg32_write(0x3c84450c,0x5a1);
+ reg32_write(0x3c84810c,0x5a1);
+ reg32_write(0x3c84850c,0x5a1);
+ reg32_write(0x3c84c10c,0x5a1);
+ reg32_write(0x3c84c50c,0x5a1);
+ reg32_write(0x3c0803e8,0x1);
+ reg32_write(0x3c4803e8,0x1);
+ reg32_write(0x3c8803e8,0x1);
+ reg32_write(0x3c080064,0x1);
+ reg32_write(0x3c480064,0x1);
+ reg32_write(0x3c880064,0x1);
+ reg32_write(0x3c0803c0,0x660);
+ reg32_write(0x3c0803c4,0x0);
+ reg32_write(0x3c0803c8,0x4444);
+ reg32_write(0x3c0803cc,0x8888);
+ reg32_write(0x3c0803d0,0x5665);
+ reg32_write(0x3c0803d4,0x0);
+ reg32_write(0x3c0803d8,0x0);
+ reg32_write(0x3c0803dc,0xf000);
+ reg32_write(0x3c080094,0x0);
+ reg32_write(0x3c0800b4,0x0);
+ reg32_write(0x3c4800b4,0x0);
+ reg32_write(0x3c8800b4,0x0);
+ reg32_write(0x3c080180,0x2);
+
+ //enable APB bus to access DDRPHY RAM
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ //load the 1D training image
+ ddr_load_train_code(FW_1D_IMAGE);
+
+ //configure DDRPHY-FW DMEM structure @clock0...
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+
+ //set the PHY input clock to the desired frequency for pstate 0
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x131f);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x15);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x15);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1500);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1500);
+
+ //disable APB bus to access DDRPHY RAM
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ //Reset MPU and run
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+ wait_ddrphy_training_complete();
+
+ //configure DDRPHY-FW DMEM structure @clock1...
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+
+ //set the PHY input clock to the desired frequency for pstate 1
+ reg32_write(0x3038a008,0x7070000);
+ reg32_write(0x3038a004,0x5000000);
+ reg32_write(0x3038a088,0x7070000);
+ reg32_write(0x3038a084,0x2010000);
+ reg32_write(0x303a00ec,0xffff);
+ tmp=reg32_read(0x303a00f8);
+ tmp |= 0x20;
+ reg32_write(0x303a00f8,tmp);
+ reg32_write(0x30389804,0x1000000);
+
+ //enable APB bus to access DDRPHY RAM
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+
+ reg32_write(0x3c150008,0x101);
+ reg32_write(0x3c15000c,0x190);
+ reg32_write(0x3c150020,0x121f);
+ reg32_write(0x3c150064,0x84);
+ reg32_write(0x3c150068,0x31);
+ reg32_write(0x3c15006c,0x4d46);
+ reg32_write(0x3c150070,0x4d08);
+ reg32_write(0x3c150074,0x0);
+ reg32_write(0x3c150078,0x15);
+ reg32_write(0x3c15007c,0x84);
+ reg32_write(0x3c150080,0x31);
+ reg32_write(0x3c150084,0x4d46);
+ reg32_write(0x3c150088,0x4d08);
+ reg32_write(0x3c15008c,0x0);
+ reg32_write(0x3c150090,0x15);
+ reg32_write(0x3c1500c8,0x8400);
+ reg32_write(0x3c1500cc,0x3100);
+ reg32_write(0x3c1500d0,0x4600);
+ reg32_write(0x3c1500d4,0x84d);
+ reg32_write(0x3c1500d8,0x4d);
+ reg32_write(0x3c1500dc,0x1500);
+ reg32_write(0x3c1500e0,0x8400);
+ reg32_write(0x3c1500e4,0x3100);
+ reg32_write(0x3c1500e8,0x4600);
+ reg32_write(0x3c1500ec,0x84d);
+ reg32_write(0x3c1500f0,0x4d);
+ reg32_write(0x3c1500f4,0x1500);
+ reg32_write(0x3c1500f8,0x0);
+
+ //disable APB bus to access DDRPHY RAM
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ //Reset MPU and run
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+ wait_ddrphy_training_complete();
+
+ //configure DDRPHY-FW DMEM structure @clock2...
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+
+ //set the PHY input clock to the desired frequency for pstate 2
+ reg32_write(0x3038a008,0x7070000);
+ reg32_write(0x3038a004,0x2000000);
+ reg32_write(0x3038a088,0x7070000);
+ reg32_write(0x3038a084,0x2010000);
+ reg32_write(0x303a00ec,0xffff);
+ tmp=reg32_read(0x303a00f8);
+ tmp |= 0x20;
+ reg32_write(0x303a00f8,tmp);
+ reg32_write(0x30389804,0x1000000);
+
+ //enable APB bus to access DDRPHY RAM
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+
+ reg32_write(0x3c150008,0x102);
+ reg32_write(0x3c15000c,0x64);
+ reg32_write(0x3c150020,0x121f);
+ reg32_write(0x3c150064,0x84);
+ reg32_write(0x3c150068,0x31);
+ reg32_write(0x3c15006c,0x4d46);
+ reg32_write(0x3c150070,0x4d08);
+ reg32_write(0x3c150074,0x0);
+ reg32_write(0x3c150078,0x15);
+ reg32_write(0x3c15007c,0x84);
+ reg32_write(0x3c150080,0x31);
+ reg32_write(0x3c150084,0x4d46);
+ reg32_write(0x3c150088,0x4d08);
+ reg32_write(0x3c15008c,0x0);
+ reg32_write(0x3c150090,0x15);
+ reg32_write(0x3c1500c8,0x8400);
+ reg32_write(0x3c1500cc,0x3100);
+ reg32_write(0x3c1500d0,0x4600);
+ reg32_write(0x3c1500d4,0x84d);
+ reg32_write(0x3c1500d8,0x4d);
+ reg32_write(0x3c1500dc,0x1500);
+ reg32_write(0x3c1500e0,0x8400);
+ reg32_write(0x3c1500e4,0x3100);
+ reg32_write(0x3c1500e8,0x4600);
+ reg32_write(0x3c1500ec,0x84d);
+ reg32_write(0x3c1500f0,0x4d);
+ reg32_write(0x3c1500f4,0x1500);
+ reg32_write(0x3c1500f8,0x0);
+
+ //disable APB bus to access DDRPHY RAM
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ //Reset MPU and run
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+ wait_ddrphy_training_complete();
+
+ //set the PHY input clock to the desired frequency for pstate 0
+ reg32_write(0x3038a088,0x7070000);
+ reg32_write(0x3038a084,0x4030000);
+ reg32_write(0x303a00ec,0xffff);
+ tmp=reg32_read(0x303a00f8);
+ tmp |= 0x20;
+ reg32_write(0x303a00f8,tmp);
+ reg32_write(0x30360068,0xbbe580);
+ tmp=reg32_read(0x30360060);
+ tmp &= ~0x80;
+ reg32_write(0x30360060,tmp);
+ tmp=reg32_read(0x30360060);
+ tmp |= 0x200;
+ reg32_write(0x30360060,tmp);
+ tmp=reg32_read(0x30360060);
+ tmp &= ~0x20;
+ reg32_write(0x30360060,tmp);
+ tmp=reg32_read(0x30360060);
+ tmp &= ~0x10;
+ reg32_write(0x30360060,tmp);
+ do{
+ tmp=reg32_read(0x30360060);
+ if(tmp&0x80000000) break;
+ }while(1);
+ reg32_write(0x30389808,0x1000000);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+
+
+ //enable APB bus to access DDRPHY RAM
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ //load the 2D training image
+ ddr_load_train_code(FW_2D_IMAGE);
+
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x61);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x100);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x1f7f);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x15);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x15);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1500);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1500);
+
+ //disable APB bus to access DDRPHY RAM
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ //Reset MPU and run
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+ wait_ddrphy_training_complete();
+
+ //Halt MPU
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ //enable APB bus to access DDRPHY RAM
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+
+ //Load firmware PIE image
+ reg32_write(0x3c240000,0x10);
+ reg32_write(0x3c240004,0x400);
+ reg32_write(0x3c240008,0x10e);
+ reg32_write(0x3c24000c,0x0);
+ reg32_write(0x3c240010,0x0);
+ reg32_write(0x3c240014,0x8);
+ reg32_write(0x3c2400a4,0xb);
+ reg32_write(0x3c2400a8,0x480);
+ reg32_write(0x3c2400ac,0x109);
+ reg32_write(0x3c2400b0,0x8);
+ reg32_write(0x3c2400b4,0x448);
+ reg32_write(0x3c2400b8,0x139);
+ reg32_write(0x3c2400bc,0x8);
+ reg32_write(0x3c2400c0,0x478);
+ reg32_write(0x3c2400c4,0x109);
+ reg32_write(0x3c2400c8,0x0);
+ reg32_write(0x3c2400cc,0xe8);
+ reg32_write(0x3c2400d0,0x109);
+ reg32_write(0x3c2400d4,0x2);
+ reg32_write(0x3c2400d8,0x10);
+ reg32_write(0x3c2400dc,0x139);
+ reg32_write(0x3c2400e0,0xf);
+ reg32_write(0x3c2400e4,0x7c0);
+ reg32_write(0x3c2400e8,0x139);
+ reg32_write(0x3c2400ec,0x44);
+ reg32_write(0x3c2400f0,0x630);
+ reg32_write(0x3c2400f4,0x159);
+ reg32_write(0x3c2400f8,0x14f);
+ reg32_write(0x3c2400fc,0x630);
+ reg32_write(0x3c240100,0x159);
+ reg32_write(0x3c240104,0x47);
+ reg32_write(0x3c240108,0x630);
+ reg32_write(0x3c24010c,0x149);
+ reg32_write(0x3c240110,0x4f);
+ reg32_write(0x3c240114,0x630);
+ reg32_write(0x3c240118,0x179);
+ reg32_write(0x3c24011c,0x8);
+ reg32_write(0x3c240120,0xe0);
+ reg32_write(0x3c240124,0x109);
+ reg32_write(0x3c240128,0x0);
+ reg32_write(0x3c24012c,0x7c8);
+ reg32_write(0x3c240130,0x109);
+ reg32_write(0x3c240134,0x0);
+ reg32_write(0x3c240138,0x1);
+ reg32_write(0x3c24013c,0x8);
+ reg32_write(0x3c240140,0x0);
+ reg32_write(0x3c240144,0x45a);
+ reg32_write(0x3c240148,0x9);
+ reg32_write(0x3c24014c,0x0);
+ reg32_write(0x3c240150,0x448);
+ reg32_write(0x3c240154,0x109);
+ reg32_write(0x3c240158,0x40);
+ reg32_write(0x3c24015c,0x630);
+ reg32_write(0x3c240160,0x179);
+ reg32_write(0x3c240164,0x1);
+ reg32_write(0x3c240168,0x618);
+ reg32_write(0x3c24016c,0x109);
+ reg32_write(0x3c240170,0x40c0);
+ reg32_write(0x3c240174,0x630);
+ reg32_write(0x3c240178,0x149);
+ reg32_write(0x3c24017c,0x8);
+ reg32_write(0x3c240180,0x4);
+ reg32_write(0x3c240184,0x48);
+ reg32_write(0x3c240188,0x4040);
+ reg32_write(0x3c24018c,0x630);
+ reg32_write(0x3c240190,0x149);
+ reg32_write(0x3c240194,0x0);
+ reg32_write(0x3c240198,0x4);
+ reg32_write(0x3c24019c,0x48);
+ reg32_write(0x3c2401a0,0x40);
+ reg32_write(0x3c2401a4,0x630);
+ reg32_write(0x3c2401a8,0x149);
+ reg32_write(0x3c2401ac,0x10);
+ reg32_write(0x3c2401b0,0x4);
+ reg32_write(0x3c2401b4,0x18);
+ reg32_write(0x3c2401b8,0x0);
+ reg32_write(0x3c2401bc,0x4);
+ reg32_write(0x3c2401c0,0x78);
+ reg32_write(0x3c2401c4,0x549);
+ reg32_write(0x3c2401c8,0x630);
+ reg32_write(0x3c2401cc,0x159);
+ reg32_write(0x3c2401d0,0xd49);
+ reg32_write(0x3c2401d4,0x630);
+ reg32_write(0x3c2401d8,0x159);
+ reg32_write(0x3c2401dc,0x94a);
+ reg32_write(0x3c2401e0,0x630);
+ reg32_write(0x3c2401e4,0x159);
+ reg32_write(0x3c2401e8,0x441);
+ reg32_write(0x3c2401ec,0x630);
+ reg32_write(0x3c2401f0,0x149);
+ reg32_write(0x3c2401f4,0x42);
+ reg32_write(0x3c2401f8,0x630);
+ reg32_write(0x3c2401fc,0x149);
+ reg32_write(0x3c240200,0x1);
+ reg32_write(0x3c240204,0x630);
+ reg32_write(0x3c240208,0x149);
+ reg32_write(0x3c24020c,0x0);
+ reg32_write(0x3c240210,0xe0);
+ reg32_write(0x3c240214,0x109);
+ reg32_write(0x3c240218,0xa);
+ reg32_write(0x3c24021c,0x10);
+ reg32_write(0x3c240220,0x109);
+ reg32_write(0x3c240224,0x9);
+ reg32_write(0x3c240228,0x3c0);
+ reg32_write(0x3c24022c,0x149);
+ reg32_write(0x3c240230,0x9);
+ reg32_write(0x3c240234,0x3c0);
+ reg32_write(0x3c240238,0x159);
+ reg32_write(0x3c24023c,0x18);
+ reg32_write(0x3c240240,0x10);
+ reg32_write(0x3c240244,0x109);
+ reg32_write(0x3c240248,0x0);
+ reg32_write(0x3c24024c,0x3c0);
+ reg32_write(0x3c240250,0x109);
+ reg32_write(0x3c240254,0x18);
+ reg32_write(0x3c240258,0x4);
+ reg32_write(0x3c24025c,0x48);
+ reg32_write(0x3c240260,0x18);
+ reg32_write(0x3c240264,0x4);
+ reg32_write(0x3c240268,0x58);
+ reg32_write(0x3c24026c,0xa);
+ reg32_write(0x3c240270,0x10);
+ reg32_write(0x3c240274,0x109);
+ reg32_write(0x3c240278,0x2);
+ reg32_write(0x3c24027c,0x10);
+ reg32_write(0x3c240280,0x109);
+ reg32_write(0x3c240284,0x5);
+ reg32_write(0x3c240288,0x7c0);
+ reg32_write(0x3c24028c,0x109);
+ reg32_write(0x3c240290,0x10);
+ reg32_write(0x3c240294,0x10);
+ reg32_write(0x3c240298,0x109);
+ reg32_write(0x3c100000,0x811);
+ reg32_write(0x3c100080,0x880);
+ reg32_write(0x3c100100,0x0);
+ reg32_write(0x3c100180,0x0);
+ reg32_write(0x3c100004,0x4008);
+ reg32_write(0x3c100084,0x83);
+ reg32_write(0x3c100104,0x4f);
+ reg32_write(0x3c100184,0x0);
+ reg32_write(0x3c100008,0x4040);
+ reg32_write(0x3c100088,0x83);
+ reg32_write(0x3c100108,0x51);
+ reg32_write(0x3c100188,0x0);
+ reg32_write(0x3c10000c,0x811);
+ reg32_write(0x3c10008c,0x880);
+ reg32_write(0x3c10010c,0x0);
+ reg32_write(0x3c10018c,0x0);
+ reg32_write(0x3c100010,0x720);
+ reg32_write(0x3c100090,0xf);
+ reg32_write(0x3c100110,0x1740);
+ reg32_write(0x3c100190,0x0);
+ reg32_write(0x3c100014,0x16);
+ reg32_write(0x3c100094,0x83);
+ reg32_write(0x3c100114,0x4b);
+ reg32_write(0x3c100194,0x0);
+ reg32_write(0x3c100018,0x716);
+ reg32_write(0x3c100098,0xf);
+ reg32_write(0x3c100118,0x2001);
+ reg32_write(0x3c100198,0x0);
+ reg32_write(0x3c10001c,0x716);
+ reg32_write(0x3c10009c,0xf);
+ reg32_write(0x3c10011c,0x2800);
+ reg32_write(0x3c10019c,0x0);
+ reg32_write(0x3c100020,0x716);
+ reg32_write(0x3c1000a0,0xf);
+ reg32_write(0x3c100120,0xf00);
+ reg32_write(0x3c1001a0,0x0);
+ reg32_write(0x3c100024,0x720);
+ reg32_write(0x3c1000a4,0xf);
+ reg32_write(0x3c100124,0x1400);
+ reg32_write(0x3c1001a4,0x0);
+ reg32_write(0x3c100028,0xe08);
+ reg32_write(0x3c1000a8,0xc15);
+ reg32_write(0x3c100128,0x0);
+ reg32_write(0x3c1001a8,0x0);
+ reg32_write(0x3c10002c,0x623);
+ reg32_write(0x3c1000ac,0x15);
+ reg32_write(0x3c10012c,0x0);
+ reg32_write(0x3c1001ac,0x0);
+ reg32_write(0x3c100030,0x4028);
+ reg32_write(0x3c1000b0,0x80);
+ reg32_write(0x3c100130,0x0);
+ reg32_write(0x3c1001b0,0x0);
+ reg32_write(0x3c100034,0xe08);
+ reg32_write(0x3c1000b4,0xc1a);
+ reg32_write(0x3c100134,0x0);
+ reg32_write(0x3c1001b4,0x0);
+ reg32_write(0x3c100038,0x623);
+ reg32_write(0x3c1000b8,0x1a);
+ reg32_write(0x3c100138,0x0);
+ reg32_write(0x3c1001b8,0x0);
+ reg32_write(0x3c10003c,0x4040);
+ reg32_write(0x3c1000bc,0x80);
+ reg32_write(0x3c10013c,0x0);
+ reg32_write(0x3c1001bc,0x0);
+ reg32_write(0x3c100040,0x2604);
+ reg32_write(0x3c1000c0,0x15);
+ reg32_write(0x3c100140,0x0);
+ reg32_write(0x3c1001c0,0x0);
+ reg32_write(0x3c100044,0x708);
+ reg32_write(0x3c1000c4,0x5);
+ reg32_write(0x3c100144,0x0);
+ reg32_write(0x3c1001c4,0x2002);
+ reg32_write(0x3c100048,0x8);
+ reg32_write(0x3c1000c8,0x80);
+ reg32_write(0x3c100148,0x0);
+ reg32_write(0x3c1001c8,0x0);
+ reg32_write(0x3c10004c,0x2604);
+ reg32_write(0x3c1000cc,0x1a);
+ reg32_write(0x3c10014c,0x0);
+ reg32_write(0x3c1001cc,0x0);
+ reg32_write(0x3c100050,0x708);
+ reg32_write(0x3c1000d0,0xa);
+ reg32_write(0x3c100150,0x0);
+ reg32_write(0x3c1001d0,0x2002);
+ reg32_write(0x3c100054,0x4040);
+ reg32_write(0x3c1000d4,0x80);
+ reg32_write(0x3c100154,0x0);
+ reg32_write(0x3c1001d4,0x0);
+ reg32_write(0x3c100058,0x60a);
+ reg32_write(0x3c1000d8,0x15);
+ reg32_write(0x3c100158,0x1200);
+ reg32_write(0x3c1001d8,0x0);
+ reg32_write(0x3c10005c,0x61a);
+ reg32_write(0x3c1000dc,0x15);
+ reg32_write(0x3c10015c,0x1300);
+ reg32_write(0x3c1001dc,0x0);
+ reg32_write(0x3c100060,0x60a);
+ reg32_write(0x3c1000e0,0x1a);
+ reg32_write(0x3c100160,0x1200);
+ reg32_write(0x3c1001e0,0x0);
+ reg32_write(0x3c100064,0x642);
+ reg32_write(0x3c1000e4,0x1a);
+ reg32_write(0x3c100164,0x1300);
+ reg32_write(0x3c1001e4,0x0);
+ reg32_write(0x3c100068,0x4808);
+ reg32_write(0x3c1000e8,0x880);
+ reg32_write(0x3c100168,0x0);
+ reg32_write(0x3c1001e8,0x0);
+ reg32_write(0x3c24029c,0x0);
+ reg32_write(0x3c2402a0,0x790);
+ reg32_write(0x3c2402a4,0x11a);
+ reg32_write(0x3c2402a8,0x8);
+ reg32_write(0x3c2402ac,0x7aa);
+ reg32_write(0x3c2402b0,0x2a);
+ reg32_write(0x3c2402b4,0x10);
+ reg32_write(0x3c2402b8,0x7b2);
+ reg32_write(0x3c2402bc,0x2a);
+ reg32_write(0x3c2402c0,0x0);
+ reg32_write(0x3c2402c4,0x7c8);
+ reg32_write(0x3c2402c8,0x109);
+ reg32_write(0x3c2402cc,0x10);
+ reg32_write(0x3c2402d0,0x2a8);
+ reg32_write(0x3c2402d4,0x129);
+ reg32_write(0x3c2402d8,0x8);
+ reg32_write(0x3c2402dc,0x370);
+ reg32_write(0x3c2402e0,0x129);
+ reg32_write(0x3c2402e4,0xa);
+ reg32_write(0x3c2402e8,0x3c8);
+ reg32_write(0x3c2402ec,0x1a9);
+ reg32_write(0x3c2402f0,0xc);
+ reg32_write(0x3c2402f4,0x408);
+ reg32_write(0x3c2402f8,0x199);
+ reg32_write(0x3c2402fc,0x14);
+ reg32_write(0x3c240300,0x790);
+ reg32_write(0x3c240304,0x11a);
+ reg32_write(0x3c240308,0x8);
+ reg32_write(0x3c24030c,0x4);
+ reg32_write(0x3c240310,0x18);
+ reg32_write(0x3c240314,0xe);
+ reg32_write(0x3c240318,0x408);
+ reg32_write(0x3c24031c,0x199);
+ reg32_write(0x3c240320,0x8);
+ reg32_write(0x3c240324,0x8568);
+ reg32_write(0x3c240328,0x108);
+ reg32_write(0x3c24032c,0x18);
+ reg32_write(0x3c240330,0x790);
+ reg32_write(0x3c240334,0x16a);
+ reg32_write(0x3c240338,0x8);
+ reg32_write(0x3c24033c,0x1d8);
+ reg32_write(0x3c240340,0x169);
+ reg32_write(0x3c240344,0x10);
+ reg32_write(0x3c240348,0x8558);
+ reg32_write(0x3c24034c,0x168);
+ reg32_write(0x3c240350,0x70);
+ reg32_write(0x3c240354,0x788);
+ reg32_write(0x3c240358,0x16a);
+ reg32_write(0x3c24035c,0x1ff8);
+ reg32_write(0x3c240360,0x85a8);
+ reg32_write(0x3c240364,0x1e8);
+ reg32_write(0x3c240368,0x50);
+ reg32_write(0x3c24036c,0x798);
+ reg32_write(0x3c240370,0x16a);
+ reg32_write(0x3c240374,0x60);
+ reg32_write(0x3c240378,0x7a0);
+ reg32_write(0x3c24037c,0x16a);
+ reg32_write(0x3c240380,0x8);
+ reg32_write(0x3c240384,0x8310);
+ reg32_write(0x3c240388,0x168);
+ reg32_write(0x3c24038c,0x8);
+ reg32_write(0x3c240390,0xa310);
+ reg32_write(0x3c240394,0x168);
+ reg32_write(0x3c240398,0xa);
+ reg32_write(0x3c24039c,0x408);
+ reg32_write(0x3c2403a0,0x169);
+ reg32_write(0x3c2403a4,0x6e);
+ reg32_write(0x3c2403a8,0x0);
+ reg32_write(0x3c2403ac,0x68);
+ reg32_write(0x3c2403b0,0x0);
+ reg32_write(0x3c2403b4,0x408);
+ reg32_write(0x3c2403b8,0x169);
+ reg32_write(0x3c2403bc,0x0);
+ reg32_write(0x3c2403c0,0x8310);
+ reg32_write(0x3c2403c4,0x168);
+ reg32_write(0x3c2403c8,0x0);
+ reg32_write(0x3c2403cc,0xa310);
+ reg32_write(0x3c2403d0,0x168);
+ reg32_write(0x3c2403d4,0x1ff8);
+ reg32_write(0x3c2403d8,0x85a8);
+ reg32_write(0x3c2403dc,0x1e8);
+ reg32_write(0x3c2403e0,0x68);
+ reg32_write(0x3c2403e4,0x798);
+ reg32_write(0x3c2403e8,0x16a);
+ reg32_write(0x3c2403ec,0x78);
+ reg32_write(0x3c2403f0,0x7a0);
+ reg32_write(0x3c2403f4,0x16a);
+ reg32_write(0x3c2403f8,0x68);
+ reg32_write(0x3c2403fc,0x790);
+ reg32_write(0x3c240400,0x16a);
+ reg32_write(0x3c240404,0x8);
+ reg32_write(0x3c240408,0x8b10);
+ reg32_write(0x3c24040c,0x168);
+ reg32_write(0x3c240410,0x8);
+ reg32_write(0x3c240414,0xab10);
+ reg32_write(0x3c240418,0x168);
+ reg32_write(0x3c24041c,0xa);
+ reg32_write(0x3c240420,0x408);
+ reg32_write(0x3c240424,0x169);
+ reg32_write(0x3c240428,0x58);
+ reg32_write(0x3c24042c,0x0);
+ reg32_write(0x3c240430,0x68);
+ reg32_write(0x3c240434,0x0);
+ reg32_write(0x3c240438,0x408);
+ reg32_write(0x3c24043c,0x169);
+ reg32_write(0x3c240440,0x0);
+ reg32_write(0x3c240444,0x8b10);
+ reg32_write(0x3c240448,0x168);
+ reg32_write(0x3c24044c,0x0);
+ reg32_write(0x3c240450,0xab10);
+ reg32_write(0x3c240454,0x168);
+ reg32_write(0x3c240458,0x0);
+ reg32_write(0x3c24045c,0x1d8);
+ reg32_write(0x3c240460,0x169);
+ reg32_write(0x3c240464,0x80);
+ reg32_write(0x3c240468,0x790);
+ reg32_write(0x3c24046c,0x16a);
+ reg32_write(0x3c240470,0x18);
+ reg32_write(0x3c240474,0x7aa);
+ reg32_write(0x3c240478,0x6a);
+ reg32_write(0x3c24047c,0xa);
+ reg32_write(0x3c240480,0x0);
+ reg32_write(0x3c240484,0x1e9);
+ reg32_write(0x3c240488,0x8);
+ reg32_write(0x3c24048c,0x8080);
+ reg32_write(0x3c240490,0x108);
+ reg32_write(0x3c240494,0xf);
+ reg32_write(0x3c240498,0x408);
+ reg32_write(0x3c24049c,0x169);
+ reg32_write(0x3c2404a0,0xc);
+ reg32_write(0x3c2404a4,0x0);
+ reg32_write(0x3c2404a8,0x68);
+ reg32_write(0x3c2404ac,0x9);
+ reg32_write(0x3c2404b0,0x0);
+ reg32_write(0x3c2404b4,0x1a9);
+ reg32_write(0x3c2404b8,0x0);
+ reg32_write(0x3c2404bc,0x408);
+ reg32_write(0x3c2404c0,0x169);
+ reg32_write(0x3c2404c4,0x0);
+ reg32_write(0x3c2404c8,0x8080);
+ reg32_write(0x3c2404cc,0x108);
+ reg32_write(0x3c2404d0,0x8);
+ reg32_write(0x3c2404d4,0x7aa);
+ reg32_write(0x3c2404d8,0x6a);
+ reg32_write(0x3c2404dc,0x0);
+ reg32_write(0x3c2404e0,0x8568);
+ reg32_write(0x3c2404e4,0x108);
+ reg32_write(0x3c2404e8,0xb7);
+ reg32_write(0x3c2404ec,0x790);
+ reg32_write(0x3c2404f0,0x16a);
+ reg32_write(0x3c2404f4,0x1f);
+ reg32_write(0x3c2404f8,0x0);
+ reg32_write(0x3c2404fc,0x68);
+ reg32_write(0x3c240500,0x8);
+ reg32_write(0x3c240504,0x8558);
+ reg32_write(0x3c240508,0x168);
+ reg32_write(0x3c24050c,0xf);
+ reg32_write(0x3c240510,0x408);
+ reg32_write(0x3c240514,0x169);
+ reg32_write(0x3c240518,0xc);
+ reg32_write(0x3c24051c,0x0);
+ reg32_write(0x3c240520,0x68);
+ reg32_write(0x3c240524,0x0);
+ reg32_write(0x3c240528,0x408);
+ reg32_write(0x3c24052c,0x169);
+ reg32_write(0x3c240530,0x0);
+ reg32_write(0x3c240534,0x8558);
+ reg32_write(0x3c240538,0x168);
+ reg32_write(0x3c24053c,0x8);
+ reg32_write(0x3c240540,0x3c8);
+ reg32_write(0x3c240544,0x1a9);
+ reg32_write(0x3c240548,0x3);
+ reg32_write(0x3c24054c,0x370);
+ reg32_write(0x3c240550,0x129);
+ reg32_write(0x3c240554,0x20);
+ reg32_write(0x3c240558,0x2aa);
+ reg32_write(0x3c24055c,0x9);
+ reg32_write(0x3c240560,0x0);
+ reg32_write(0x3c240564,0x400);
+ reg32_write(0x3c240568,0x10e);
+ reg32_write(0x3c24056c,0x8);
+ reg32_write(0x3c240570,0xe8);
+ reg32_write(0x3c240574,0x109);
+ reg32_write(0x3c240578,0x0);
+ reg32_write(0x3c24057c,0x8140);
+ reg32_write(0x3c240580,0x10c);
+ reg32_write(0x3c240584,0x10);
+ reg32_write(0x3c240588,0x8138);
+ reg32_write(0x3c24058c,0x10c);
+ reg32_write(0x3c240590,0x8);
+ reg32_write(0x3c240594,0x7c8);
+ reg32_write(0x3c240598,0x101);
+ reg32_write(0x3c24059c,0x8);
+ reg32_write(0x3c2405a0,0x0);
+ reg32_write(0x3c2405a4,0x8);
+ reg32_write(0x3c2405a8,0x8);
+ reg32_write(0x3c2405ac,0x448);
+ reg32_write(0x3c2405b0,0x109);
+ reg32_write(0x3c2405b4,0xf);
+ reg32_write(0x3c2405b8,0x7c0);
+ reg32_write(0x3c2405bc,0x109);
+ reg32_write(0x3c2405c0,0x0);
+ reg32_write(0x3c2405c4,0xe8);
+ reg32_write(0x3c2405c8,0x109);
+ reg32_write(0x3c2405cc,0x47);
+ reg32_write(0x3c2405d0,0x630);
+ reg32_write(0x3c2405d4,0x109);
+ reg32_write(0x3c2405d8,0x8);
+ reg32_write(0x3c2405dc,0x618);
+ reg32_write(0x3c2405e0,0x109);
+ reg32_write(0x3c2405e4,0x8);
+ reg32_write(0x3c2405e8,0xe0);
+ reg32_write(0x3c2405ec,0x109);
+ reg32_write(0x3c2405f0,0x0);
+ reg32_write(0x3c2405f4,0x7c8);
+ reg32_write(0x3c2405f8,0x109);
+ reg32_write(0x3c2405fc,0x8);
+ reg32_write(0x3c240600,0x8140);
+ reg32_write(0x3c240604,0x10c);
+ reg32_write(0x3c240608,0x0);
+ reg32_write(0x3c24060c,0x1);
+ reg32_write(0x3c240610,0x8);
+ reg32_write(0x3c240614,0x8);
+ reg32_write(0x3c240618,0x4);
+ reg32_write(0x3c24061c,0x8);
+ reg32_write(0x3c240620,0x8);
+ reg32_write(0x3c240624,0x7c8);
+ reg32_write(0x3c240628,0x101);
+ reg32_write(0x3c240018,0x0);
+ reg32_write(0x3c24001c,0x0);
+ reg32_write(0x3c240020,0x8);
+ reg32_write(0x3c240024,0x0);
+ reg32_write(0x3c240028,0x0);
+ reg32_write(0x3c24002c,0x0);
+ reg32_write(0x3c34039c,0x400);
+ reg32_write(0x3c24005c,0x0);
+ reg32_write(0x3c24007c,0x2a);
+ reg32_write(0x3c240098,0x6a);
+ reg32_write(0x3c100340,0x0);
+ reg32_write(0x3c100344,0x101);
+ reg32_write(0x3c100348,0x105);
+ reg32_write(0x3c10034c,0x107);
+ reg32_write(0x3c100350,0x10f);
+ reg32_write(0x3c100354,0x202);
+ reg32_write(0x3c100358,0x20a);
+ reg32_write(0x3c10035c,0x20b);
+ reg32_write(0x3c0800e8,0x2);
+ reg32_write(0x3c08002c,0x65);
+ reg32_write(0x3c080030,0xc9);
+ reg32_write(0x3c080034,0x7d1);
+ reg32_write(0x3c080038,0x2c);
+ reg32_write(0x3c48002c,0x65);
+ reg32_write(0x3c480030,0xc9);
+ reg32_write(0x3c480034,0x7d1);
+ reg32_write(0x3c480038,0x2c);
+ reg32_write(0x3c88002c,0x65);
+ reg32_write(0x3c880030,0xc9);
+ reg32_write(0x3c880034,0x7d1);
+ reg32_write(0x3c880038,0x2c);
+ reg32_write(0x3c240030,0x0);
+ reg32_write(0x3c240034,0x173);
+ reg32_write(0x3c240038,0x60);
+ reg32_write(0x3c24003c,0x6110);
+ reg32_write(0x3c240040,0x2152);
+ reg32_write(0x3c240044,0xdfbd);
+ reg32_write(0x3c240048,0x60);
+ reg32_write(0x3c24004c,0x6152);
+ reg32_write(0x3c080040,0x5a);
+ reg32_write(0x3c080044,0x3);
+ reg32_write(0x3c480040,0x5a);
+ reg32_write(0x3c480044,0x3);
+ reg32_write(0x3c880040,0x5a);
+ reg32_write(0x3c880044,0x3);
+ reg32_write(0x3c100200,0xe0);
+ reg32_write(0x3c100204,0x12);
+ reg32_write(0x3c100208,0xe0);
+ reg32_write(0x3c10020c,0x12);
+ reg32_write(0x3c100210,0xe0);
+ reg32_write(0x3c100214,0x12);
+ reg32_write(0x3c500200,0xe0);
+ reg32_write(0x3c500204,0x12);
+ reg32_write(0x3c500208,0xe0);
+ reg32_write(0x3c50020c,0x12);
+ reg32_write(0x3c500210,0xe0);
+ reg32_write(0x3c500214,0x12);
+ reg32_write(0x3c900200,0xe0);
+ reg32_write(0x3c900204,0x12);
+ reg32_write(0x3c900208,0xe0);
+ reg32_write(0x3c90020c,0x12);
+ reg32_write(0x3c900210,0xe0);
+ reg32_write(0x3c900214,0x12);
+ reg32_write(0x3c1003f4,0xf);
+ reg32_write(0x3c040044,0x1);
+ reg32_write(0x3c040048,0x1);
+ reg32_write(0x3c04004c,0x180);
+ reg32_write(0x3c040060,0x1);
+ reg32_write(0x3c040008,0x6209);
+ reg32_write(0x3c0402c8,0x1);
+ reg32_write(0x3c0406d0,0x1);
+ reg32_write(0x3c040ad0,0x1);
+ reg32_write(0x3c040ed0,0x1);
+ reg32_write(0x3c0412d0,0x1);
+ reg32_write(0x3c0416d0,0x1);
+ reg32_write(0x3c041ad0,0x1);
+ reg32_write(0x3c041ed0,0x1);
+ reg32_write(0x3c0422d0,0x1);
+ reg32_write(0x3c044044,0x1);
+ reg32_write(0x3c044048,0x1);
+ reg32_write(0x3c04404c,0x180);
+ reg32_write(0x3c044060,0x1);
+ reg32_write(0x3c044008,0x6209);
+ reg32_write(0x3c0442c8,0x1);
+ reg32_write(0x3c0446d0,0x1);
+ reg32_write(0x3c044ad0,0x1);
+ reg32_write(0x3c044ed0,0x1);
+ reg32_write(0x3c0452d0,0x1);
+ reg32_write(0x3c0456d0,0x1);
+ reg32_write(0x3c045ad0,0x1);
+ reg32_write(0x3c045ed0,0x1);
+ reg32_write(0x3c0462d0,0x1);
+ reg32_write(0x3c048044,0x1);
+ reg32_write(0x3c048048,0x1);
+ reg32_write(0x3c04804c,0x180);
+ reg32_write(0x3c048060,0x1);
+ reg32_write(0x3c048008,0x6209);
+ reg32_write(0x3c0482c8,0x1);
+ reg32_write(0x3c0486d0,0x1);
+ reg32_write(0x3c048ad0,0x1);
+ reg32_write(0x3c048ed0,0x1);
+ reg32_write(0x3c0492d0,0x1);
+ reg32_write(0x3c0496d0,0x1);
+ reg32_write(0x3c049ad0,0x1);
+ reg32_write(0x3c049ed0,0x1);
+ reg32_write(0x3c04a2d0,0x1);
+ reg32_write(0x3c04c044,0x1);
+ reg32_write(0x3c04c048,0x1);
+ reg32_write(0x3c04c04c,0x180);
+ reg32_write(0x3c04c060,0x1);
+ reg32_write(0x3c04c008,0x6209);
+ reg32_write(0x3c04c2c8,0x1);
+ reg32_write(0x3c04c6d0,0x1);
+ reg32_write(0x3c04cad0,0x1);
+ reg32_write(0x3c04ced0,0x1);
+ reg32_write(0x3c04d2d0,0x1);
+ reg32_write(0x3c04d6d0,0x1);
+ reg32_write(0x3c04dad0,0x1);
+ reg32_write(0x3c04ded0,0x1);
+ reg32_write(0x3c04e2d0,0x1);
+ reg32_write(0x3c0800e8,0x2);
+ reg32_write(0x3c300200,0x2);
+ //customer Post Train
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020010, 0x0000006a);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x0002001d, 0x00000001);
+ /*
+ * CalBusy.0 =1, indicates the calibrator is actively calibrating.
+ * Wait Calibrating done.
+ */
+ tmp_t = 1;
+ while(tmp_t) {
+ tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20097);
+ tmp_t = tmp & 0x01;
+ }
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0);
+ //disable APB bus to access DDRPHY RAM
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+}
\ No newline at end of file
diff --git a/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg b/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg
new file mode 100644
index 000000000..585f8fe33
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg
@@ -0,0 +1,4 @@
+soc imx8
+
+loadaddr 0x007E1000
+dcdofs 0x400
diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
new file mode 100644
index 000000000..1ed918ee0
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
@@ -0,0 +1,81 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <mach/generic.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <mach/imx8-ccm-regs.h>
+#include <mach/iomux-mx8.h>
+#include <mach/imx8-ddrc.h>
+#include <mach/xload.h>
+#include <io.h>
+#include <debug_ll.h>
+#include <asm/cache.h>
+#include <asm/sections.h>
+#include <asm/mmu.h>
+
+#include "ddr.h"
+
+extern char __dtb_imx8mq_evk_start[];
+
+#define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM)
+
+static void setup_uart(void)
+{
+ void __iomem *iomux = IOMEM(MX8MQ_IOMUXC_BASE_ADDR);
+ void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR);
+
+ writel(CCM_CCGR_SETTINGn_NEEDED(0),
+ ccm + CCM_CCGRn_CLR(CCM_CCGR_UART1));
+ writel(CCM_TARGET_ROOTn_ENABLE | UART1_CLK_ROOT__25M_REF_CLK,
+ ccm + CCM_TARGET_ROOTn(UART1_CLK_ROOT));
+ writel(CCM_CCGR_SETTINGn_NEEDED(0),
+ ccm + CCM_CCGRn_SET(CCM_CCGR_UART1));
+
+ imx_setup_pad(iomux, IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL);
+
+ imx8_uart_setup_ll();
+
+ putc_ll('>');
+}
+
+static void nxp_imx8mq_evk_sram_setup(void)
+{
+ enum bootsource src = BOOTSOURCE_UNKNOWN;
+ int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
+ int ret = -ENOTSUPP;
+
+ ddr_init();
+
+ imx8_get_boot_source(&src, &instance);
+
+ if (src == BOOTSOURCE_MMC)
+ ret = imx8_esdhc_start_image(instance);
+
+ BUG_ON(ret);
+}
+
+ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)
+{
+ arm_cpu_lowlevel_init();
+
+ if (IS_ENABLED(CONFIG_DEBUG_LL))
+ setup_uart();
+
+ if (get_pc() < MX8MQ_DDR_CSD1_BASE_ADDR)
+ nxp_imx8mq_evk_sram_setup();
+
+ barebox_arm_entry(MX8MQ_DDR_CSD1_BASE_ADDR,
+ SZ_2G + SZ_1G, __dtb_imx8mq_evk_start);
+}
+
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b69592e64..10fcfbf1f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -86,6 +86,7 @@ pbl-dtb-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-humm
pbl-dtb-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o
pbl-dtb-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += imx6ul-pico-hobbit.dtb.o
pbl-dtb-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += imx6ull-14x14-evk.dtb.o
+pbl-dtb-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += imx8mq-evk.dtb.o
pbl-dtb-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o
pbl-dtb-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o
pbl-dtb-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o
diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
new file mode 100644
index 000000000..3ac13baa1
--- /dev/null
+++ b/arch/arm/dts/imx8mq-evk.dts
@@ -0,0 +1,444 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017 NXP
+ * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+
+/ {
+ model = "NXP i.MX8MQ EVK";
+ compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000 0 0xc0000000>;
+ };
+
+ reg_usdhc2_vmmc: regulator-vsd-3v3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2>;
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&dcss {
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1_mdc>, <&pinctrl_fec1_mdio>,
+ <&pinctrl_fec1_data_tx>, <&pinctrl_fec1_data_rx>,
+ <&pinctrl_fec1_phy_reset>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&hdmi {
+ status ="okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic@8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x8>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3ab {
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <975000>;
+ regulator-always-on;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1675000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1625000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3625000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};
+
+&ocotp {
+ barebox,provide-mac-address = <&fec1 0x640>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb3_1 {
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1_cd_reset>, <&pinctrl_usdhc1_clk_strobe>,
+ <&pinctrl_usdhc1_data>;
+ pinctrl-1 = <&pinctrl_usdhc1_cd_reset>,
+ <&pinctrl_usdhc1_clk_strobe_100mhz>,
+ <&pinctrl_usdhc1_data_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_cd_reset>,
+ <&pinctrl_usdhc1_clk_strobe_200mhz>,
+ <&pinctrl_usdhc1_data_200mhz>;
+ vqmmc-supply = <&sw4_reg>;
+ bus-width = <8>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2_vselect>, <&pinctrl_usdhc2_clk>,
+ <&pinctrl_usdhc2_data>;
+ pinctrl-1 = <&pinctrl_usdhc2_vselect>, <&pinctrl_usdhc2_clk_100mhz>,
+ <&pinctrl_usdhc2_data_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_vselect>, <&pinctrl_usdhc2_clk_200mhz>,
+ <&pinctrl_usdhc2_data_200mhz>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_fec1_mdc: fec1mdcgrp {
+ pinmux = <MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC>;
+ drive-strength = <3>;
+ slew-rate = <0>;
+ };
+
+ pinctrl_fec1_mdio: fec1mdiogrp {
+ pinmux = <MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO>;
+ drive-strength = <3>;
+ slew-rate = <0>;
+ drive-open-drain;
+ };
+
+ pinctrl_fec1_phy_reset: fec1phyresetgrp {
+ pinmux = <MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9>;
+ drive-strength = <1>;
+ slew-rate = <0>;
+ };
+
+ pinctrl_fec1_data_tx: fec1datatxgrp {
+ pinmux = <
+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3
+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2
+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1
+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0
+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC
+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
+ >;
+ drive-strength = <7>;
+ slew-rate = <3>;
+ };
+
+ pinctrl_fec1_data_rx: fec1datarxgrp {
+ pinmux = <
+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3
+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2
+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1
+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0
+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC
+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL
+ >;
+ drive-strength = <1>;
+ slew-rate = <2>;
+ input-schmitt-enable;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ pinmux = <
+ MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL
+ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA
+ >;
+ drive-strength = <7>;
+ slew-rate = <0>;
+ drive-open-drain;
+ input-enable;
+ };
+
+ pinctrl_reg_usdhc2: regusdhc2grpgpio {
+ pinmux = <MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19>;
+ drive-strength = <1>;
+ slew-rate = <0>;
+ bias-pull-up;
+ };
+
+ pinctrl_uart1: uart1grp {
+ pinmux = <
+ MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX
+ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX
+ >;
+ drive-strength = <1>;
+ slew-rate = <0>;
+ bias-pull-up;
+ };
+
+ pinctrl_usdhc1_cd_reset: usdhc1cdgrp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
+ >;
+ drive-strength = <1>;
+ slew-rate = <0>;
+ bias-pull-up;
+ };
+
+ pinctrl_usdhc1_clk_strobe: usdhc1clkgrp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
+ >;
+ drive-strength = <3>;
+ slew-rate = <0>;
+ };
+
+ pinctrl_usdhc1_data: usdhc1datagrp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
+ >;
+ drive-strength = <3>;
+ slew-rate = <0>;
+ bias-pull-up;
+ input-schmitt-enable;
+ };
+
+ pinctrl_usdhc1_clk_strobe_100mhz: usdhc1clk100grp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
+ >;
+ drive-strength = <3>;
+ slew-rate = <0>;
+ };
+
+ pinctrl_usdhc1_data_100mhz: usdhc1data100grp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
+ >;
+ drive-strength = <5>;
+ slew-rate = <1>;
+ bias-pull-up;
+ input-schmitt-enable;
+ };
+
+ pinctrl_usdhc1_clk_strobe_200mhz: usdhc1clk200grp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
+ >;
+ drive-strength = <7>;
+ slew-rate = <3>;
+ };
+
+ pinctrl_usdhc1_data_200mhz: usdhc1data200grp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
+ >;
+ drive-strength = <7>;
+ slew-rate = <3>;
+ bias-pull-up;
+ input-schmitt-enable;
+ };
+
+ pinctrl_usdhc2_vselect: usdhc2vselectgrp {
+ pinmux = <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT>;
+ drive-strength = <1>;
+ slew-rate = <0>;
+ bias-pull-up;
+ };
+
+ pinctrl_usdhc2_clk: usdhc2clkgrp {
+ pinmux = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK>;
+ drive-strength = <3>;
+ slew-rate = <0>;
+ };
+
+ pinctrl_usdhc2_data: usdhc2datagrp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
+ >;
+ drive-strength = <3>;
+ slew-rate = <0>;
+ bias-pull-up;
+ input-schmitt-enable;
+ };
+
+ pinctrl_usdhc2_clk_100mhz: usdhc2clk100grp {
+ pinmux = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK>;
+ drive-strength = <5>;
+ slew-rate = <1>;
+ };
+
+ pinctrl_usdhc2_data_100mhz: usdhc2data100grp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
+ >;
+ drive-strength = <5>;
+ slew-rate = <1>;
+ bias-pull-up;
+ input-schmitt-enable;
+ };
+
+ pinctrl_usdhc2_clk_200mhz: usdhc2clk200grp {
+ pinmux = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK>;
+ drive-strength = <7>;
+ slew-rate = <3>;
+ };
+
+ pinctrl_usdhc2_data_200mhz: usdhc2data200grp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
+ >;
+ drive-strength = <7>;
+ slew-rate = <3>;
+ bias-pull-up;
+ input-schmitt-enable;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ pinmux = <MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B>;
+ drive-strength = <6>;
+ slew-rate = <0>;
+ bias-pull-up;
+ };
+};
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 020b6fa05..d77f22df2 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -444,6 +444,10 @@ config MACH_NXP_IMX6ULL_EVK
bool "NXP i.MX6ull EVK Board"
select ARCH_IMX6UL
+config MACH_NXP_IMX8MQ_EVK
+ bool "NXP i.MX8MQ EVK Board"
+ select ARCH_IMX8MQ
+
endif
# ----------------------------------------------------------
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 43505b1ff..0550686a1 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -530,7 +530,14 @@ CFG_start_zii_vf610_dev.pblx.imximg = $(board)/zii-vf610-dev/flash-header-zii-vf
FILE_barebox-zii-vf610-dev.img = start_zii_vf610_dev.pblx.imximg
image-$(CONFIG_MACH_ZII_VF610_DEV) += barebox-zii-vf610-dev.img
+# ----------------------- i.MX7 based boards ---------------------------
pblx-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += start_imx7d_sabresd
CFG_start_imx7d_sabresd.pblx.imximg = $(board)/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg
FILE_barebox-freescale-mx7-sabresd.img = start_imx7d_sabresd.pblx.imximg
image-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += barebox-freescale-mx7-sabresd.img
+
+# ----------------------- i.MX8mq based boards --------------------------
+pblx-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += start_nxp_imx8mq_evk
+CFG_start_nxp_imx8mq_evk.imx-sram-img = $(board)/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg
+FILE_barebox-nxp-imx8mq-evk.img = start_nxp_imx8mq_evk.imx-sram-img
+image-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += barebox-nxp-imx8mq-evk.img
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 3024b068e..405ea553a 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -467,3 +467,25 @@ quiet_cmd_b64dec = B64DEC $@
%: %.base64
$(call cmd,b64dec)
+
+#
+# Generate an assembly file to wrap DDR PHY firmware for i.MX8
+#
+extra-y += $(patsubst %.ddr-phy-fw.o,%.ddr-phy-fw.S,$(pbl-y))
+
+quiet_cmd_ddr_phy_fw_S = DDR-PHY-FW.S $@
+cmd_ddr_phy_fw_S = \
+( \
+ echo '\#include <asm-generic/barebox.lds.h>'; \
+ echo '.section .ddr-phy-fw.rodata.$(subst -,_,$(*F)),"a"'; \
+ echo '.balign STRUCT_ALIGNMENT'; \
+ echo '.global __ddr_phy_fw_$(subst -,_,$(*F))_start'; \
+ echo '__ddr_phy_fw_$(subst -,_,$(*F))_start:'; \
+ echo '.incbin "$<" '; \
+ echo '__ddr_phy_fw_$(subst -,_,$(*F))_end:'; \
+ echo '.global __ddr_phy_fw_$(subst -,_,$(*F))_end'; \
+ echo '.balign STRUCT_ALIGNMENT'; \
+) > $@
+
+$(obj)/%.ddr-phy-fw.S: $(src)/%.ddr-phy-fw FORCE
+ $(call if_changed,ddr_phy_fw_S)
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* Re: [PATCH v2 47/48] ARM: i.MX8: Add i.MX8mq EVK support
2018-05-26 20:44 ` [PATCH v2 47/48] ARM: i.MX8: Add i.MX8mq EVK support Andrey Smirnov
@ 2018-05-28 15:51 ` Sascha Hauer
2018-05-28 18:04 ` Andrey Smirnov
2018-05-28 16:04 ` Sascha Hauer
1 sibling, 1 reply; 57+ messages in thread
From: Sascha Hauer @ 2018-05-28 15:51 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: barebox
On Sat, May 26, 2018 at 01:44:50PM -0700, Andrey Smirnov wrote:
> From: Sascha Hauer <s.hauer@pengutronix.de>
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> diff --git a/Documentation/boards/imx.rst b/Documentation/boards/imx.rst
> index 196513520..9ceb68bef 100644
> --- a/Documentation/boards/imx.rst
> +++ b/Documentation/boards/imx.rst
> @@ -38,12 +38,19 @@ SD card::
> # otherwise:
> cat barebox-flash-image > /dev/sdd
>
> +NOTE: Commands above will not work on i.MX8
> +
> The above will overwrite the MBR (and consequently the partition table)
> on the destination SD card. To preserve the MBR while writing the rest
> of the image to the card, use::
>
> dd if=images/barebox-freescale-imx51-babbage.img of=/dev/sdd bs=1024 skip=1 seek=1
>
> +NOTE: MaskROM on i.MX8 expects image to start at +33KiB mark, so the
> +following command has to be used instead:
> +
> + dd if=images/barebox-nxp-imx8mq-evk.img of=/dev/sdd bs=1024 skip=1 seek=33
Why don't you use my version of imx-image which already adds the
necessary offset to the image?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v2 47/48] ARM: i.MX8: Add i.MX8mq EVK support
2018-05-28 15:51 ` Sascha Hauer
@ 2018-05-28 18:04 ` Andrey Smirnov
0 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-28 18:04 UTC (permalink / raw)
To: Sascha Hauer; +Cc: Barebox List
On Mon, May 28, 2018 at 8:51 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Sat, May 26, 2018 at 01:44:50PM -0700, Andrey Smirnov wrote:
>> From: Sascha Hauer <s.hauer@pengutronix.de>
>>
>> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>> ---
>> diff --git a/Documentation/boards/imx.rst b/Documentation/boards/imx.rst
>> index 196513520..9ceb68bef 100644
>> --- a/Documentation/boards/imx.rst
>> +++ b/Documentation/boards/imx.rst
>> @@ -38,12 +38,19 @@ SD card::
>> # otherwise:
>> cat barebox-flash-image > /dev/sdd
>>
>> +NOTE: Commands above will not work on i.MX8
>> +
>> The above will overwrite the MBR (and consequently the partition table)
>> on the destination SD card. To preserve the MBR while writing the rest
>> of the image to the card, use::
>>
>> dd if=images/barebox-freescale-imx51-babbage.img of=/dev/sdd bs=1024 skip=1 seek=1
>>
>> +NOTE: MaskROM on i.MX8 expects image to start at +33KiB mark, so the
>> +following command has to be used instead:
>> +
>> + dd if=images/barebox-nxp-imx8mq-evk.img of=/dev/sdd bs=1024 skip=1 seek=33
>
> Why don't you use my version of imx-image which already adds the
> necessary offset to the image?
I just wasn't aware it existed. I'd love to switch. Where can I find it?
Thanks,
Andrey Smirnov
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v2 47/48] ARM: i.MX8: Add i.MX8mq EVK support
2018-05-26 20:44 ` [PATCH v2 47/48] ARM: i.MX8: Add i.MX8mq EVK support Andrey Smirnov
2018-05-28 15:51 ` Sascha Hauer
@ 2018-05-28 16:04 ` Sascha Hauer
2018-05-28 18:07 ` Andrey Smirnov
1 sibling, 1 reply; 57+ messages in thread
From: Sascha Hauer @ 2018-05-28 16:04 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: barebox
On Sat, May 26, 2018 at 01:44:50PM -0700, Andrey Smirnov wrote:
> From: Sascha Hauer <s.hauer@pengutronix.de>
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> +
> +#define reg32_write(a, v) writel(v, a)
> +#define reg32_read(a) readl(a)
> +
> +#define DDRC_DDR_SS_GPR0 0x3d000000
> +
> +#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + (X * 0x2000000))
> +#define DDRC_IPS_BASE_ADDR_0 0x3f400000
> +
> +#define DDRC_MSTR_0 0x3d400000
> +#define DDRC_STAT_0 0x3d400004
> +#define DDRC_MSTR1_0 0x3d400008
> +#define DDRC_MRCTRL0_0 0x3d400010
These are all i.MX8M register defines, right? They shouldn't live in the
board support.
> diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c
> new file mode 100644
> index 000000000..81691b2fa
> --- /dev/null
> +void ddr_init(void)
> +{
> + tmp=reg32_read(0x30360060);
> + tmp &= ~0x10;
> + reg32_write(0x30360060,tmp);
> + do{
> + tmp=reg32_read(0x30360060);
> + if(tmp&0x80000000) break;
> + }while(1);
> + reg32_write(0x30391000,0x8f000006);
> + reg32_write(0x3d400304,0x1);
> + reg32_write(0x3d400030,0x1);
Do we need the defines anyway when the generated code uses raw adresses
and not the defines?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread* Re: [PATCH v2 47/48] ARM: i.MX8: Add i.MX8mq EVK support
2018-05-28 16:04 ` Sascha Hauer
@ 2018-05-28 18:07 ` Andrey Smirnov
0 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-28 18:07 UTC (permalink / raw)
To: Sascha Hauer; +Cc: Barebox List
On Mon, May 28, 2018 at 9:04 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Sat, May 26, 2018 at 01:44:50PM -0700, Andrey Smirnov wrote:
>> From: Sascha Hauer <s.hauer@pengutronix.de>
>>
>> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
>> ---
>> +
>> +#define reg32_write(a, v) writel(v, a)
>> +#define reg32_read(a) readl(a)
>> +
>> +#define DDRC_DDR_SS_GPR0 0x3d000000
>> +
>> +#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + (X * 0x2000000))
>> +#define DDRC_IPS_BASE_ADDR_0 0x3f400000
>> +
>> +#define DDRC_MSTR_0 0x3d400000
>> +#define DDRC_STAT_0 0x3d400004
>> +#define DDRC_MSTR1_0 0x3d400008
>> +#define DDRC_MRCTRL0_0 0x3d400010
>
> These are all i.MX8M register defines, right? They shouldn't live in the
> board support.
>
Yes, that's right. I placed them here out of concern that
autogenerated code might one day re-name/abandon those constants. But
I can move them into imx8-ddrc.h.
>> diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c
>> new file mode 100644
>> index 000000000..81691b2fa
>> --- /dev/null
>> +void ddr_init(void)
>> +{
>> + tmp=reg32_read(0x30360060);
>> + tmp &= ~0x10;
>> + reg32_write(0x30360060,tmp);
>> + do{
>> + tmp=reg32_read(0x30360060);
>> + if(tmp&0x80000000) break;
>> + }while(1);
>> + reg32_write(0x30391000,0x8f000006);
>> + reg32_write(0x3d400304,0x1);
>> + reg32_write(0x3d400030,0x1);
>
> Do we need the defines anyway when the generated code uses raw adresses
> and not the defines?
Unfortunately the code is a mix of raw addresses and symbolic
constants. We don't need all of them but there is a few that are
required. I'll cull the list while I am moving it to imx8-ddrc.h
Thanks,
Andrey Smirnov
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH v2 48/48] ARM: Introduce imx_v8_defconfig
2018-05-26 20:44 [PATCH v2 00/48] ARM: i.MX8MQ and EVK support Andrey Smirnov
` (46 preceding siblings ...)
2018-05-26 20:44 ` [PATCH v2 47/48] ARM: i.MX8: Add i.MX8mq EVK support Andrey Smirnov
@ 2018-05-26 20:44 ` Andrey Smirnov
47 siblings, 0 replies; 57+ messages in thread
From: Andrey Smirnov @ 2018-05-26 20:44 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Similar to imx_v7_defconfig, add imx_v8_defconfig as a default
configuration encompassing all ARMv8 based i.MX SoCs.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/configs/imx_v8_defconfig | 95 +++++++++++++++++++++++++++++++
1 file changed, 95 insertions(+)
create mode 100644 arch/arm/configs/imx_v8_defconfig
diff --git a/arch/arm/configs/imx_v8_defconfig b/arch/arm/configs/imx_v8_defconfig
new file mode 100644
index 000000000..b5bff512e
--- /dev/null
+++ b/arch/arm/configs/imx_v8_defconfig
@@ -0,0 +1,95 @@
+CONFIG_ARCH_IMX=y
+CONFIG_IMX_MULTI_BOARDS=y
+CONFIG_MACH_NXP_IMX8MQ_EVK=y
+CONFIG_IMX_OCOTP=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_MMU=y
+CONFIG_MALLOC_SIZE=0x0
+CONFIG_MALLOC_TLSF=y
+CONFIG_KALLSYMS=y
+CONFIG_RELOCATABLE=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
+CONFIG_BOOTM_SHOW_TYPE=y
+CONFIG_BOOTM_VERBOSE=y
+CONFIG_BOOTM_INITRD=y
+CONFIG_BOOTM_OFTREE=y
+CONFIG_BOOTM_OFTREE_UIMAGE=y
+CONFIG_BLSPEC=y
+CONFIG_PBL_CONSOLE=y
+CONFIG_CONSOLE_RATP=y
+CONFIG_PARTITION_DISK_EFI=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_RESET_SOURCE=y
+CONFIG_CMD_DMESG=y
+CONFIG_LONGHELP=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_IMD=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MMC_EXTCSD=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_FILETYPE=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_READF=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_MENU=y
+CONFIG_CMD_MENU_MANAGEMENT=y
+CONFIG_CMD_MENUTREE=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_LED_TRIGGER=y
+CONFIG_CMD_WD=y
+CONFIG_CMD_BAREBOX_UPDATE=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIME=y
+CONFIG_OFDEVICE=y
+CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_DRIVER_SPI_IMX=y
+CONFIG_MCI=y
+CONFIG_MCI_MMC_BOOT_PARTITIONS=y
+CONFIG_MCI_IMX_ESDHC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_GPIO_OF=y
+CONFIG_LED_TRIGGERS=y
+CONFIG_EEPROM_AT25=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_IMX=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_ZLIB=y
+CONFIG_LZO_DECOMPRESS=y
--
2.17.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 57+ messages in thread