From: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH 2/2] dove: fix bit layout of DOVE_CPU_CTRL register
Date: Mon, 28 May 2018 23:44:00 +0200 [thread overview]
Message-ID: <20180528214400.28252-2-u.kleine-koenig@pengutronix.de> (raw)
In-Reply-To: <20180528214400.28252-1-u.kleine-koenig@pengutronix.de>
While creating the previous patch I checked the cpu's reference manual
to see what the affected registers actually do and noticed that bits
of the DOVE_CPU_CTRL actually used by the code doesn't match the bits
described as AHBSlaveBase in the manual.
I'm not aware of any effect (neither positive nor negative) of this
patch.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
arch/arm/mach-mvebu/common.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c
index e951bc06276a..83aeb41ae225 100644
--- a/arch/arm/mach-mvebu/common.c
+++ b/arch/arm/mach-mvebu/common.c
@@ -219,8 +219,8 @@ void __naked __noreturn dove_barebox_entry(void *boarddata)
* The AXI units internal space base starts at the same address as the
* DDR controller.
*/
- val = readl(DOVE_CPU_CTRL) & 0xffff0000;
- val |= ((unsigned long)DOVE_SDRAM_BASE & 0xffff0000) >> 16;
+ val = readl(DOVE_CPU_CTRL) & 0xfff007ff;
+ val |= ((unsigned long)DOVE_SDRAM_BASE & 0xff800000) >> 12;
writel(val, DOVE_CPU_CTRL);
barebox_arm_entry(0, dove_memory_find(), boarddata);
--
2.17.0
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next prev parent reply other threads:[~2018-05-28 21:44 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-28 21:43 [PATCH 1/2] dove: move memory controller remapping before RAM detection Uwe Kleine-König
2018-05-28 21:44 ` Uwe Kleine-König [this message]
2018-05-29 12:27 ` [PATCH 2/2] dove: fix bit layout of DOVE_CPU_CTRL register Uwe Kleine-König
2018-05-31 15:18 ` [PATCH 1/2] dove: move memory controller remapping before RAM detection Sascha Hauer
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