From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: barebox@lists.infradead.org
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Subject: [PATCH 14/14] VFxxx: DCD: Remove read leveling and gate training delays
Date: Tue, 12 Jun 2018 11:48:00 -0700 [thread overview]
Message-ID: <20180612184800.4940-15-andrew.smirnov@gmail.com> (raw)
In-Reply-To: <20180612184800.4940-1-andrew.smirnov@gmail.com>
Read leveling delays are being specified as zero, so they are as good
as disabled and can be safely dropped.
Gate training delay is specified as 4/128 tCK for both data
slices. This setting, when applied to Data Byte 1, makes that slice
unusable* during POR startup which is somehow is mitigated by
double-reset hack in DCD.
Dropping gate training delays allows both VF610 Tower board and ZII
VF610 Dev board to sucessfully PoR-boot without the need for double
resetting of the DDRMC.
* The board fails to boot. When examined via JTAG in such a state
only even bytes of DDR memory are functional.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
| 32 -------------------
| 9 ------
| 4 ---
3 files changed, 45 deletions(-)
--git a/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg b/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg
index 553eae25d..71150802b 100644
--- a/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg
+++ b/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg
@@ -13,35 +13,3 @@ dcdofs 0x400
wm 32 DDRMC_CR00 DDRMC_CR00_DRAM_CLASS_DDR3_START
check 32 until_any_bit_set 0x400ae140 0x100
-
-/*
- * Cargo cult DDR controller initialization here we come!
- *
- * Experemintation with VF610 Tower Board shows that without the
- * following code the board would not boot off of SD card when
- * power-cycled. It will however happily boot when reset via SW3/Reset
- * button. For whatever reason the following actions appear to be
- * necessary:
- *
- * - Initialize DDRMC as usual
- * - Issue a read to location in DDR address space
- * - Disable DDRMC
- * - Enable DDRMC and wait for it to finish initializing
- *
- * I am sure this is all going to be extrememly embarrassing to read
- * if/when the real problem and real solution is found.
- */
-
-/*
- * Because there's no standalone read command what we do here instead
- * is write a pattern to memory and then checking that memory address
- * against that pattern
- */
-wm 32 0x80000000 0xa5a5a5a5
-check 32 until_any_bit_set 0x80000000 0xa5a5a5a5
-
-wm 32 0x400ae000 0x00000600
-wm 32 0x400ae000 0x00000601
-
-check 32 until_any_bit_set 0x400ae140 0x100
-
--git a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg
index e03bd9b74..7076a6431 100644
--- a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg
+++ b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg
@@ -25,13 +25,4 @@ wm 32 DDRMC_CR00 DDRMC_CR00_DRAM_CLASS_DDR3_START
check 32 until_any_bit_set 0x400ae140 0x100
-wm 32 0x80000000 0xa5a5a5a5
-check 32 until_any_bit_set 0x80000000 0xa5a5a5a5
-
-wm 32 0x400ae000 0x00000600
-wm 32 0x400ae000 0x00000601
-
-check 32 until_any_bit_set 0x400ae140 0x100
-
-
--git a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg
index 956cc5c58..8c411ddc7 100644
--- a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg
+++ b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg
@@ -107,10 +107,6 @@ wm 32 DDRMC_CR88 0x00040000
wm 32 DDRMC_CR89 0x00000002
wm 32 DDRMC_CR91 0x00020000
wm 32 DDRMC_CR96 0x00002819
-wm 32 DDRMC_CR102 0x00010100
-wm 32 DDRMC_CR105 0x00000000
-wm 32 DDRMC_CR106 0x00000004
-wm 32 DDRMC_CR110 0x00040000
wm 32 DDRMC_CR117 0x00000000
wm 32 DDRMC_CR118 0x01010000
wm 32 DDRMC_CR120 0x02020000
--
2.17.0
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next prev parent reply other threads:[~2018-06-12 18:49 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-12 18:47 [PATCH 00/14] VFxxx DCD fixes and improvements Andrey Smirnov
2018-06-12 18:47 ` [PATCH 01/14] VFxxx: Remove stale code from DCD files Andrey Smirnov
2018-06-12 18:47 ` [PATCH 02/14] VFxxx: Add common header for DDR IOMUX DCD configuration Andrey Smirnov
2018-06-12 18:47 ` [PATCH 03/14] VFxxx: Add common DDR PHY DCD header Andrey Smirnov
2018-06-12 18:47 ` [PATCH 04/14] VFxxx: Add common header for DDR clock setting DCD Andrey Smirnov
2018-06-12 18:47 ` [PATCH 05/14] VFxxx: Add common DCD header for common DDR configuration Andrey Smirnov
2018-06-12 18:47 ` [PATCH 06/14] VFxxx: Reconcile shared DDR DCD configuration with U-Boot Andrey Smirnov
2018-06-12 18:47 ` [PATCH 07/14] VFxxx: Reconcile shared DDR DCD with memory datasheet Andrey Smirnov
2018-06-12 18:47 ` [PATCH 08/14] VFxxx: zii-vf610-dev: Drop most custom DDRMC DCD code Andrey Smirnov
2018-06-12 18:47 ` [PATCH 09/14] VFxxx: Initialize IOMUXC_DUMMY_DDRBYTE1/2 in default DDR DCD Andrey Smirnov
2018-06-12 18:47 ` [PATCH 10/14] VFxxx: Reconcile shared DDR IOMUX DCD with schematic Andrey Smirnov
2018-06-12 18:47 ` [PATCH 11/14] VFxxx: DCD: Remove CR151 initialization Andrey Smirnov
2018-06-12 18:47 ` [PATCH 12/14] VFxxx: DCD: Drop initialization of CR139 - CR148 Andrey Smirnov
2018-06-12 18:47 ` [PATCH 13/14] VFxxx: DCD: Remove CR97, CR98 and CR99 Andrey Smirnov
2018-06-12 18:48 ` Andrey Smirnov [this message]
2018-06-13 7:58 ` [PATCH 00/14] VFxxx DCD fixes and improvements Sascha Hauer
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