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From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: barebox@lists.infradead.org
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Subject: [PATCH v5 37/54] ARM: i.MX8: Add DDRC PHY support code
Date: Tue, 12 Jun 2018 13:52:53 -0700	[thread overview]
Message-ID: <20180612205310.25745-38-andrew.smirnov@gmail.com> (raw)
In-Reply-To: <20180612205310.25745-1-andrew.smirnov@gmail.com>

Add DDRC PHY support code needed to upload DDR training firwmare as
well as to wait for the training process to complete.

Those are needed to support board specific DDR initialization code.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/mach-imx/Makefile                 |   1 +
 arch/arm/mach-imx/imx8-ddrc.c              | 107 +++++++++++++++++++++
 arch/arm/mach-imx/include/mach/imx8-ddrc.h |  66 +++++++++++++
 3 files changed, 174 insertions(+)
 create mode 100644 arch/arm/mach-imx/imx8-ddrc.c
 create mode 100644 arch/arm/mach-imx/include/mach/imx8-ddrc.h

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 442039a27..28fe60dba 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -17,6 +17,7 @@ lwl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o
 obj-$(CONFIG_ARCH_IMX7) += imx7.o
 obj-$(CONFIG_ARCH_VF610) += vf610.o
 obj-$(CONFIG_ARCH_IMX8MQ) += imx8mq.o
+lwl-$(CONFIG_ARCH_IMX8MQ) += imx8-ddrc.o
 obj-$(CONFIG_ARCH_IMX_XLOAD) += xload.o
 obj-$(CONFIG_IMX_IIM)	+= iim.o
 obj-$(CONFIG_NAND_IMX) += nand.o
diff --git a/arch/arm/mach-imx/imx8-ddrc.c b/arch/arm/mach-imx/imx8-ddrc.c
new file mode 100644
index 000000000..18454a915
--- /dev/null
+++ b/arch/arm/mach-imx/imx8-ddrc.c
@@ -0,0 +1,107 @@
+#include <common.h>
+#include <linux/iopoll.h>
+#include <mach/imx8-ddrc.h>
+#include <debug_ll.h>
+
+void ddrc_phy_load_firmware(void __iomem *phy,
+			    enum ddrc_phy_firmware_offset offset,
+			    const u16 *blob, size_t size)
+{
+	while (size) {
+		writew(*blob++, phy + DDRC_PHY_REG(offset));
+		offset++;
+		size -= sizeof(*blob);
+	}
+}
+
+enum pmc_constants {
+	PMC_MESSAGE_ID,
+	PMC_MESSAGE_STREAM,
+
+	PMC_TRAIN_SUCCESS	= 0x07,
+	PMC_TRAIN_STREAM_START	= 0x08,
+	PMC_TRAIN_FAIL		= 0xff,
+};
+
+static u32 ddrc_phy_get_message(void __iomem *phy, int type)
+{
+	u32 r, message;
+
+	/*
+	 * When BIT0 set to 0, the PMU has a message for the user
+	 * 10ms seems not enough for poll message, so use 1s here.
+	 */
+	readl_poll_timeout(phy + DDRC_PHY_REG(0xd0004),
+			   r, !(r & BIT(0)), 0);
+
+	switch (type) {
+	case PMC_MESSAGE_ID:
+		/*
+		 * Get the major message ID
+		 */
+		message = readl(phy + DDRC_PHY_REG(0xd0032));
+		break;
+	case PMC_MESSAGE_STREAM:
+		message = readl(phy + DDRC_PHY_REG(0xd0034));
+		message <<= 16;
+		message |= readl(phy + DDRC_PHY_REG(0xd0032));
+		break;
+	}
+
+	/*
+	 * By setting this register to 0, the user acknowledges the
+	 * receipt of the message.
+	 */
+	writel(0x00000000, phy + DDRC_PHY_REG(0xd0031));
+	/*
+	 * When BIT0 set to 0, the PMU has a message for the user
+	 */
+	readl_poll_timeout(phy + DDRC_PHY_REG(0xd0004),
+			   r, r & BIT(0), 0);
+
+	writel(0x00000001, phy + DDRC_PHY_REG(0xd0031));
+
+	return message;
+}
+
+static void ddrc_phy_fetch_streaming_message(void __iomem *phy)
+{
+	const u16 index = ddrc_phy_get_message(phy, PMC_MESSAGE_STREAM);
+	u16 i;
+
+	putc_ll('|');
+	puthex_ll(index);
+
+	for (i = 0; i < index; i++) {
+		const u32 arg = ddrc_phy_get_message(phy, PMC_MESSAGE_STREAM);
+
+		putc_ll('|');
+		puthex_ll(arg);
+	}
+}
+
+void ddrc_phy_wait_training_complete(void __iomem *phy)
+{
+	for (;;) {
+		const u32 m = ddrc_phy_get_message(phy, PMC_MESSAGE_ID);
+
+		puthex_ll(m);
+
+		switch (m) {
+		case PMC_TRAIN_STREAM_START:
+			ddrc_phy_fetch_streaming_message(phy);
+			break;
+		case PMC_TRAIN_SUCCESS:
+			putc_ll('P');
+			putc_ll('\r');
+			putc_ll('\n');
+			return;
+		case PMC_TRAIN_FAIL:
+			putc_ll('F');
+			hang();
+		}
+
+		putc_ll('\r');
+		putc_ll('\n');
+	}
+}
\ No newline at end of file
diff --git a/arch/arm/mach-imx/include/mach/imx8-ddrc.h b/arch/arm/mach-imx/include/mach/imx8-ddrc.h
new file mode 100644
index 000000000..d49e29f26
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx8-ddrc.h
@@ -0,0 +1,66 @@
+#ifndef __IMX8_DDRC_H__
+#define __IMX8_DDRC_H__
+
+#include <mach/imx8mq-regs.h>
+#include <io.h>
+#include <firmware.h>
+#include <linux/compiler.h>
+
+enum ddrc_phy_firmware_offset {
+	DDRC_PHY_IMEM = 0x00050000U,
+	DDRC_PHY_DMEM = 0x00054000U,
+};
+
+void ddrc_phy_load_firmware(void __iomem *,
+			    enum ddrc_phy_firmware_offset,
+			    const u16 *, size_t);
+
+#define DDRC_PHY_REG(x)	((x) * 4)
+
+void ddrc_phy_wait_training_complete(void __iomem *phy);
+
+
+/*
+ * i.MX8M DDR Tool compatibility layer
+ */
+
+#define reg32_write(a, v)	writel(v, a)
+#define reg32_read(a)		readl(a)
+
+static inline void wait_ddrphy_training_complete(void)
+{
+	ddrc_phy_wait_training_complete(IOMEM(MX8MQ_DDRC_PHY_BASE_ADDR));
+}
+
+#define __ddr_load_train_code(imem, dmem)				\
+	do {								\
+		const u16 *__mem;					\
+		size_t __size;						\
+									\
+		get_builtin_firmware(imem, &__mem, &__size);		\
+		ddrc_phy_load_firmware(IOMEM(MX8MQ_DDRC_PHY_BASE_ADDR),	\
+				       DDRC_PHY_IMEM, __mem, __size);	\
+									\
+		get_builtin_firmware(dmem, &__mem, &__size);		\
+		ddrc_phy_load_firmware(IOMEM(MX8MQ_DDRC_PHY_BASE_ADDR),	\
+				       DDRC_PHY_DMEM, __mem, __size);	\
+	} while (0)
+
+#define ddr_load_train_code(imem_dmem) __ddr_load_train_code(imem_dmem)
+
+#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + (X * 0x2000000))
+
+#define DDRC_STAT(X)             (DDRC_IPS_BASE_ADDR(X) + 0x04)
+#define DDRC_MRSTAT(X)           (DDRC_IPS_BASE_ADDR(X) + 0x18)
+#define DDRC_PWRCTL(X)           (DDRC_IPS_BASE_ADDR(X) + 0x30)
+#define DDRC_RFSHCTL3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x60)
+#define DDRC_CRCPARSTAT(X)       (DDRC_IPS_BASE_ADDR(X) + 0xcc)
+#define DDRC_DFIMISC(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1b0)
+#define DDRC_DFISTAT(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1bc)
+#define DDRC_SWCTL(X)            (DDRC_IPS_BASE_ADDR(X) + 0x320)
+#define DDRC_SWSTAT(X)           (DDRC_IPS_BASE_ADDR(X) + 0x324)
+#define DDRC_PCTRL_0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x490)
+
+#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000))
+
+#endif
\ No newline at end of file
-- 
2.17.0


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  parent reply	other threads:[~2018-06-12 20:54 UTC|newest]

Thread overview: 63+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-12 20:52 [PATCH v5 00/54] ARM: i.MX8MQ and EVK support Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 01/54] ARM: i.MX: xload: Fix compiler warning Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 02/54] ARM: i.MX: compile arm32 specific errata only for CPU32 Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 03/54] ARM: Add i.MX8 support Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 04/54] aarch64: Add i.MX8 debug UART support Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 05/54] Include our own include/dt-bindings Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 06/54] mci: imx-esdhc: use dma mapping functions Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 07/54] net: fec_imx: remove unnecessary DMA sync ops Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 08/54] net: fec_imx: Use dma mapping functions Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 09/54] net: fec_imx: Make use of IS_ALIGNED Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 10/54] clock: Add i.MX8MQ clock driver Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 11/54] serial: i.MX: Add i.MX8 support Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 12/54] mmc: i.MX esdhc: " Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 13/54] gpio: i.MX: Add i.MX8mq support Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 14/54] ARM: i.MX: ocotp: Add i.MX8MQ support Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 15/54] ARM: i.MX: Split shared CCM code into a separate file Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 16/54] ARM: i.MX: Add IOMUX pad constants for i.MX8 Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 17/54] ARM: i.MX: Add basic CCM " Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 18/54] ARM: Add constants and helpers for system counter interface Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 19/54] clocksource: armv8-timer: Convert explicit assembly into helpers Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 20/54] ARM: i.MX8: Initialize system counter Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 21/54] ARM: i.MX: boot: Fix address casting on 64-bit platforms Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 22/54] ARM: boot: Add trivial i.MX8 support Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 23/54] ARM: i.MX: xload-esdhc: Rework to make code be less i.MX6-specific Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 24/54] ARM: i.MX: xload-esdhc: Allow custom buffer address, device offset Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 25/54] ARM: i.MX: xload-esdhc: Add support for i.MX8 Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 26/54] pinctrl: i.MX: " Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 27/54] Documentation: imx: Change block size for 'dd' to 1024 Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 28/54] Documentation: i.MX: Add missing <soctype> Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 29/54] clocksource: armv8-timer: Make armv8_clocksource_read() static Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 30/54] clocksource: armv8-timer: Make use of postcore_platform_driver() Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 31/54] Port <linux/iopoll.h> from U-Boot Andrey Smirnov
2018-06-13  8:12   ` Sascha Hauer
2018-06-13 12:29     ` Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 32/54] common/clock: Move delay and timeout functions to lib/ Andrey Smirnov
2018-06-13  8:19   ` Sascha Hauer
2018-06-13 12:26     ` Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 33/54] clock: Use udelay() to implement mdelay() Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 34/54] ARM: i.MX8: Add DDRC PHY and DDR CTL base addresses Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 35/54] Kbuild: Add $(quote) Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 36/54] Add builtin firmware support Andrey Smirnov
2018-06-12 20:52 ` Andrey Smirnov [this message]
2018-06-12 20:52 ` [PATCH v5 38/54] ARM: Specify HAVE_PBL_IMAGE for CPU_64 Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 39/54] ARM: lib64: Make string functions aware of MMU configuration Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 40/54] ARM: mmu: Make use of dsb() and isb() helpers Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 41/54] ARM: cache: Remove unused cache ops struct Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 42/54] ARM: no-mmu: Disable building for ARMv8 Andrey Smirnov
2018-06-12 20:52 ` [PATCH v5 43/54] ARM: interrupts64: Include ESR value in exception traceback Andrey Smirnov
2018-06-12 20:53 ` [PATCH v5 44/54] ARM: mmu64: Trivial code simplification Andrey Smirnov
2018-06-12 20:53 ` [PATCH v5 45/54] ARM: mmu64: Make use of create_table() Andrey Smirnov
2018-06-12 20:53 ` [PATCH v5 46/54] ARM: mmu64: Convert flags in arch_remap_range() Andrey Smirnov
2018-06-12 20:53 ` [PATCH v5 47/54] ARM: include: dma: Add missing no-MMU stubs Andrey Smirnov
2018-06-12 20:53 ` [PATCH v5 48/54] scripts: imx-image: Drop error return from write_dcd() Andrey Smirnov
2018-06-12 20:53 ` [PATCH v5 49/54] scripts: imx-image: Limit v2 header size to HEADER_LEN Andrey Smirnov
2018-06-12 20:53 ` [PATCH v5 50/54] scripts: imx-image: Use a loop to create multiple header copies Andrey Smirnov
2018-06-12 20:53 ` [PATCH v5 51/54] scripts: imx-image: Share the code to write barebox header Andrey Smirnov
2018-06-12 20:53 ` [PATCH v5 52/54] scripts: imx-image: Add i.MX8MQ support Andrey Smirnov
2018-06-12 20:53 ` [PATCH v5 53/54] ARM: i.MX8: Add i.MX8mq EVK support Andrey Smirnov
2018-06-13  8:49   ` Christian Hemp
2018-06-13 12:33     ` Andrey Smirnov
2018-06-12 20:53 ` [PATCH v5 54/54] ARM: Introduce imx_v8_defconfig Andrey Smirnov
2018-06-13  8:24 ` [PATCH v5 00/54] ARM: i.MX8MQ and EVK support Sascha Hauer
2018-06-13 12:29   ` Andrey Smirnov

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