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From: Steffen Trumtrar <s.trumtrar@pengutronix.de>
To: Barebox List <barebox@lists.infradead.org>
Subject: [PATCH 02/19] mci: dw_mmc: convert to BIT() macro
Date: Tue, 31 Jul 2018 12:44:25 +0200	[thread overview]
Message-ID: <20180731104442.2451-3-s.trumtrar@pengutronix.de> (raw)
In-Reply-To: <20180731104442.2451-1-s.trumtrar@pengutronix.de>

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
 drivers/mci/dw_mmc.c | 99 ++++++++++++++++++++++++++--------------------------
 1 file changed, 50 insertions(+), 49 deletions(-)

diff --git a/drivers/mci/dw_mmc.c b/drivers/mci/dw_mmc.c
index 0dd4c1f44154..473942cbe0f9 100644
--- a/drivers/mci/dw_mmc.c
+++ b/drivers/mci/dw_mmc.c
@@ -26,6 +26,7 @@
 #include <mci.h>
 #include <io.h>
 #include <platform_data/dw_mmc.h>
+#include <linux/bitops.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <asm-generic/errno.h>
@@ -70,22 +71,22 @@
 #define DWMCI_DATA		0x200
 
 /* Interrupt Mask register */
-#define DWMCI_INTMSK_ALL		0xffffffff
-#define DWMCI_INTMSK_RE			(1 << 1)
-#define DWMCI_INTMSK_CDONE		(1 << 2)
-#define DWMCI_INTMSK_DTO		(1 << 3)
-#define DWMCI_INTMSK_TXDR		(1 << 4)
-#define DWMCI_INTMSK_RXDR		(1 << 5)
-#define DWMCI_INTMSK_RCRC		(1 << 6)
-#define DWMCI_INTMSK_DCRC		(1 << 7)
-#define DWMCI_INTMSK_RTO		(1 << 8)
-#define DWMCI_INTMSK_DRTO		(1 << 9)
-#define DWMCI_INTMSK_HTO		(1 << 10)
-#define DWMCI_INTMSK_FRUN		(1 << 11)
-#define DWMCI_INTMSK_HLE		(1 << 12)
-#define DWMCI_INTMSK_SBE		(1 << 13)
-#define DWMCI_INTMSK_ACD		(1 << 14)
-#define DWMCI_INTMSK_EBE		(1 << 15)
+#define DWMCI_INTMSK_ALL	0xffffffff
+#define DWMCI_INTMSK_RE		BIT(1)
+#define DWMCI_INTMSK_CDONE	BIT(2)
+#define DWMCI_INTMSK_DTO	BIT(3)
+#define DWMCI_INTMSK_TXDR	BIT(4)
+#define DWMCI_INTMSK_RXDR	BIT(5)
+#define DWMCI_INTMSK_RCRC	BIT(6)
+#define DWMCI_INTMSK_DCRC	BIT(7)
+#define DWMCI_INTMSK_RTO	BIT(8)
+#define DWMCI_INTMSK_DRTO	BIT(9)
+#define DWMCI_INTMSK_HTO	BIT(10)
+#define DWMCI_INTMSK_FRUN	BIT(11)
+#define DWMCI_INTMSK_HLE	BIT(12)
+#define DWMCI_INTMSK_SBE	BIT(13)
+#define DWMCI_INTMSK_ACD	BIT(14)
+#define DWMCI_INTMSK_EBE	BIT(15)
 
 /* Raw interrupt Register */
 #define DWMCI_DATA_ERR	(DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
@@ -93,41 +94,41 @@
 #define DWMCI_DATA_TOUT	(DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
 
 /* CTRL register */
-#define DWMCI_CTRL_RESET		(1 << 0)
-#define DWMCI_CTRL_FIFO_RESET		(1 << 1)
-#define DWMCI_CTRL_DMA_RESET		(1 << 2)
-#define DWMCI_DMA_EN			(1 << 5)
-#define DWMCI_CTRL_SEND_AS_CCSD		(1 << 10)
-#define DWMCI_IDMAC_EN			(1 << 25)
-#define DWMCI_RESET_ALL			(DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
+#define DWMCI_CTRL_RESET	BIT(0)
+#define DWMCI_CTRL_FIFO_RESET	BIT(1)
+#define DWMCI_CTRL_DMA_RESET	BIT(2)
+#define DWMCI_DMA_EN		BIT(5)
+#define DWMCI_CTRL_SEND_AS_CCSD	BIT(10)
+#define DWMCI_IDMAC_EN		BIT(25)
+#define DWMCI_RESET_ALL		(DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |	\
 				DWMCI_CTRL_DMA_RESET)
 
 /* CMD register */
-#define DWMCI_CMD_RESP_EXP		(1 << 6)
-#define DWMCI_CMD_RESP_LENGTH		(1 << 7)
-#define DWMCI_CMD_CHECK_CRC		(1 << 8)
-#define DWMCI_CMD_DATA_EXP		(1 << 9)
-#define DWMCI_CMD_RW			(1 << 10)
-#define DWMCI_CMD_SEND_STOP		(1 << 12)
-#define DWMCI_CMD_ABORT_STOP		(1 << 14)
-#define DWMCI_CMD_PRV_DAT_WAIT		(1 << 13)
-#define DWMCI_CMD_UPD_CLK		(1 << 21)
-#define DWMCI_CMD_USE_HOLD_REG		(1 << 29)
-#define DWMCI_CMD_START			(1 << 31)
+#define DWMCI_CMD_RESP_EXP	BIT(6)
+#define DWMCI_CMD_RESP_LENGTH	BIT(7)
+#define DWMCI_CMD_CHECK_CRC	BIT(8)
+#define DWMCI_CMD_DATA_EXP	BIT(9)
+#define DWMCI_CMD_RW		BIT(10)
+#define DWMCI_CMD_SEND_STOP	BIT(12)
+#define DWMCI_CMD_ABORT_STOP	BIT(14)
+#define DWMCI_CMD_PRV_DAT_WAIT	BIT(13)
+#define DWMCI_CMD_UPD_CLK	BIT(21)
+#define DWMCI_CMD_USE_HOLD_REG	BIT(29)
+#define DWMCI_CMD_START		BIT(31)
 
 /* CLKENA register */
-#define DWMCI_CLKEN_ENABLE		(1 << 0)
-#define DWMCI_CLKEN_LOW_PWR		(1 << 16)
+#define DWMCI_CLKEN_ENABLE	BIT(0)
+#define DWMCI_CLKEN_LOW_PWR	BIT(16)
 
 /* Card-type register */
-#define DWMCI_CTYPE_1BIT		0
-#define DWMCI_CTYPE_4BIT		(1 << 0)
-#define DWMCI_CTYPE_8BIT		(1 << 16)
+#define DWMCI_CTYPE_1BIT	0
+#define DWMCI_CTYPE_4BIT	BIT(0)
+#define DWMCI_CTYPE_8BIT	BIT(16)
 
 /* Status Register */
-#define DWMCI_STATUS_FIFO_EMPTY		(1 << 2)
-#define DWMCI_STATUS_FIFO_FULL		(1 << 3)
-#define DWMCI_STATUS_BUSY		(1 << 9)
+#define DWMCI_STATUS_FIFO_EMPTY	BIT(2)
+#define DWMCI_STATUS_FIFO_FULL	BIT(3)
+#define DWMCI_STATUS_BUSY	BIT(9)
 
 /* FIFOTH Register */
 #define DWMCI_FIFOTH_MSIZE(x)		((x) << 28)
@@ -135,15 +136,15 @@
 #define DWMCI_FIFOTH_TX_WMARK(x)	(x)
 #define DWMCI_FIFOTH_FIFO_DEPTH(x)	((((x) >> 16) & 0x3ff) + 1)
 
-#define DWMCI_IDMAC_OWN			(1 << 31)
-#define DWMCI_IDMAC_CH			(1 << 4)
-#define DWMCI_IDMAC_FS			(1 << 3)
-#define DWMCI_IDMAC_LD			(1 << 2)
+#define DWMCI_IDMAC_OWN	BIT(31)
+#define DWMCI_IDMAC_CH	BIT(4)
+#define DWMCI_IDMAC_FS	BIT(3)
+#define DWMCI_IDMAC_LD	BIT(2)
 
 /* Bus Mode Register */
-#define DWMCI_BMOD_IDMAC_RESET		(1 << 0)
-#define DWMCI_BMOD_IDMAC_FB		(1 << 1)
-#define DWMCI_BMOD_IDMAC_EN		(1 << 7)
+#define DWMCI_BMOD_IDMAC_RESET	BIT(0)
+#define DWMCI_BMOD_IDMAC_FB	BIT(1)
+#define DWMCI_BMOD_IDMAC_EN	BIT(7)
 
 struct dwmci_host {
 	struct mci_host mci;
-- 
2.11.0


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  parent reply	other threads:[~2018-07-31 10:45 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-31 10:44 [PATCH 00/19] ARM: SoCFPGA: Arria10: Early FPGA config Steffen Trumtrar
2018-07-31 10:44 ` [PATCH 01/19] mci: dw_mmc: remove device_d pointer Steffen Trumtrar
2018-07-31 10:44 ` Steffen Trumtrar [this message]
2018-07-31 10:44 ` [PATCH 03/19] mci: dw: move defines to headerfile Steffen Trumtrar
2018-07-31 10:44 ` [PATCH 04/19] bootm: allow booting SoCFPGA prebootloader image Steffen Trumtrar
2018-07-31 10:44 ` [PATCH 05/19] reset: socfpga: add missing driver name Steffen Trumtrar
2018-07-31 10:44 ` [PATCH 06/19] ARM: socfpga: arria10: move debug_ll to common code Steffen Trumtrar
2018-07-31 10:44 ` [PATCH 07/19] ARM: socfpga: arria10: add ocram base address Steffen Trumtrar
2018-07-31 10:44 ` [PATCH 08/19] ARM: socfpga: add SMP_TWD_ADDR for Arria10 Steffen Trumtrar
2018-07-31 10:44 ` [PATCH 09/19] ARM: socfpga: arria10-init: split pinsetup Steffen Trumtrar
2018-07-31 10:44 ` [PATCH 10/19] ARM: socfpga: arria10: set default TEXTBASE Steffen Trumtrar
2018-07-31 10:44 ` [PATCH 11/19] ARM: socfpga: arria10: fix SDMMC phase shift Steffen Trumtrar
2018-07-31 10:44 ` [PATCH 12/19] ARM: socfpga: achilles: update handoff files Steffen Trumtrar
2018-07-31 10:44 ` [PATCH 13/19] ARM: dts: socfpga: Fix achilles dtc warnings Steffen Trumtrar
2018-07-31 10:44 ` [PATCH 14/19] scripts: socfpga_mkimage: add size feature for PBL barebox Steffen Trumtrar
2018-07-31 10:44 ` [PATCH 15/19] ARM: socfpga: arria10-reset-manager: don't reset bootsource Steffen Trumtrar
2018-07-31 10:44 ` [PATCH 16/19] ARM: socfpga: Arria10: support programming FPGA in PBL Steffen Trumtrar
2018-07-31 10:44 ` [PATCH 17/19] ARM: socfpga: achilles: convert to PBL barebox Steffen Trumtrar
2018-07-31 10:44 ` [PATCH 18/19] ARM: arria10: update defconfig Steffen Trumtrar
2018-07-31 10:44 ` [PATCH 19/19] ARM: socfpga: achilles: move environment to raw partition Steffen Trumtrar
2018-08-08  7:24 ` [PATCH 00/19] ARM: SoCFPGA: Arria10: Early FPGA config Sascha Hauer

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