Re: [PATCH 2/2] clk: clk-sccg-pll: Drop prepare/unprepare for SCCG_PLL2

[Sascha Hauer <s.hauer@pengutronix.de>]

On Mon, Aug 20, 2018 at 11:28:53PM -0700, Andrey Smirnov wrote:
> A number of PLL pairs (e.g. "sys1_pll1" and "sys1_pll2") share the
> same configuration register, so touching PD bit, as is done for
> SCCG_PLL2 in its prepare/unprepare methods will result in shut down of
> both PLLs. This is very undesireable, since attempting to re-parent a
> clock to "sys1_pll2" might result in complete system shutdown due to
> "sys1_pll1" being shut-down as a part of re-parenting process.

I can imagine that there are problems with the way it is currently
handled, but the scenario you describe shouldn't happen. "sys1_pll1"
will never be shut down because it doesn't have a disable hook:

static const struct clk_ops clk_sccg_pll1_ops = {
        .is_enabled     = clk_pll1_is_prepared,
        .recalc_rate    = clk_pll1_recalc_rate,
        .round_rate     = clk_pll1_round_rate,
        .set_rate       = clk_pll1_set_rate,
};

static const struct clk_ops clk_sccg_pll2_ops = {
        .enable         = clk_pll1_prepare,
        .disable        = clk_pll1_unprepare,
        .recalc_rate    = clk_pll2_recalc_rate,
        .round_rate     = clk_pll2_round_rate,
        .set_rate       = clk_pll2_set_rate,
};

Have I missed something?

Sascha

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