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From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: barebox@lists.infradead.org
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Subject: [PATCH 17/58] PCI: designware: Remove incorrect RC memory base/limit configuration
Date: Wed, 12 Dec 2018 23:11:03 -0800	[thread overview]
Message-ID: <20181213071144.31691-18-andrew.smirnov@gmail.com> (raw)
In-Reply-To: <20181213071144.31691-1-andrew.smirnov@gmail.com>

Port of a Linux commit a5cb903aef8c642e6f0f6810d46dacedf666b54a

  Currently dw_pcie_setup_rc() configures memory base and memory limit in the
  type1 configuration header for the root complex.  In doing so it uses the
  CPU address (pp->mem_base) rather than the bus address (pp->mem_bus_addr).
  This is wrong and it is useless since the configuration is overwritten
  later on when pci_bus_assign_resources() is called.

  Remove this configuration from dw_pcie_setup_rc().

  Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Pratyush Anand <pratyush.anand@gmail.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 drivers/pci/pcie-designware.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c
index 5e824cedc..e9058768d 100644
--- a/drivers/pci/pcie-designware.c
+++ b/drivers/pci/pcie-designware.c
@@ -489,8 +489,6 @@ static struct pci_ops dw_pcie_ops = {
 void dw_pcie_setup_rc(struct pcie_port *pp)
 {
 	u32 val;
-	u32 membase;
-	u32 memlimit;
 
 	/* set the number of lanes */
 	dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
@@ -537,12 +535,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 	val |= 0x00010100;
 	dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
 
-	/* setup memory base, memory limit */
-	membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
-	memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
-	val = memlimit | membase;
-	dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
-
 	/* setup command register */
 	dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
 	val &= 0xffff0000;
-- 
2.19.1


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  parent reply	other threads:[~2018-12-13  7:12 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-13  7:10 [PATCH 00/58] PCI i.MX6/DesignWare sync up with 4.20-rc1 Andrey Smirnov
2018-12-13  7:10 ` [PATCH 01/58] PCI: desginware: Remove bogus prototypes Andrey Smirnov
2018-12-13  7:10 ` [PATCH 02/58] PCI: designware: Consolidate outbound iATU programming functions Andrey Smirnov
2018-12-13  7:10 ` [PATCH 03/58] PCI: designware: Use iATU0 for cfg and IO, iATU1 for MEM Andrey Smirnov
2018-12-13  7:10 ` [PATCH 04/58] PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASK Andrey Smirnov
2018-12-13  7:10 ` [PATCH 05/58] PCI: designware: Use exact access size in dw_pcie_cfg_read() Andrey Smirnov
2018-12-13  7:10 ` [PATCH 06/58] PCI: designware: Simplify dw_pcie_cfg_read/write() interfaces Andrey Smirnov
2018-12-13  7:10 ` [PATCH 07/58] PCI: designware: Require config accesses to be naturally aligned Andrey Smirnov
2018-12-13  7:10 ` [PATCH 08/58] PCI: designware: Make "num-lanes" an optional DT property Andrey Smirnov
2018-12-13  7:10 ` [PATCH 09/58] PCI: designware: Ensure ATU is enabled before IO/conf space accesses Andrey Smirnov
2018-12-13  7:10 ` [PATCH 10/58] PCI: designware: Simplify control flow Andrey Smirnov
2018-12-13  7:10 ` [PATCH 11/58] PCI: designware: Make config accessor override checking symmetric Andrey Smirnov
2018-12-13  7:10 ` [PATCH 12/58] PCI: designware: Explain why we don't program ATU for some platforms Andrey Smirnov
2018-12-13  7:10 ` [PATCH 13/58] PCI: imx6: Move link up check into imx6_pcie_wait_for_link() Andrey Smirnov
2018-12-13  7:11 ` [PATCH 14/58] PCI: designware: Add generic dw_pcie_wait_for_link() Andrey Smirnov
2018-12-13  7:11 ` [PATCH 15/58] PCI: designware: Add default link up check if sub-driver doesn't override Andrey Smirnov
2018-12-13  7:11 ` [PATCH 16/58] PCI: designware: Move Root Complex setup code to dw_pcie_setup_rc() Andrey Smirnov
2018-12-13  7:11 ` Andrey Smirnov [this message]
2018-12-13  7:11 ` [PATCH 18/58] PCI: designware: Return data directly from dw_pcie_readl_rc() Andrey Smirnov
2018-12-13  7:11 ` [PATCH 19/58] PCI: designware: Move link wait definitions to .c file Andrey Smirnov
2018-12-13  7:11 ` [PATCH 20/58] PCI: designware: Wait for iATU enable Andrey Smirnov
2018-12-13  7:11 ` [PATCH 21/58] PCI: designware: Check LTSSM training bit before deciding link is up Andrey Smirnov
2018-12-13  7:11 ` [PATCH 22/58] PCI: designware: Keep viewport fixed for IO transaction if num_viewport > 2 Andrey Smirnov
2018-12-14  6:49   ` Andrey Smirnov
2018-12-13  7:11 ` [PATCH 23/58] PCI: designware: Exchange viewport of `MEMORYs' and `CFGs/IOs' Andrey Smirnov
2018-12-13  7:11 ` [PATCH 24/58] PCI: designware: Rename dw_pcie_valid_config() to dw_pcie_valid_device() Andrey Smirnov
2018-12-13  7:11 ` [PATCH 25/58] PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfaces Andrey Smirnov
2018-12-13  7:11 ` [PATCH 26/58] PCI: designware: Swap order of dw_pcie_writel_rc() reg/val arguments Andrey Smirnov
2018-12-13  7:11 ` [PATCH 27/58] PCI: designware: Export dw_pcie_readl_rc(), dw_pcie_writel_rc() Andrey Smirnov
2018-12-13  7:11 ` [PATCH 28/58] PCI: dwc: designware: Move register defines to designware header file Andrey Smirnov
2018-12-13  7:11 ` [PATCH 29/58] PCI: dwc: all: Rename cfg_read/cfg_write to read/write Andrey Smirnov
2018-12-13  7:11 ` [PATCH 30/58] PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init() Andrey Smirnov
2018-12-13  7:11 ` [PATCH 31/58] PCI: imx6: Add local struct device pointers Andrey Smirnov
2018-12-13  7:11 ` [PATCH 32/58] PCI: imx6: Removed unused struct imx6_pcie.mem_base Andrey Smirnov
2018-12-13  7:11 ` [PATCH 33/58] PCI: imx6: Pass struct imx6_pcie to PHY accessors Andrey Smirnov
2018-12-13  7:11 ` [PATCH 34/58] PCI: imx6: Pass device-specific struct to internal functions Andrey Smirnov
2018-12-13  7:11 ` [PATCH 35/58] PCI: imx6: Use generic DesignWare accessors Andrey Smirnov
2018-12-13  7:11 ` [PATCH 36/58] PCI: imx6: Reorder struct imx6_pcie Andrey Smirnov
2018-12-13  7:11 ` [PATCH 37/58] PCI: imx6: Port error messages for imx6_pcie_deassert_core_reset() Andrey Smirnov
2018-12-13  7:11 ` [PATCH 38/58] PCI: imx6: Remove unused return values Andrey Smirnov
2018-12-13  7:11 ` [PATCH 39/58] PCI: imx6: Factor out ref clock enable Andrey Smirnov
2018-12-13  7:11 ` [PATCH 40/58] PCI: imx6: Add DT property for link gen, default to Gen1 Andrey Smirnov
2018-12-13  7:11 ` [PATCH 41/58] PCI: imx6: Remove redundant "Link never came up" message Andrey Smirnov
2018-12-13  7:11 ` [PATCH 42/58] PCI: imx6: Remove LTSSM disable workaround Andrey Smirnov
2018-12-13  7:11 ` [PATCH 43/58] PCI: dwc: all: Split struct pcie_port into host-only and core structures Andrey Smirnov
2018-12-13  7:11 ` [PATCH 44/58] PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc() Andrey Smirnov
2018-12-13  7:11 ` [PATCH 45/58] PCI: dwc: designware: Fix style errors in pcie-designware.c Andrey Smirnov
2018-12-13  7:11 ` [PATCH 46/58] PCI: dwc: Split pcie-designware.c into host and core files Andrey Smirnov
2018-12-13  7:11 ` [PATCH 47/58] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument Andrey Smirnov
2018-12-13  7:11 ` [PATCH 48/58] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes Andrey Smirnov
2018-12-13  7:11 ` [PATCH 49/58] PCI: dwc: designware: Test PCIE_ATU_ENABLE bit specifically Andrey Smirnov
2018-12-13  7:11 ` [PATCH 50/58] PCI: Fix typos and whitespace errors Andrey Smirnov
2018-12-13  7:11 ` [PATCH 51/58] PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplate Andrey Smirnov
2018-12-13  7:11 ` [PATCH 52/58] PCI: dwc: Replace lower into upper case characters Andrey Smirnov
2018-12-13  7:11 ` [PATCH 53/58] PCI: dwc: designware: Handle ->host_init() failures Andrey Smirnov
2018-12-13  7:11 ` [PATCH 54/58] PCI: dwc: Add accessors for write permission of DBI read-only registers Andrey Smirnov
2018-12-13  7:11 ` [PATCH 55/58] PCI: dwc: Enable write permission for Class Code, Interrupt Pin updates Andrey Smirnov
2018-12-13  7:11 ` [PATCH 56/58] PCI: dwc: Fix enumeration end when reaching root subordinate Andrey Smirnov
2018-12-13  7:11 ` [PATCH 57/58] PCI: dwc: Small computation improvement Andrey Smirnov
2018-12-13  7:11 ` [PATCH 58/58] PCI: dwc: Constify dw_pcie_host_ops structures Andrey Smirnov
2018-12-14  8:28 ` [PATCH 00/58] PCI i.MX6/DesignWare sync up with 4.20-rc1 Andrey Smirnov

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