mail archive of the barebox mailing list
 help / color / mirror / Atom feed
From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: barebox@lists.infradead.org
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Subject: [PATCH 40/58] PCI: imx6: Add DT property for link gen, default to Gen1
Date: Wed, 12 Dec 2018 23:11:26 -0800	[thread overview]
Message-ID: <20181213071144.31691-41-andrew.smirnov@gmail.com> (raw)
In-Reply-To: <20181213071144.31691-1-andrew.smirnov@gmail.com>

Port of a Linux commit a5fcec480f25eb5444c0b71ecdf9b18b09236b95

  Freescale has stated [1] that the LVDS clock source of the IMX6 does not
  pass the PCI Gen2 clock jitter test, therefore unless an external Gen2
  compliant external clock source is present and supplied back to the IMX6
  PCIe core via LVDS CLK1/CLK2 you can not claim Gen2 compliance.

  Add a DT property to specify Gen1 vs Gen2 and check this before allowing a
  Gen2 link.

  We default to Gen1 if the property is not present because at this time
  there are no IMX6 boards in mainline that 'input' a clock on LVDS
  CLK1/CLK2.

  In order to be Gen2 compliant on IMX6 you need to:

   - Have a Gen2 compliant external clock generator and route that clock back
     to either LVDS CLK1 or LVDS CLK2 as an input (see IMX6SX-SabreSD
     reference design).

   - Specify this clock in the PCIe node in the DT (i.e.,
     IMX6QDL_CLK_LVDS1_IN or IMX6QDL_CLK_LVDS2_IN instead of
     IMX6QDL_CLK_LVDS1_GATE which configures it as a CLK output).

  [1] https://community.freescale.com/message/453209

  Signed-off-by: Tim Harvey <tharvey@gateworks.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
  CC: Fabio Estevam <fabio.estevam@freescale.com>
  CC: Zhu Richard <Richard.Zhu@freescale.com>
  CC: Akshay Bhat <akshay.bhat@timesys.com>
  CC: Rob Herring <robh+dt@kernel.org>
  CC: Shawn Guo <shawnguo@kernel.org>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 drivers/pci/pci-imx6.c | 25 ++++++++++++++++++-------
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/drivers/pci/pci-imx6.c b/drivers/pci/pci-imx6.c
index 447bb72ad..d72abe3a3 100644
--- a/drivers/pci/pci-imx6.c
+++ b/drivers/pci/pci-imx6.c
@@ -55,6 +55,7 @@ struct imx6_pcie {
 	u32                     tx_deemph_gen2_6db;
 	u32                     tx_swing_full;
 	u32                     tx_swing_low;
+	int			link_gen;
 };
 
 /* PCIe Root Complex registers (memory-mapped) */
@@ -464,11 +465,16 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
 		goto err_reset_phy;
 	}
 
-	/* Allow Gen2 mode after the link is up. */
-	tmp = dw_pcie_readl_rc(pp, PCIE_RC_LCR);
-	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
-	tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
-	dw_pcie_writel_rc(pp, PCIE_RC_LCR, tmp);
+
+	if (imx6_pcie->link_gen == 2) {
+		/* Allow Gen2 mode after the link is up. */
+		tmp = dw_pcie_readl_rc(pp, PCIE_RC_LCR);
+		tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
+		tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
+		dw_pcie_writel_rc(pp, PCIE_RC_LCR, tmp);
+	} else {
+		dev_info(dev, "Link: Gen2 disabled\n");
+	}
 
 	/*
 	 * Start Directed Speed Change so the best possible speed both link
@@ -492,8 +498,7 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
 	}
 
 	tmp = dw_pcie_readl_rc(pp, PCIE_RC_LCSR);
-	dev_dbg(dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
-
+	dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
 	return 0;
 
 err_reset_phy:
@@ -620,6 +625,12 @@ static int __init imx6_pcie_probe(struct device_d *dev)
 				 &imx6_pcie->tx_swing_low))
 		imx6_pcie->tx_swing_low = 127;
 
+       /* Limit link speed */
+       ret = of_property_read_u32(np, "fsl,max-link-speed",
+                                  &imx6_pcie->link_gen);
+       if (ret)
+               imx6_pcie->link_gen = 1;
+
 	ret = imx6_add_pcie_port(imx6_pcie, dev);
 	if (ret < 0)
 		return ret;
-- 
2.19.1


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

  parent reply	other threads:[~2018-12-13  7:12 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-13  7:10 [PATCH 00/58] PCI i.MX6/DesignWare sync up with 4.20-rc1 Andrey Smirnov
2018-12-13  7:10 ` [PATCH 01/58] PCI: desginware: Remove bogus prototypes Andrey Smirnov
2018-12-13  7:10 ` [PATCH 02/58] PCI: designware: Consolidate outbound iATU programming functions Andrey Smirnov
2018-12-13  7:10 ` [PATCH 03/58] PCI: designware: Use iATU0 for cfg and IO, iATU1 for MEM Andrey Smirnov
2018-12-13  7:10 ` [PATCH 04/58] PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASK Andrey Smirnov
2018-12-13  7:10 ` [PATCH 05/58] PCI: designware: Use exact access size in dw_pcie_cfg_read() Andrey Smirnov
2018-12-13  7:10 ` [PATCH 06/58] PCI: designware: Simplify dw_pcie_cfg_read/write() interfaces Andrey Smirnov
2018-12-13  7:10 ` [PATCH 07/58] PCI: designware: Require config accesses to be naturally aligned Andrey Smirnov
2018-12-13  7:10 ` [PATCH 08/58] PCI: designware: Make "num-lanes" an optional DT property Andrey Smirnov
2018-12-13  7:10 ` [PATCH 09/58] PCI: designware: Ensure ATU is enabled before IO/conf space accesses Andrey Smirnov
2018-12-13  7:10 ` [PATCH 10/58] PCI: designware: Simplify control flow Andrey Smirnov
2018-12-13  7:10 ` [PATCH 11/58] PCI: designware: Make config accessor override checking symmetric Andrey Smirnov
2018-12-13  7:10 ` [PATCH 12/58] PCI: designware: Explain why we don't program ATU for some platforms Andrey Smirnov
2018-12-13  7:10 ` [PATCH 13/58] PCI: imx6: Move link up check into imx6_pcie_wait_for_link() Andrey Smirnov
2018-12-13  7:11 ` [PATCH 14/58] PCI: designware: Add generic dw_pcie_wait_for_link() Andrey Smirnov
2018-12-13  7:11 ` [PATCH 15/58] PCI: designware: Add default link up check if sub-driver doesn't override Andrey Smirnov
2018-12-13  7:11 ` [PATCH 16/58] PCI: designware: Move Root Complex setup code to dw_pcie_setup_rc() Andrey Smirnov
2018-12-13  7:11 ` [PATCH 17/58] PCI: designware: Remove incorrect RC memory base/limit configuration Andrey Smirnov
2018-12-13  7:11 ` [PATCH 18/58] PCI: designware: Return data directly from dw_pcie_readl_rc() Andrey Smirnov
2018-12-13  7:11 ` [PATCH 19/58] PCI: designware: Move link wait definitions to .c file Andrey Smirnov
2018-12-13  7:11 ` [PATCH 20/58] PCI: designware: Wait for iATU enable Andrey Smirnov
2018-12-13  7:11 ` [PATCH 21/58] PCI: designware: Check LTSSM training bit before deciding link is up Andrey Smirnov
2018-12-13  7:11 ` [PATCH 22/58] PCI: designware: Keep viewport fixed for IO transaction if num_viewport > 2 Andrey Smirnov
2018-12-14  6:49   ` Andrey Smirnov
2018-12-13  7:11 ` [PATCH 23/58] PCI: designware: Exchange viewport of `MEMORYs' and `CFGs/IOs' Andrey Smirnov
2018-12-13  7:11 ` [PATCH 24/58] PCI: designware: Rename dw_pcie_valid_config() to dw_pcie_valid_device() Andrey Smirnov
2018-12-13  7:11 ` [PATCH 25/58] PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfaces Andrey Smirnov
2018-12-13  7:11 ` [PATCH 26/58] PCI: designware: Swap order of dw_pcie_writel_rc() reg/val arguments Andrey Smirnov
2018-12-13  7:11 ` [PATCH 27/58] PCI: designware: Export dw_pcie_readl_rc(), dw_pcie_writel_rc() Andrey Smirnov
2018-12-13  7:11 ` [PATCH 28/58] PCI: dwc: designware: Move register defines to designware header file Andrey Smirnov
2018-12-13  7:11 ` [PATCH 29/58] PCI: dwc: all: Rename cfg_read/cfg_write to read/write Andrey Smirnov
2018-12-13  7:11 ` [PATCH 30/58] PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init() Andrey Smirnov
2018-12-13  7:11 ` [PATCH 31/58] PCI: imx6: Add local struct device pointers Andrey Smirnov
2018-12-13  7:11 ` [PATCH 32/58] PCI: imx6: Removed unused struct imx6_pcie.mem_base Andrey Smirnov
2018-12-13  7:11 ` [PATCH 33/58] PCI: imx6: Pass struct imx6_pcie to PHY accessors Andrey Smirnov
2018-12-13  7:11 ` [PATCH 34/58] PCI: imx6: Pass device-specific struct to internal functions Andrey Smirnov
2018-12-13  7:11 ` [PATCH 35/58] PCI: imx6: Use generic DesignWare accessors Andrey Smirnov
2018-12-13  7:11 ` [PATCH 36/58] PCI: imx6: Reorder struct imx6_pcie Andrey Smirnov
2018-12-13  7:11 ` [PATCH 37/58] PCI: imx6: Port error messages for imx6_pcie_deassert_core_reset() Andrey Smirnov
2018-12-13  7:11 ` [PATCH 38/58] PCI: imx6: Remove unused return values Andrey Smirnov
2018-12-13  7:11 ` [PATCH 39/58] PCI: imx6: Factor out ref clock enable Andrey Smirnov
2018-12-13  7:11 ` Andrey Smirnov [this message]
2018-12-13  7:11 ` [PATCH 41/58] PCI: imx6: Remove redundant "Link never came up" message Andrey Smirnov
2018-12-13  7:11 ` [PATCH 42/58] PCI: imx6: Remove LTSSM disable workaround Andrey Smirnov
2018-12-13  7:11 ` [PATCH 43/58] PCI: dwc: all: Split struct pcie_port into host-only and core structures Andrey Smirnov
2018-12-13  7:11 ` [PATCH 44/58] PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc() Andrey Smirnov
2018-12-13  7:11 ` [PATCH 45/58] PCI: dwc: designware: Fix style errors in pcie-designware.c Andrey Smirnov
2018-12-13  7:11 ` [PATCH 46/58] PCI: dwc: Split pcie-designware.c into host and core files Andrey Smirnov
2018-12-13  7:11 ` [PATCH 47/58] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument Andrey Smirnov
2018-12-13  7:11 ` [PATCH 48/58] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes Andrey Smirnov
2018-12-13  7:11 ` [PATCH 49/58] PCI: dwc: designware: Test PCIE_ATU_ENABLE bit specifically Andrey Smirnov
2018-12-13  7:11 ` [PATCH 50/58] PCI: Fix typos and whitespace errors Andrey Smirnov
2018-12-13  7:11 ` [PATCH 51/58] PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplate Andrey Smirnov
2018-12-13  7:11 ` [PATCH 52/58] PCI: dwc: Replace lower into upper case characters Andrey Smirnov
2018-12-13  7:11 ` [PATCH 53/58] PCI: dwc: designware: Handle ->host_init() failures Andrey Smirnov
2018-12-13  7:11 ` [PATCH 54/58] PCI: dwc: Add accessors for write permission of DBI read-only registers Andrey Smirnov
2018-12-13  7:11 ` [PATCH 55/58] PCI: dwc: Enable write permission for Class Code, Interrupt Pin updates Andrey Smirnov
2018-12-13  7:11 ` [PATCH 56/58] PCI: dwc: Fix enumeration end when reaching root subordinate Andrey Smirnov
2018-12-13  7:11 ` [PATCH 57/58] PCI: dwc: Small computation improvement Andrey Smirnov
2018-12-13  7:11 ` [PATCH 58/58] PCI: dwc: Constify dw_pcie_host_ops structures Andrey Smirnov
2018-12-14  8:28 ` [PATCH 00/58] PCI i.MX6/DesignWare sync up with 4.20-rc1 Andrey Smirnov

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20181213071144.31691-41-andrew.smirnov@gmail.com \
    --to=andrew.smirnov@gmail.com \
    --cc=barebox@lists.infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox