* [PATCH v2 01/15] PCI: dwc: Fix pointer width cast problem
2019-02-05 21:53 [PATCH v2 00/15] PCIE support for i.MX8MQ Andrey Smirnov
@ 2019-02-05 21:53 ` Andrey Smirnov
2019-02-05 21:53 ` [PATCH v2 02/15] ARM: aarch64: Add PCI fixups section to linker script Andrey Smirnov
` (14 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Andrey Smirnov @ 2019-02-05 21:53 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Casting to u32 works well on 32-bit builds, but causes problem when
compiled on 64-bit machines. Switch it to cast to "unsigned long", so
that it would have appropriate width in both cases.
While at it, replace explicit casts to void * with IOMEM.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/pci/pcie-designware-host.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/pcie-designware-host.c b/drivers/pci/pcie-designware-host.c
index 5acd47f6e..7a95b2a09 100644
--- a/drivers/pci/pcie-designware-host.c
+++ b/drivers/pci/pcie-designware-host.c
@@ -150,15 +150,15 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
}
if (!pci->dbi_base)
- pci->dbi_base = (void __force *)pp->cfg.start;
+ pci->dbi_base = IOMEM(pp->cfg.start);
pp->mem_base = pp->mem.start;
if (!pp->va_cfg0_base)
- pp->va_cfg0_base = (void __force *)(u32)pp->cfg0_base;
+ pp->va_cfg0_base = IOMEM((unsigned long)pp->cfg0_base);
if (!pp->va_cfg1_base)
- pp->va_cfg1_base = (void __force *)(u32)pp->cfg1_base;
+ pp->va_cfg1_base = IOMEM((unsigned long)pp->cfg1_base);
ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
if (ret)
--
2.20.1
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v2 02/15] ARM: aarch64: Add PCI fixups section to linker script
2019-02-05 21:53 [PATCH v2 00/15] PCIE support for i.MX8MQ Andrey Smirnov
2019-02-05 21:53 ` [PATCH v2 01/15] PCI: dwc: Fix pointer width cast problem Andrey Smirnov
@ 2019-02-05 21:53 ` Andrey Smirnov
2019-02-05 21:53 ` [PATCH v2 03/15] soc: imx: gpcv2: use A_CORE instread of A7 for more i.MX platforms Andrey Smirnov
` (13 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Andrey Smirnov @ 2019-02-05 21:53 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Add PCI fixups section to linker script, so it would be possible to
enable PCI support.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/lib64/barebox.lds.S | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/lib64/barebox.lds.S b/arch/arm/lib64/barebox.lds.S
index 08adc44e8..b3e6843a1 100644
--- a/arch/arm/lib64/barebox.lds.S
+++ b/arch/arm/lib64/barebox.lds.S
@@ -86,6 +86,18 @@ SECTIONS
__usymtab : { BAREBOX_SYMS }
__usymtab_end = .;
+#ifdef CONFIG_PCI
+ __start_pci_fixups_early = .;
+ .pci_fixup_early : { KEEP(*(.pci_fixup_early)) }
+ __end_pci_fixups_early = .;
+ __start_pci_fixups_header = .;
+ .pci_fixup_header : { KEEP(*(.pci_fixup_header)) }
+ __end_pci_fixups_header = .;
+ __start_pci_fixups_enable = .;
+ .pci_fixup_enable : { KEEP(*(.pci_fixup_enable)) }
+ __end_pci_fixups_enable = .;
+#endif
+
.oftables : { BAREBOX_CLK_TABLE() }
.dtb : { BAREBOX_DTB() }
--
2.20.1
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v2 03/15] soc: imx: gpcv2: use A_CORE instread of A7 for more i.MX platforms
2019-02-05 21:53 [PATCH v2 00/15] PCIE support for i.MX8MQ Andrey Smirnov
2019-02-05 21:53 ` [PATCH v2 01/15] PCI: dwc: Fix pointer width cast problem Andrey Smirnov
2019-02-05 21:53 ` [PATCH v2 02/15] ARM: aarch64: Add PCI fixups section to linker script Andrey Smirnov
@ 2019-02-05 21:53 ` Andrey Smirnov
2019-02-05 21:54 ` [PATCH v2 04/15] soc: imx: gpcv2: make pgc driver more generic for other " Andrey Smirnov
` (12 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Andrey Smirnov @ 2019-02-05 21:53 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Port of a Linux commit fea88b2b80ab7a01982a6494ea8e8099cddc7b38
gpcv2 driver is NOT just used on i.MX7D which has Cortex-A7
cores, but also on i.MX8MQ/i.MX8MM platforms which use Cortex-A53
cores, so let's use A_CORE instread of A7 to avoid confusion.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/soc/imx/gpcv2.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 158bfc02d..a48f6d9a7 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -26,14 +26,14 @@
#include <regulator.h>
#include <dt-bindings/power/imx7-power.h>
-#define GPC_LPCR_A7_BSC 0x000
+#define GPC_LPCR_A_BSC 0x000
#define GPC_PGC_CPU_MAPPING 0x0ec
-#define USB_HSIC_PHY_A7_DOMAIN BIT(6)
-#define USB_OTG2_PHY_A7_DOMAIN BIT(5)
-#define USB_OTG1_PHY_A7_DOMAIN BIT(4)
-#define PCIE_PHY_A7_DOMAIN BIT(3)
-#define MIPI_PHY_A7_DOMAIN BIT(2)
+#define USB_HSIC_PHY_A_DOMAIN BIT(6)
+#define USB_OTG2_PHY_A_DOMAIN BIT(5)
+#define USB_OTG1_PHY_A_DOMAIN BIT(4)
+#define PCIE_PHY_A_DOMAIN BIT(3)
+#define MIPI_PHY_A_DOMAIN BIT(2)
#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
#define GPC_PU_PGC_SW_PDN_REQ 0x104
@@ -167,7 +167,7 @@ static const struct imx7_pgc_domain imx7_pgc_domains[] = {
},
.bits = {
.pxx = MIPI_PHY_SW_Pxx_REQ,
- .map = MIPI_PHY_A7_DOMAIN,
+ .map = MIPI_PHY_A_DOMAIN,
},
.voltage = 1000000,
.pgc = PGC_MIPI,
@@ -179,7 +179,7 @@ static const struct imx7_pgc_domain imx7_pgc_domains[] = {
},
.bits = {
.pxx = PCIE_PHY_SW_Pxx_REQ,
- .map = PCIE_PHY_A7_DOMAIN,
+ .map = PCIE_PHY_A_DOMAIN,
},
.voltage = 1000000,
.pgc = PGC_PCIE,
@@ -191,7 +191,7 @@ static const struct imx7_pgc_domain imx7_pgc_domains[] = {
},
.bits = {
.pxx = USB_HSIC_PHY_SW_Pxx_REQ,
- .map = USB_HSIC_PHY_A7_DOMAIN,
+ .map = USB_HSIC_PHY_A_DOMAIN,
},
.voltage = 1200000,
.pgc = PGC_USB_HSIC,
--
2.20.1
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v2 04/15] soc: imx: gpcv2: make pgc driver more generic for other i.MX platforms
2019-02-05 21:53 [PATCH v2 00/15] PCIE support for i.MX8MQ Andrey Smirnov
` (2 preceding siblings ...)
2019-02-05 21:53 ` [PATCH v2 03/15] soc: imx: gpcv2: use A_CORE instread of A7 for more i.MX platforms Andrey Smirnov
@ 2019-02-05 21:54 ` Andrey Smirnov
2019-02-05 21:54 ` [PATCH v2 05/15] soc: imx: gpcv2: Switch to SPDX identifier Andrey Smirnov
` (11 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Andrey Smirnov @ 2019-02-05 21:54 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Port of a Linux commit 73f59712a1a3e532a2cbfe582ecfdbf56c33297d
i.MX8MQ and i.MX8MM share same gpc module with i.MX7D, they
can reuse gpcv2 pgc driver for power domain control, this
patch renames all functions and structure definitions started
with "imx7" to "imx", and use .data in imx_gpcv2_dt_ids[] to
pass platform specific power domain data for power domain
driver, thus make gpcv2 pgc driver more generic for i.MX
platforms.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/soc/imx/gpcv2.c | 68 +++++++++++++++++++++++++----------------
1 file changed, 41 insertions(+), 27 deletions(-)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index a48f6d9a7..0b428bfc1 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -14,6 +14,7 @@
* http://www.gnu.org/copyleft/gpl.html
*/
+#include <of_device.h>
#include <common.h>
#include <clock.h>
#include <abort.h>
@@ -59,7 +60,7 @@
#define GPC_PGC_CTRL_PCR BIT(0)
-struct imx7_pgc_domain {
+struct imx_pgc_domain {
struct generic_pm_domain genpd;
void __iomem *base;
struct regulator *regulator;
@@ -75,12 +76,17 @@ struct imx7_pgc_domain {
struct device_d *dev;
};
-static int imx7_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
+struct imx_pgc_domain_data {
+ const struct imx_pgc_domain *domains;
+ size_t domains_num;
+};
+
+static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
bool on)
{
- struct imx7_pgc_domain *domain = container_of(genpd,
- struct imx7_pgc_domain,
- genpd);
+ struct imx_pgc_domain *domain = container_of(genpd,
+ struct imx_pgc_domain,
+ genpd);
unsigned int offset = on ?
GPC_PU_PGC_SW_PUP_REQ : GPC_PU_PGC_SW_PDN_REQ;
const bool enable_power_control = !on;
@@ -150,17 +156,17 @@ unmap:
return ret;
}
-static int imx7_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd)
+static int imx_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd)
{
- return imx7_gpc_pu_pgc_sw_pxx_req(genpd, true);
+ return imx_gpc_pu_pgc_sw_pxx_req(genpd, true);
}
-static int imx7_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
+static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
{
- return imx7_gpc_pu_pgc_sw_pxx_req(genpd, false);
+ return imx_gpc_pu_pgc_sw_pxx_req(genpd, false);
}
-static const struct imx7_pgc_domain imx7_pgc_domains[] = {
+static const struct imx_pgc_domain imx7_pgc_domains[] = {
[IMX7_POWER_DOMAIN_MIPI_PHY] = {
.genpd = {
.name = "mipi-phy",
@@ -198,9 +204,14 @@ static const struct imx7_pgc_domain imx7_pgc_domains[] = {
},
};
-static int imx7_pgc_domain_probe(struct device_d *dev)
+static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
+ .domains = imx7_pgc_domains,
+ .domains_num = ARRAY_SIZE(imx7_pgc_domains),
+};
+
+static int imx_pgc_domain_probe(struct device_d *dev)
{
- struct imx7_pgc_domain *domain = dev->priv;
+ struct imx_pgc_domain *domain = dev->priv;
int ret;
domain->dev = dev;
@@ -232,24 +243,25 @@ static int imx7_pgc_domain_probe(struct device_d *dev)
return ret;
}
-static const struct platform_device_id imx7_pgc_domain_id[] = {
- { "imx7-pgc-domain", },
+static const struct platform_device_id imx_pgc_domain_id[] = {
+ { "imx-pgc-domain", },
{ },
};
-static struct driver_d imx7_pgc_domain_driver = {
+static struct driver_d imx_pgc_domain_driver = {
.name = "imx-pgc",
- .probe = imx7_pgc_domain_probe,
- .id_table = imx7_pgc_domain_id,
+ .probe = imx_pgc_domain_probe,
+ .id_table = imx_pgc_domain_id,
};
-coredevice_platform_driver(imx7_pgc_domain_driver);
+coredevice_platform_driver(imx_pgc_domain_driver);
static int imx_gpcv2_probe(struct device_d *dev)
{
+ static const struct imx_pgc_domain_data *domain_data;
struct device_node *pgc_np, *np;
struct resource *res;
void __iomem *base;
- int ret;
+ int ret;
pgc_np = of_get_child_by_name(dev->device_node, "pgc");
if (!pgc_np) {
@@ -263,9 +275,11 @@ static int imx_gpcv2_probe(struct device_d *dev)
base = IOMEM(res->start);
+ domain_data = of_device_get_match_data(dev);
+
for_each_child_of_node(pgc_np, np) {
struct device_d *pd_dev;
- struct imx7_pgc_domain *domain;
+ struct imx_pgc_domain *domain;
u32 domain_index;
ret = of_property_read_u32(np, "reg", &domain_index);
if (ret) {
@@ -273,18 +287,18 @@ static int imx_gpcv2_probe(struct device_d *dev)
return ret;
}
- if (domain_index >= ARRAY_SIZE(imx7_pgc_domains)) {
+ if (domain_index >= domain_data->domains_num) {
dev_warn(dev,
"Domain index %d is out of bounds\n",
domain_index);
continue;
}
- domain = xmemdup(&imx7_pgc_domains[domain_index],
- sizeof(imx7_pgc_domains[domain_index]));
+ domain = xmemdup(&domain_data->domains[domain_index],
+ sizeof(domain_data->domains[domain_index]));
domain->base = base;
- domain->genpd.power_on = imx7_gpc_pu_pgc_sw_pup_req;
- domain->genpd.power_off = imx7_gpc_pu_pgc_sw_pdn_req;
+ domain->genpd.power_on = imx_gpc_pu_pgc_sw_pup_req;
+ domain->genpd.power_off = imx_gpc_pu_pgc_sw_pdn_req;
pd_dev = xzalloc(sizeof(*pd_dev));
pd_dev->device_node = np;
@@ -292,7 +306,7 @@ static int imx_gpcv2_probe(struct device_d *dev)
pd_dev->parent = dev;
pd_dev->priv = domain;
pd_dev->device_node = np;
- dev_set_name(pd_dev, imx7_pgc_domain_id[0].name);
+ dev_set_name(pd_dev, imx_pgc_domain_id[0].name);
ret = platform_device_register(pd_dev);
if (ret)
@@ -303,7 +317,7 @@ static int imx_gpcv2_probe(struct device_d *dev)
}
static const struct of_device_id imx_gpcv2_dt_ids[] = {
- { .compatible = "fsl,imx7d-gpc" },
+ { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data },
{ }
};
--
2.20.1
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v2 05/15] soc: imx: gpcv2: Switch to SPDX identifier
2019-02-05 21:53 [PATCH v2 00/15] PCIE support for i.MX8MQ Andrey Smirnov
` (3 preceding siblings ...)
2019-02-05 21:54 ` [PATCH v2 04/15] soc: imx: gpcv2: make pgc driver more generic for other " Andrey Smirnov
@ 2019-02-05 21:54 ` Andrey Smirnov
2019-02-05 21:54 ` [PATCH v2 06/15] soc: imx: gpcv2: prefix i.MX7 specific defines Andrey Smirnov
` (10 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Andrey Smirnov @ 2019-02-05 21:54 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Port of a Linux commit 8d8e3b7d8f06f69005d829d4a195b00ef976004b
Adopt the SPDX license identifier headers to ease license compliance
management.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/soc/imx/gpcv2.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 0b428bfc1..7bf45d42b 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017 Impinj, Inc
* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
@@ -5,13 +6,6 @@
* Based on the code of analogus driver:
*
* Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <of_device.h>
--
2.20.1
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v2 06/15] soc: imx: gpcv2: prefix i.MX7 specific defines
2019-02-05 21:53 [PATCH v2 00/15] PCIE support for i.MX8MQ Andrey Smirnov
` (4 preceding siblings ...)
2019-02-05 21:54 ` [PATCH v2 05/15] soc: imx: gpcv2: Switch to SPDX identifier Andrey Smirnov
@ 2019-02-05 21:54 ` Andrey Smirnov
2019-02-05 21:54 ` [PATCH v2 07/15] soc: imx: gpcv2: add support for i.MX8MQ SoC Andrey Smirnov
` (9 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Andrey Smirnov @ 2019-02-05 21:54 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Port of a Linux commit a800f418420d37f60fa471665a156c45d2702437
So we can add i.MX8M support without introducing name clashes.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/soc/imx/gpcv2.c | 44 ++++++++++++++++++++---------------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 7bf45d42b..24a6b96c1 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -24,19 +24,19 @@
#define GPC_LPCR_A_BSC 0x000
#define GPC_PGC_CPU_MAPPING 0x0ec
-#define USB_HSIC_PHY_A_DOMAIN BIT(6)
-#define USB_OTG2_PHY_A_DOMAIN BIT(5)
-#define USB_OTG1_PHY_A_DOMAIN BIT(4)
-#define PCIE_PHY_A_DOMAIN BIT(3)
-#define MIPI_PHY_A_DOMAIN BIT(2)
+#define IMX7_USB_HSIC_PHY_A_DOMAIN BIT(6)
+#define IMX7_USB_OTG2_PHY_A_DOMAIN BIT(5)
+#define IMX7_USB_OTG1_PHY_A_DOMAIN BIT(4)
+#define IMX7_PCIE_PHY_A_DOMAIN BIT(3)
+#define IMX7_MIPI_PHY_A_DOMAIN BIT(2)
#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
#define GPC_PU_PGC_SW_PDN_REQ 0x104
-#define USB_HSIC_PHY_SW_Pxx_REQ BIT(4)
-#define USB_OTG2_PHY_SW_Pxx_REQ BIT(3)
-#define USB_OTG1_PHY_SW_Pxx_REQ BIT(2)
-#define PCIE_PHY_SW_Pxx_REQ BIT(1)
-#define MIPI_PHY_SW_Pxx_REQ BIT(0)
+#define IMX7_USB_HSIC_PHY_SW_Pxx_REQ BIT(4)
+#define IMX7_USB_OTG2_PHY_SW_Pxx_REQ BIT(3)
+#define IMX7_USB_OTG1_PHY_SW_Pxx_REQ BIT(2)
+#define IMX7_PCIE_PHY_SW_Pxx_REQ BIT(1)
+#define IMX7_MIPI_PHY_SW_Pxx_REQ BIT(0)
#define GPC_M4_PU_PDN_FLG 0x1bc
@@ -46,9 +46,9 @@
* GPC_PGC memory map are incorrect, below offset
* values are from design RTL.
*/
-#define PGC_MIPI 16
-#define PGC_PCIE 17
-#define PGC_USB_HSIC 20
+#define IMX7_PGC_MIPI 16
+#define IMX7_PGC_PCIE 17
+#define IMX7_PGC_USB_HSIC 20
#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
@@ -166,11 +166,11 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
.name = "mipi-phy",
},
.bits = {
- .pxx = MIPI_PHY_SW_Pxx_REQ,
- .map = MIPI_PHY_A_DOMAIN,
+ .pxx = IMX7_MIPI_PHY_SW_Pxx_REQ,
+ .map = IMX7_MIPI_PHY_A_DOMAIN,
},
.voltage = 1000000,
- .pgc = PGC_MIPI,
+ .pgc = IMX7_PGC_MIPI,
},
[IMX7_POWER_DOMAIN_PCIE_PHY] = {
@@ -178,11 +178,11 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
.name = "pcie-phy",
},
.bits = {
- .pxx = PCIE_PHY_SW_Pxx_REQ,
- .map = PCIE_PHY_A_DOMAIN,
+ .pxx = IMX7_PCIE_PHY_SW_Pxx_REQ,
+ .map = IMX7_PCIE_PHY_A_DOMAIN,
},
.voltage = 1000000,
- .pgc = PGC_PCIE,
+ .pgc = IMX7_PGC_PCIE,
},
[IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
@@ -190,11 +190,11 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
.name = "usb-hsic-phy",
},
.bits = {
- .pxx = USB_HSIC_PHY_SW_Pxx_REQ,
- .map = USB_HSIC_PHY_A_DOMAIN,
+ .pxx = IMX7_USB_HSIC_PHY_SW_Pxx_REQ,
+ .map = IMX7_USB_HSIC_PHY_A_DOMAIN,
},
.voltage = 1200000,
- .pgc = PGC_USB_HSIC,
+ .pgc = IMX7_PGC_USB_HSIC,
},
};
--
2.20.1
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v2 07/15] soc: imx: gpcv2: add support for i.MX8MQ SoC
2019-02-05 21:53 [PATCH v2 00/15] PCIE support for i.MX8MQ Andrey Smirnov
` (5 preceding siblings ...)
2019-02-05 21:54 ` [PATCH v2 06/15] soc: imx: gpcv2: prefix i.MX7 specific defines Andrey Smirnov
@ 2019-02-05 21:54 ` Andrey Smirnov
2019-02-05 21:54 ` [PATCH v2 08/15] reset: Constify "ops" in struct reset_controller_dev Andrey Smirnov
` (8 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Andrey Smirnov @ 2019-02-05 21:54 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Port of a Linux commit 685efffe37c921cf1d56dd3c8617dc67bc343a99
The GPCv2 on the Freescale i.MX8MQ SoC works in the same way as the
GPCv2 on the i.MX7, but only controls more power domains with a
different mapping.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/soc/imx/Kconfig | 8 +-
drivers/soc/imx/Makefile | 2 +-
drivers/soc/imx/gpcv2.c | 175 +++++++++++++++++++++++++++++++++++++++
3 files changed, 180 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/imx/Kconfig b/drivers/soc/imx/Kconfig
index a78a9e396..32ec76fea 100644
--- a/drivers/soc/imx/Kconfig
+++ b/drivers/soc/imx/Kconfig
@@ -1,9 +1,9 @@
menu "i.MX SoC drivers"
-config IMX7_PM_DOMAINS
- bool "i.MX7 PM domains"
- depends on ARCH_IMX7
+config IMX_GPCV2_PM_DOMAINS
+ bool "i.MX GPCv2 PM domains"
+ depends on ARCH_IMX7 || ARCH_IMX8MQ
select PM_GENERIC_DOMAINS
- default y if ARCH_IMX7
+ default y if ARCH_IMX7 || ARCH_IMX8MQ
endmenu
diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile
index b039f77dc..d60056c7b 100644
--- a/drivers/soc/imx/Makefile
+++ b/drivers/soc/imx/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_IMX7_PM_DOMAINS) += gpcv2.o
+obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 24a6b96c1..bc373ecf4 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -21,23 +21,55 @@
#include <regulator.h>
#include <dt-bindings/power/imx7-power.h>
+#include <dt-bindings/power/imx8mq-power.h>
+
#define GPC_LPCR_A_BSC 0x000
#define GPC_PGC_CPU_MAPPING 0x0ec
+
#define IMX7_USB_HSIC_PHY_A_DOMAIN BIT(6)
#define IMX7_USB_OTG2_PHY_A_DOMAIN BIT(5)
#define IMX7_USB_OTG1_PHY_A_DOMAIN BIT(4)
#define IMX7_PCIE_PHY_A_DOMAIN BIT(3)
#define IMX7_MIPI_PHY_A_DOMAIN BIT(2)
+#define IMX8M_PCIE2_A53_DOMAIN BIT(15)
+#define IMX8M_MIPI_CSI2_A53_DOMAIN BIT(14)
+#define IMX8M_MIPI_CSI1_A53_DOMAIN BIT(13)
+#define IMX8M_DISP_A53_DOMAIN BIT(12)
+#define IMX8M_HDMI_A53_DOMAIN BIT(11)
+#define IMX8M_VPU_A53_DOMAIN BIT(10)
+#define IMX8M_GPU_A53_DOMAIN BIT(9)
+#define IMX8M_DDR2_A53_DOMAIN BIT(8)
+#define IMX8M_DDR1_A53_DOMAIN BIT(7)
+#define IMX8M_OTG2_A53_DOMAIN BIT(5)
+#define IMX8M_OTG1_A53_DOMAIN BIT(4)
+#define IMX8M_PCIE1_A53_DOMAIN BIT(3)
+#define IMX8M_MIPI_A53_DOMAIN BIT(2)
+
#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
#define GPC_PU_PGC_SW_PDN_REQ 0x104
+
#define IMX7_USB_HSIC_PHY_SW_Pxx_REQ BIT(4)
#define IMX7_USB_OTG2_PHY_SW_Pxx_REQ BIT(3)
#define IMX7_USB_OTG1_PHY_SW_Pxx_REQ BIT(2)
#define IMX7_PCIE_PHY_SW_Pxx_REQ BIT(1)
#define IMX7_MIPI_PHY_SW_Pxx_REQ BIT(0)
+#define IMX8M_PCIE2_SW_Pxx_REQ BIT(13)
+#define IMX8M_MIPI_CSI2_SW_Pxx_REQ BIT(12)
+#define IMX8M_MIPI_CSI1_SW_Pxx_REQ BIT(11)
+#define IMX8M_DISP_SW_Pxx_REQ BIT(10)
+#define IMX8M_HDMI_SW_Pxx_REQ BIT(9)
+#define IMX8M_VPU_SW_Pxx_REQ BIT(8)
+#define IMX8M_GPU_SW_Pxx_REQ BIT(7)
+#define IMX8M_DDR2_SW_Pxx_REQ BIT(6)
+#define IMX8M_DDR1_SW_Pxx_REQ BIT(5)
+#define IMX8M_OTG2_SW_Pxx_REQ BIT(3)
+#define IMX8M_OTG1_SW_Pxx_REQ BIT(2)
+#define IMX8M_PCIE1_SW_Pxx_REQ BIT(1)
+#define IMX8M_MIPI_SW_Pxx_REQ BIT(0)
+
#define GPC_M4_PU_PDN_FLG 0x1bc
/*
@@ -49,6 +81,20 @@
#define IMX7_PGC_MIPI 16
#define IMX7_PGC_PCIE 17
#define IMX7_PGC_USB_HSIC 20
+
+
+#define IMX8M_PGC_MIPI 16
+#define IMX8M_PGC_PCIE1 17
+#define IMX8M_PGC_OTG1 18
+#define IMX8M_PGC_OTG2 19
+#define IMX8M_PGC_DDR1 21
+#define IMX8M_PGC_GPU 23
+#define IMX8M_PGC_VPU 24
+#define IMX8M_PGC_DISP 26
+#define IMX8M_PGC_MIPI_CSI1 27
+#define IMX8M_PGC_MIPI_CSI2 28
+#define IMX8M_PGC_PCIE2 29
+
#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
@@ -203,6 +249,134 @@ static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
.domains_num = ARRAY_SIZE(imx7_pgc_domains),
};
+static const struct imx_pgc_domain imx8m_pgc_domains[] = {
+ [IMX8M_POWER_DOMAIN_MIPI] = {
+ .genpd = {
+ .name = "mipi",
+ },
+ .bits = {
+ .pxx = IMX8M_MIPI_SW_Pxx_REQ,
+ .map = IMX8M_MIPI_A53_DOMAIN,
+ },
+ .pgc = IMX8M_PGC_MIPI,
+ },
+
+ [IMX8M_POWER_DOMAIN_PCIE1] = {
+ .genpd = {
+ .name = "pcie1",
+ },
+ .bits = {
+ .pxx = IMX8M_PCIE1_SW_Pxx_REQ,
+ .map = IMX8M_PCIE1_A53_DOMAIN,
+ },
+ .pgc = IMX8M_PGC_PCIE1,
+ },
+
+ [IMX8M_POWER_DOMAIN_USB_OTG1] = {
+ .genpd = {
+ .name = "usb-otg1",
+ },
+ .bits = {
+ .pxx = IMX8M_OTG1_SW_Pxx_REQ,
+ .map = IMX8M_OTG1_A53_DOMAIN,
+ },
+ .pgc = IMX8M_PGC_OTG1,
+ },
+
+ [IMX8M_POWER_DOMAIN_USB_OTG2] = {
+ .genpd = {
+ .name = "usb-otg2",
+ },
+ .bits = {
+ .pxx = IMX8M_OTG2_SW_Pxx_REQ,
+ .map = IMX8M_OTG2_A53_DOMAIN,
+ },
+ .pgc = IMX8M_PGC_OTG2,
+ },
+
+ [IMX8M_POWER_DOMAIN_DDR1] = {
+ .genpd = {
+ .name = "ddr1",
+ },
+ .bits = {
+ .pxx = IMX8M_DDR1_SW_Pxx_REQ,
+ .map = IMX8M_DDR2_A53_DOMAIN,
+ },
+ .pgc = IMX8M_PGC_DDR1,
+ },
+
+ [IMX8M_POWER_DOMAIN_GPU] = {
+ .genpd = {
+ .name = "gpu",
+ },
+ .bits = {
+ .pxx = IMX8M_GPU_SW_Pxx_REQ,
+ .map = IMX8M_GPU_A53_DOMAIN,
+ },
+ .pgc = IMX8M_PGC_GPU,
+ },
+
+ [IMX8M_POWER_DOMAIN_VPU] = {
+ .genpd = {
+ .name = "vpu",
+ },
+ .bits = {
+ .pxx = IMX8M_VPU_SW_Pxx_REQ,
+ .map = IMX8M_VPU_A53_DOMAIN,
+ },
+ .pgc = IMX8M_PGC_VPU,
+ },
+
+ [IMX8M_POWER_DOMAIN_DISP] = {
+ .genpd = {
+ .name = "disp",
+ },
+ .bits = {
+ .pxx = IMX8M_DISP_SW_Pxx_REQ,
+ .map = IMX8M_DISP_A53_DOMAIN,
+ },
+ .pgc = IMX8M_PGC_DISP,
+ },
+
+ [IMX8M_POWER_DOMAIN_MIPI_CSI1] = {
+ .genpd = {
+ .name = "mipi-csi1",
+ },
+ .bits = {
+ .pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ,
+ .map = IMX8M_MIPI_CSI1_A53_DOMAIN,
+ },
+ .pgc = IMX8M_PGC_MIPI_CSI1,
+ },
+
+ [IMX8M_POWER_DOMAIN_MIPI_CSI2] = {
+ .genpd = {
+ .name = "mipi-csi2",
+ },
+ .bits = {
+ .pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ,
+ .map = IMX8M_MIPI_CSI2_A53_DOMAIN,
+ },
+ .pgc = IMX8M_PGC_MIPI_CSI2,
+ },
+
+ [IMX8M_POWER_DOMAIN_PCIE2] = {
+ .genpd = {
+ .name = "pcie2",
+ },
+ .bits = {
+ .pxx = IMX8M_PCIE2_SW_Pxx_REQ,
+ .map = IMX8M_PCIE2_A53_DOMAIN,
+ },
+ .pgc = IMX8M_PGC_PCIE2,
+ },
+};
+
+static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
+ .domains = imx8m_pgc_domains,
+ .domains_num = ARRAY_SIZE(imx8m_pgc_domains),
+};
+
static int imx_pgc_domain_probe(struct device_d *dev)
{
struct imx_pgc_domain *domain = dev->priv;
@@ -312,6 +486,7 @@ static int imx_gpcv2_probe(struct device_d *dev)
static const struct of_device_id imx_gpcv2_dt_ids[] = {
{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data },
+ { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
{ }
};
--
2.20.1
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v2 08/15] reset: Constify "ops" in struct reset_controller_dev
2019-02-05 21:53 [PATCH v2 00/15] PCIE support for i.MX8MQ Andrey Smirnov
` (6 preceding siblings ...)
2019-02-05 21:54 ` [PATCH v2 07/15] soc: imx: gpcv2: add support for i.MX8MQ SoC Andrey Smirnov
@ 2019-02-05 21:54 ` Andrey Smirnov
2019-02-05 21:54 ` [PATCH v2 09/15] reset: imx7: Add plubming to support multiple IP variants Andrey Smirnov
` (7 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Andrey Smirnov @ 2019-02-05 21:54 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/reset/reset-socfpga.c | 2 +-
include/linux/reset-controller.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index b6faa0217..9b499f23c 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -73,7 +73,7 @@ static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
return 0;
}
-static struct reset_control_ops socfpga_reset_ops = {
+static const struct reset_control_ops socfpga_reset_ops = {
.assert = socfpga_reset_assert,
.deassert = socfpga_reset_deassert,
};
diff --git a/include/linux/reset-controller.h b/include/linux/reset-controller.h
index d8265486a..aff03a9c6 100644
--- a/include/linux/reset-controller.h
+++ b/include/linux/reset-controller.h
@@ -35,7 +35,7 @@ struct of_phandle_args;
* @nr_resets: number of reset controls in this reset controller device
*/
struct reset_controller_dev {
- struct reset_control_ops *ops;
+ const struct reset_control_ops *ops;
struct list_head list;
struct device_node *of_node;
int of_reset_n_cells;
--
2.20.1
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v2 09/15] reset: imx7: Add plubming to support multiple IP variants
2019-02-05 21:53 [PATCH v2 00/15] PCIE support for i.MX8MQ Andrey Smirnov
` (7 preceding siblings ...)
2019-02-05 21:54 ` [PATCH v2 08/15] reset: Constify "ops" in struct reset_controller_dev Andrey Smirnov
@ 2019-02-05 21:54 ` Andrey Smirnov
2019-02-05 21:54 ` [PATCH v2 10/15] include: Import dt-bindings/reset/imx8mq-reset.h Andrey Smirnov
` (6 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Andrey Smirnov @ 2019-02-05 21:54 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Port of a Linux commit cffaab878178c7842ab38690070d665adb3f41fd
In order to enable supporting i.MX8MQ with this driver, convert it to
expect variant specific bits to be passed via driver data.
Cc: p.zabel@pengutronix.de
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: cphealy@gmail.com
Cc: l.stach@pengutronix.de
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/reset/reset-imx7.c | 50 +++++++++++++++++++++++++++-----------
1 file changed, 36 insertions(+), 14 deletions(-)
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index 6dc5de16a..f723dc28e 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -22,10 +22,22 @@
#include <linux/reset-controller.h>
#include <mfd/syscon.h>
#include <regmap.h>
+#include <of_device.h>
+
+struct imx7_src_signal {
+ unsigned int offset, bit;
+};
+
+struct imx7_src_variant {
+ const struct imx7_src_signal *signals;
+ unsigned int signals_num;
+ struct reset_control_ops ops;
+};
struct imx7_src {
struct reset_controller_dev rcdev;
struct regmap *regmap;
+ const struct imx7_src_signal *signals;
};
enum imx7_src_registers {
@@ -40,9 +52,14 @@ enum imx7_src_registers {
SRC_DDRC_RCR = 0x1000,
};
-struct imx7_src_signal {
- unsigned int offset, bit;
-};
+static int imx7_reset_update(struct imx7_src *imx7src,
+ unsigned long id, unsigned int value)
+{
+ const struct imx7_src_signal *signal = &imx7src->signals[id];
+
+ return regmap_update_bits(imx7src->regmap,
+ signal->offset, signal->bit, value);
+}
static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {
[IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
@@ -81,8 +98,8 @@ static int imx7_reset_set(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct imx7_src *imx7src = to_imx7_src(rcdev);
- const struct imx7_src_signal *signal = &imx7_src_signals[id];
- unsigned int value = assert ? signal->bit : 0;;
+ const unsigned int bit = imx7src->signals[id].bit;
+ unsigned int value = assert ? bit : 0;
switch (id) {
case IMX7_RESET_PCIEPHY:
@@ -95,12 +112,11 @@ static int imx7_reset_set(struct reset_controller_dev *rcdev,
break;
case IMX7_RESET_PCIE_CTRL_APPS_EN:
- value = (assert) ? 0 : signal->bit;
+ value = assert ? 0 : bit;
break;
}
- return regmap_update_bits(imx7src->regmap,
- signal->offset, signal->bit, value);
+ return imx7_reset_update(imx7src, id, value);
}
static int imx7_reset_assert(struct reset_controller_dev *rcdev,
@@ -115,31 +131,37 @@ static int imx7_reset_deassert(struct reset_controller_dev *rcdev,
return imx7_reset_set(rcdev, id, false);
}
-static struct reset_control_ops imx7_reset_ops = {
- .assert = imx7_reset_assert,
- .deassert = imx7_reset_deassert,
+static const struct imx7_src_variant variant_imx7 = {
+ .signals = imx7_src_signals,
+ .signals_num = ARRAY_SIZE(imx7_src_signals),
+ .ops = {
+ .assert = imx7_reset_assert,
+ .deassert = imx7_reset_deassert,
+ },
};
static int imx7_reset_probe(struct device_d *dev)
{
struct imx7_src *imx7src;
+ const struct imx7_src_variant *variant = of_device_get_match_data(dev);
imx7src = xzalloc(sizeof(*imx7src));
+ imx7src->signals = variant->signals;
imx7src->regmap = syscon_node_to_regmap(dev->device_node);
if (IS_ERR(imx7src->regmap)) {
dev_err(dev, "Unable to get imx7-src regmap");
return PTR_ERR(imx7src->regmap);
}
- imx7src->rcdev.nr_resets = IMX7_RESET_NUM;
- imx7src->rcdev.ops = &imx7_reset_ops;
+ imx7src->rcdev.nr_resets = variant->signals_num;
+ imx7src->rcdev.ops = &variant->ops;
imx7src->rcdev.of_node = dev->device_node;
return reset_controller_register(&imx7src->rcdev);
}
static const struct of_device_id imx7_reset_dt_ids[] = {
- { .compatible = "fsl,imx7d-src", },
+ { .compatible = "fsl,imx7d-src", .data = &variant_imx7 },
{ /* sentinel */ },
};
--
2.20.1
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v2 10/15] include: Import dt-bindings/reset/imx8mq-reset.h
2019-02-05 21:53 [PATCH v2 00/15] PCIE support for i.MX8MQ Andrey Smirnov
` (8 preceding siblings ...)
2019-02-05 21:54 ` [PATCH v2 09/15] reset: imx7: Add plubming to support multiple IP variants Andrey Smirnov
@ 2019-02-05 21:54 ` Andrey Smirnov
2019-02-05 21:54 ` [PATCH v2 11/15] reset: imx7: Add support for i.MX8MQ IP block variant Andrey Smirnov
` (5 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Andrey Smirnov @ 2019-02-05 21:54 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Import dt-bindings/reset/imx8mq-reset.h from Liunx kernel until that
file trickles down into dts/include/.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
include/dt-bindings/reset/imx8mq-reset.h | 64 ++++++++++++++++++++++++
1 file changed, 64 insertions(+)
create mode 100644 include/dt-bindings/reset/imx8mq-reset.h
diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h
new file mode 100644
index 000000000..57c592498
--- /dev/null
+++ b/include/dt-bindings/reset/imx8mq-reset.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Zodiac Inflight Innovations
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ */
+
+#ifndef DT_BINDING_RESET_IMX8MQ_H
+#define DT_BINDING_RESET_IMX8MQ_H
+
+#define IMX8MQ_RESET_A53_CORE_POR_RESET0 0
+#define IMX8MQ_RESET_A53_CORE_POR_RESET1 1
+#define IMX8MQ_RESET_A53_CORE_POR_RESET2 2
+#define IMX8MQ_RESET_A53_CORE_POR_RESET3 3
+#define IMX8MQ_RESET_A53_CORE_RESET0 4
+#define IMX8MQ_RESET_A53_CORE_RESET1 5
+#define IMX8MQ_RESET_A53_CORE_RESET2 6
+#define IMX8MQ_RESET_A53_CORE_RESET3 7
+#define IMX8MQ_RESET_A53_DBG_RESET0 8
+#define IMX8MQ_RESET_A53_DBG_RESET1 9
+#define IMX8MQ_RESET_A53_DBG_RESET2 10
+#define IMX8MQ_RESET_A53_DBG_RESET3 11
+#define IMX8MQ_RESET_A53_ETM_RESET0 12
+#define IMX8MQ_RESET_A53_ETM_RESET1 13
+#define IMX8MQ_RESET_A53_ETM_RESET2 14
+#define IMX8MQ_RESET_A53_ETM_RESET3 15
+#define IMX8MQ_RESET_A53_SOC_DBG_RESET 16
+#define IMX8MQ_RESET_A53_L2RESET 17
+#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18
+#define IMX8MQ_RESET_OTG1_PHY_RESET 19
+#define IMX8MQ_RESET_OTG2_PHY_RESET 20
+#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21
+#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22
+#define IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N 23
+#define IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N 24
+#define IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N 25
+#define IMX8MQ_RESET_PCIEPHY 26
+#define IMX8MQ_RESET_PCIEPHY_PERST 27
+#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28
+#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29
+#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30
+#define IMX8MQ_RESET_DISP_RESET 31
+#define IMX8MQ_RESET_GPU_RESET 32
+#define IMX8MQ_RESET_VPU_RESET 33
+#define IMX8MQ_RESET_PCIEPHY2 34
+#define IMX8MQ_RESET_PCIEPHY2_PERST 35
+#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36
+#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37
+#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38
+#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39
+#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40
+#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41
+#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42
+#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43
+#define IMX8MQ_RESET_DDRC1_PRST 44
+#define IMX8MQ_RESET_DDRC1_CORE_RESET 45
+#define IMX8MQ_RESET_DDRC1_PHY_RESET 46
+#define IMX8MQ_RESET_DDRC2_PRST 47
+#define IMX8MQ_RESET_DDRC2_CORE_RESET 48
+#define IMX8MQ_RESET_DDRC2_PHY_RESET 49
+
+#define IMX8MQ_RESET_NUM 50
+
+#endif
--
2.20.1
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v2 11/15] reset: imx7: Add support for i.MX8MQ IP block variant
2019-02-05 21:53 [PATCH v2 00/15] PCIE support for i.MX8MQ Andrey Smirnov
` (9 preceding siblings ...)
2019-02-05 21:54 ` [PATCH v2 10/15] include: Import dt-bindings/reset/imx8mq-reset.h Andrey Smirnov
@ 2019-02-05 21:54 ` Andrey Smirnov
2019-02-05 21:54 ` [PATCH v2 12/15] PCI: imx6: Introduce drvdata Andrey Smirnov
` (4 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Andrey Smirnov @ 2019-02-05 21:54 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Port of a Linux commit 34be9b453608fa4475d2b48ee27df2023f08ef2d
Add bits and pieces needed to support IP block variant found on
i.MX8MQ SoCs.
Cc: p.zabel@pengutronix.de
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: cphealy@gmail.com
Cc: l.stach@pengutronix.de
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/reset/reset-imx7.c | 122 +++++++++++++++++++++++++++++++++++++
1 file changed, 122 insertions(+)
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index f723dc28e..9d4344a94 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -17,6 +17,7 @@
#include <common.h>
#include <dt-bindings/reset/imx7-reset.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
#include <init.h>
#include <linux/err.h>
#include <linux/reset-controller.h>
@@ -140,6 +141,126 @@ static const struct imx7_src_variant variant_imx7 = {
},
};
+enum imx8mq_src_registers {
+ SRC_A53RCR0 = 0x0004,
+ SRC_HDMI_RCR = 0x0030,
+ SRC_DISP_RCR = 0x0034,
+ SRC_GPU_RCR = 0x0040,
+ SRC_VPU_RCR = 0x0044,
+ SRC_PCIE2_RCR = 0x0048,
+ SRC_MIPIPHY1_RCR = 0x004c,
+ SRC_MIPIPHY2_RCR = 0x0050,
+ SRC_DDRC2_RCR = 0x1004,
+};
+
+static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
+ [IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
+ [IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
+ [IMX8MQ_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
+ [IMX8MQ_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
+ [IMX8MQ_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
+ [IMX8MQ_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
+ [IMX8MQ_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
+ [IMX8MQ_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
+ [IMX8MQ_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
+ [IMX8MQ_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
+ [IMX8MQ_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
+ [IMX8MQ_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
+ [IMX8MQ_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
+ [IMX8MQ_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
+ [IMX8MQ_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
+ [IMX8MQ_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
+ [IMX8MQ_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
+ [IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
+ [IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) },
+ [IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
+ [IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
+ [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) },
+ [IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) },
+ [IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) },
+ [IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) },
+ [IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) },
+ [IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR,
+ BIT(2) | BIT(1) },
+ [IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
+ [IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
+ [IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
+ [IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
+ [IMX8MQ_RESET_DISP_RESET] = { SRC_DISP_RCR, BIT(0) },
+ [IMX8MQ_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
+ [IMX8MQ_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
+ [IMX8MQ_RESET_PCIEPHY2] = { SRC_PCIE2_RCR,
+ BIT(2) | BIT(1) },
+ [IMX8MQ_RESET_PCIEPHY2_PERST] = { SRC_PCIE2_RCR, BIT(3) },
+ [IMX8MQ_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, BIT(6) },
+ [IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, BIT(11) },
+ [IMX8MQ_RESET_MIPI_CSI1_CORE_RESET] = { SRC_MIPIPHY1_RCR, BIT(0) },
+ [IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET] = { SRC_MIPIPHY1_RCR, BIT(1) },
+ [IMX8MQ_RESET_MIPI_CSI1_ESC_RESET] = { SRC_MIPIPHY1_RCR, BIT(2) },
+ [IMX8MQ_RESET_MIPI_CSI2_CORE_RESET] = { SRC_MIPIPHY2_RCR, BIT(0) },
+ [IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET] = { SRC_MIPIPHY2_RCR, BIT(1) },
+ [IMX8MQ_RESET_MIPI_CSI2_ESC_RESET] = { SRC_MIPIPHY2_RCR, BIT(2) },
+ [IMX8MQ_RESET_DDRC1_PRST] = { SRC_DDRC_RCR, BIT(0) },
+ [IMX8MQ_RESET_DDRC1_CORE_RESET] = { SRC_DDRC_RCR, BIT(1) },
+ [IMX8MQ_RESET_DDRC1_PHY_RESET] = { SRC_DDRC_RCR, BIT(2) },
+ [IMX8MQ_RESET_DDRC2_PHY_RESET] = { SRC_DDRC2_RCR, BIT(0) },
+ [IMX8MQ_RESET_DDRC2_CORE_RESET] = { SRC_DDRC2_RCR, BIT(1) },
+ [IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) },
+};
+
+static int imx8mq_reset_set(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+ struct imx7_src *imx7src = to_imx7_src(rcdev);
+ const unsigned int bit = imx7src->signals[id].bit;
+ unsigned int value = assert ? bit : 0;
+
+ switch (id) {
+ case IMX8MQ_RESET_PCIEPHY:
+ case IMX8MQ_RESET_PCIEPHY2: /* fallthrough */
+ /*
+ * wait for more than 10us to release phy g_rst and
+ * btnrst
+ */
+ if (!assert)
+ udelay(10);
+ break;
+
+ case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
+ case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */
+ case IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N: /* fallthrough */
+ case IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N: /* fallthrough */
+ case IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N: /* fallthrough */
+ case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */
+ case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */
+ value = assert ? 0 : bit;
+ break;
+ }
+
+ return imx7_reset_update(imx7src, id, value);
+}
+
+static int imx8mq_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return imx8mq_reset_set(rcdev, id, true);
+}
+
+static int imx8mq_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return imx8mq_reset_set(rcdev, id, false);
+}
+
+static const struct imx7_src_variant variant_imx8mq = {
+ .signals = imx8mq_src_signals,
+ .signals_num = ARRAY_SIZE(imx8mq_src_signals),
+ .ops = {
+ .assert = imx8mq_reset_assert,
+ .deassert = imx8mq_reset_deassert,
+ },
+};
+
static int imx7_reset_probe(struct device_d *dev)
{
struct imx7_src *imx7src;
@@ -162,6 +283,7 @@ static int imx7_reset_probe(struct device_d *dev)
static const struct of_device_id imx7_reset_dt_ids[] = {
{ .compatible = "fsl,imx7d-src", .data = &variant_imx7 },
+ { .compatible = "fsl,imx8mq-src", .data = &variant_imx8mq },
{ /* sentinel */ },
};
--
2.20.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v2 12/15] PCI: imx6: Introduce drvdata
2019-02-05 21:53 [PATCH v2 00/15] PCIE support for i.MX8MQ Andrey Smirnov
` (10 preceding siblings ...)
2019-02-05 21:54 ` [PATCH v2 11/15] reset: imx7: Add support for i.MX8MQ IP block variant Andrey Smirnov
@ 2019-02-05 21:54 ` Andrey Smirnov
2019-02-05 21:54 ` [PATCH v2 13/15] PCI: imx6: Mark PHY functions as i.MX6 specific Andrey Smirnov
` (3 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Andrey Smirnov @ 2019-02-05 21:54 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Port of a Linux commit e8e4d4e95701a10691c53165c55789e5e50ba3f5
Introduce driver data struct. This will simplify handling of device
specific differences.
Signed-off-by: Stefan Agner <stefan@agner.ch>
[andrew.smirnov@gmail.com reformatted drvdata, to simplify future diffs]
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/pci/pci-imx6.c | 43 ++++++++++++++++++++++++++++--------------
1 file changed, 29 insertions(+), 14 deletions(-)
diff --git a/drivers/pci/pci-imx6.c b/drivers/pci/pci-imx6.c
index c1719093b..dcebd7658 100644
--- a/drivers/pci/pci-imx6.c
+++ b/drivers/pci/pci-imx6.c
@@ -42,6 +42,10 @@ enum imx6_pcie_variants {
IMX7D,
};
+struct imx6_pcie_drvdata {
+ enum imx6_pcie_variants variant;
+};
+
struct imx6_pcie {
struct dw_pcie *pci;
int reset_gpio;
@@ -51,13 +55,13 @@ struct imx6_pcie {
void __iomem *iomuxc_gpr;
struct reset_control *pciephy_reset;
struct reset_control *apps_reset;
- enum imx6_pcie_variants variant;
u32 tx_deemph_gen1;
u32 tx_deemph_gen2_3p5db;
u32 tx_deemph_gen2_6db;
u32 tx_swing_full;
u32 tx_swing_low;
int link_gen;
+ const struct imx6_pcie_drvdata *drvdata;
};
/* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
@@ -248,7 +252,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
{
u32 gpr1;
- switch (imx6_pcie->variant) {
+ switch (imx6_pcie->drvdata->variant) {
case IMX7D:
reset_control_assert(imx6_pcie->pciephy_reset);
reset_control_assert(imx6_pcie->apps_reset);
@@ -273,7 +277,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
{
u32 gpr1;
- switch (imx6_pcie->variant) {
+ switch (imx6_pcie->drvdata->variant) {
case IMX6QP:
case IMX6Q: /* FALLTHROUGH */
/* power up core phy and enable ref clock */
@@ -359,7 +363,7 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
/*
* Release the PCIe PHY reset here
*/
- switch (imx6_pcie->variant) {
+ switch (imx6_pcie->drvdata->variant) {
case IMX7D:
reset_control_deassert(imx6_pcie->pciephy_reset);
imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
@@ -391,7 +395,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
gpr12 = readl(imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
- switch (imx6_pcie->variant) {
+ switch (imx6_pcie->drvdata->variant) {
case IMX7D:
gpr12 &= ~IMX7D_GPR12_PCIE_PHY_REFCLK_SEL;
writel(gpr12, imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
@@ -462,7 +466,7 @@ static void imx6_pcie_ltssm_enable(struct device_d *dev)
struct imx6_pcie *imx6_pcie = dev->priv;
u32 gpr12;
- switch (imx6_pcie->variant) {
+ switch (imx6_pcie->drvdata->variant) {
case IMX6Q:
case IMX6QP:
gpr12 = readl(imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
@@ -514,7 +518,7 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
tmp |= PORT_LOGIC_SPEED_CHANGE;
dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
- if (imx6_pcie->variant != IMX7D) {
+ if (imx6_pcie->drvdata->variant != IMX7D) {
/*
* On i.MX7, DIRECT_SPEED_CHANGE behaves
* differently from i.MX6 family when no link
@@ -616,8 +620,7 @@ static int imx6_pcie_probe(struct device_d *dev)
pci->ops = &dw_pcie_ops;
imx6_pcie->pci = pci;
- imx6_pcie->variant =
- (enum imx6_pcie_variants)of_device_get_match_data(dev);
+ imx6_pcie->drvdata = of_device_get_match_data(dev);
/* Fetch GPIOs */
imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
@@ -657,7 +660,7 @@ static int imx6_pcie_probe(struct device_d *dev)
return PTR_ERR(imx6_pcie->pcie);
}
- switch (imx6_pcie->variant) {
+ switch (imx6_pcie->drvdata->variant) {
case IMX7D:
imx6_pcie->iomuxc_gpr = IOMEM(MX7_IOMUXC_GPR_BASE_ADDR);
@@ -720,7 +723,7 @@ static void imx6_pcie_remove(struct device_d *dev)
{
struct imx6_pcie *imx6_pcie = dev->priv;
- if (imx6_pcie->variant == IMX6Q) {
+ if (imx6_pcie->drvdata->variant == IMX6Q) {
/*
* If the bootloader already enabled the link we need
* some special handling to get the core back into a
@@ -750,10 +753,22 @@ static void imx6_pcie_remove(struct device_d *dev)
imx6_pcie_assert_core_reset(imx6_pcie);
}
+static const struct imx6_pcie_drvdata drvdata[] = {
+ [IMX6Q] = {
+ .variant = IMX6Q,
+ },
+ [IMX6QP] = {
+ .variant = IMX6QP,
+ },
+ [IMX7D] = {
+ .variant = IMX7D,
+ },
+};
+
static struct of_device_id imx6_pcie_of_match[] = {
- { .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, },
- { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, },
- { .compatible = "fsl,imx7d-pcie", .data = (void *)IMX7D, },
+ { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
+ { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
+ { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
{},
};
--
2.20.1
_______________________________________________
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v2 13/15] PCI: imx6: Mark PHY functions as i.MX6 specific
2019-02-05 21:53 [PATCH v2 00/15] PCIE support for i.MX8MQ Andrey Smirnov
` (11 preceding siblings ...)
2019-02-05 21:54 ` [PATCH v2 12/15] PCI: imx6: Introduce drvdata Andrey Smirnov
@ 2019-02-05 21:54 ` Andrey Smirnov
2019-02-05 21:54 ` [PATCH v2 14/15] PCI: imx6: Convert DIRECT_SPEED_CHANGE quirk code to use a flag Andrey Smirnov
` (2 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Andrey Smirnov @ 2019-02-05 21:54 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Port of a Linux commit 2f532d07f0cce72f88a4a0532ae11be6a2745697
PCIe PHY IP block on i.MX7D differs from the one used on i.MX6 family,
so none of the code in the current implementation of
imx6_setup_phy_mpll() or imx6_pcie_reset_phy() is applicable.
Introduce IMX6_PCIE_FLAG_IMX6_PHY and check for it in the aforementioned
functions to make sure they are only executed on appropriate PCIe IP
variants.
Tested-by: Trent Piepho <tpiepho@impinj.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
[lorenzo.pieralisi@arm.com: updated log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/pci/pci-imx6.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/pci/pci-imx6.c b/drivers/pci/pci-imx6.c
index dcebd7658..2911a019c 100644
--- a/drivers/pci/pci-imx6.c
+++ b/drivers/pci/pci-imx6.c
@@ -42,8 +42,11 @@ enum imx6_pcie_variants {
IMX7D,
};
+#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
+
struct imx6_pcie_drvdata {
enum imx6_pcie_variants variant;
+ u32 flags;
};
struct imx6_pcie {
@@ -235,6 +238,9 @@ static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
{
uint32_t temp;
+ if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
+ return;
+
pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &temp);
temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
PHY_RX_OVRD_IN_LO_RX_PLL_EN);
@@ -756,9 +762,11 @@ static void imx6_pcie_remove(struct device_d *dev)
static const struct imx6_pcie_drvdata drvdata[] = {
[IMX6Q] = {
.variant = IMX6Q,
+ .flags = IMX6_PCIE_FLAG_IMX6_PHY,
},
[IMX6QP] = {
.variant = IMX6QP,
+ .flags = IMX6_PCIE_FLAG_IMX6_PHY,
},
[IMX7D] = {
.variant = IMX7D,
--
2.20.1
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v2 14/15] PCI: imx6: Convert DIRECT_SPEED_CHANGE quirk code to use a flag
2019-02-05 21:53 [PATCH v2 00/15] PCIE support for i.MX8MQ Andrey Smirnov
` (12 preceding siblings ...)
2019-02-05 21:54 ` [PATCH v2 13/15] PCI: imx6: Mark PHY functions as i.MX6 specific Andrey Smirnov
@ 2019-02-05 21:54 ` Andrey Smirnov
2019-02-05 21:54 ` [PATCH v2 15/15] PCI: imx6: Add support for i.MX8MQ Andrey Smirnov
2019-02-07 7:53 ` [PATCH v2 00/15] PCIE " Sascha Hauer
15 siblings, 0 replies; 17+ messages in thread
From: Andrey Smirnov @ 2019-02-05 21:54 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Port of a Linux commit 4c458bb347ae016e75f6c61dab95ce530f4ff6fc
Both i.MX7D and i.MX8MQ have the same behaviour when it comes to
clearing DIRECT_SPEED_CHANGE bit when no speed change occurs, so to
handle variants correctly add a flag instead of checking the IP block
variant.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
[lorenzo.pieralisi@arm.com: updated log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/pci/pci-imx6.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/pci-imx6.c b/drivers/pci/pci-imx6.c
index 2911a019c..d77c24990 100644
--- a/drivers/pci/pci-imx6.c
+++ b/drivers/pci/pci-imx6.c
@@ -43,6 +43,7 @@ enum imx6_pcie_variants {
};
#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
+#define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
struct imx6_pcie_drvdata {
enum imx6_pcie_variants variant;
@@ -524,7 +525,8 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
tmp |= PORT_LOGIC_SPEED_CHANGE;
dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
- if (imx6_pcie->drvdata->variant != IMX7D) {
+ if (imx6_pcie->drvdata->flags &
+ IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) {
/*
* On i.MX7, DIRECT_SPEED_CHANGE behaves
* differently from i.MX6 family when no link
@@ -762,11 +764,13 @@ static void imx6_pcie_remove(struct device_d *dev)
static const struct imx6_pcie_drvdata drvdata[] = {
[IMX6Q] = {
.variant = IMX6Q,
- .flags = IMX6_PCIE_FLAG_IMX6_PHY,
+ .flags = IMX6_PCIE_FLAG_IMX6_PHY |
+ IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
},
[IMX6QP] = {
.variant = IMX6QP,
- .flags = IMX6_PCIE_FLAG_IMX6_PHY,
+ .flags = IMX6_PCIE_FLAG_IMX6_PHY |
+ IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
},
[IMX7D] = {
.variant = IMX7D,
--
2.20.1
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v2 15/15] PCI: imx6: Add support for i.MX8MQ
2019-02-05 21:53 [PATCH v2 00/15] PCIE support for i.MX8MQ Andrey Smirnov
` (13 preceding siblings ...)
2019-02-05 21:54 ` [PATCH v2 14/15] PCI: imx6: Convert DIRECT_SPEED_CHANGE quirk code to use a flag Andrey Smirnov
@ 2019-02-05 21:54 ` Andrey Smirnov
2019-02-07 7:53 ` [PATCH v2 00/15] PCIE " Sascha Hauer
15 siblings, 0 replies; 17+ messages in thread
From: Andrey Smirnov @ 2019-02-05 21:54 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Port of a Linux commit 2d8ed461dbc9bc734185db92d2b9d1bb7b586b30
Add code needed to support i.MX8MQ variant.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/Kconfig | 1 +
drivers/pci/Kconfig | 4 +-
drivers/pci/pci-imx6.c | 94 +++++++++++++++++++++++++++++++++++----
3 files changed, 89 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 587f0383d..a9cda3ed2 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -183,6 +183,7 @@ config ARCH_IMX8MQ
select SYS_SUPPORTS_64BIT_KERNEL
select COMMON_CLK_OF_PROVIDER
select ARCH_HAS_FEC_IMX
+ select HW_HAS_PCI
config ARCH_VF610
bool
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index d81afb3d2..44a89d005 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -41,8 +41,8 @@ config PCI_TEGRA
select PCI
config PCI_IMX6
- bool "Freescale i.MX6/7 PCIe controller"
- depends on ARCH_IMX6 || ARCH_IMX7
+ bool "Freescale i.MX6/7/8 PCIe controller"
+ depends on ARCH_IMX6 || ARCH_IMX7 || ARCH_IMX8MQ
select PCIE_DW
select OF_PCI
select PCI
diff --git a/drivers/pci/pci-imx6.c b/drivers/pci/pci-imx6.c
index d77c24990..138b4ca8b 100644
--- a/drivers/pci/pci-imx6.c
+++ b/drivers/pci/pci-imx6.c
@@ -26,20 +26,29 @@
#include <linux/phy/phy.h>
#include <linux/reset.h>
#include <linux/sizes.h>
+#include <linux/bitfield.h>
#include <mfd/imx6q-iomuxc-gpr.h>
#include <mfd/imx7-iomuxc-gpr.h>
#include <mach/imx6-regs.h>
#include <mach/imx7-regs.h>
+#include <mach/imx8mq-regs.h>
#include "pcie-designware.h"
+#define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
+#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
+#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
+#define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
+#define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000
+
#define to_imx6_pcie(x) ((x)->dev->priv)
enum imx6_pcie_variants {
IMX6Q,
IMX6QP,
IMX7D,
+ IMX8MQ,
};
#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
@@ -57,6 +66,7 @@ struct imx6_pcie {
struct clk *pcie_phy;
struct clk *pcie;
void __iomem *iomuxc_gpr;
+ u32 controller_id;
struct reset_control *pciephy_reset;
struct reset_control *apps_reset;
u32 tx_deemph_gen1;
@@ -261,6 +271,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
switch (imx6_pcie->drvdata->variant) {
case IMX7D:
+ case IMX8MQ:
reset_control_assert(imx6_pcie->pciephy_reset);
reset_control_assert(imx6_pcie->apps_reset);
break;
@@ -280,9 +291,16 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
}
}
+static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
+{
+ WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ);
+ return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
+}
+
static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
{
- u32 gpr1;
+ u32 gpr1, gpr1x;
+ unsigned int offset;
switch (imx6_pcie->drvdata->variant) {
case IMX6QP:
@@ -304,6 +322,20 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
break;
case IMX7D:
break;
+ case IMX8MQ:
+ offset = imx6_pcie_grp_offset(imx6_pcie);
+ /*
+ * Set the over ride low and enabled
+ * make sure that REF_CLK is turned on.
+ */
+ gpr1x = readl(imx6_pcie->iomuxc_gpr + offset);
+ gpr1x &= ~IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE;
+ writel(gpr1x, imx6_pcie->iomuxc_gpr + offset);
+
+ gpr1x = readl(imx6_pcie->iomuxc_gpr + offset);
+ gpr1x |= IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN;
+ writel(gpr1x, imx6_pcie->iomuxc_gpr + offset);
+ break;
}
return 0;
@@ -371,6 +403,9 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
* Release the PCIe PHY reset here
*/
switch (imx6_pcie->drvdata->variant) {
+ case IMX8MQ:
+ reset_control_deassert(imx6_pcie->pciephy_reset);
+ break;
case IMX7D:
reset_control_deassert(imx6_pcie->pciephy_reset);
imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
@@ -396,19 +431,52 @@ err_pcie_bus:
clk_disable(imx6_pcie->pcie_phy);
}
-static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
+static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
{
- u32 gpr12, gpr8;
+ unsigned int mask, val;
+ u32 gpr12;
- gpr12 = readl(imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
+ if (imx6_pcie->drvdata->variant == IMX8MQ &&
+ imx6_pcie->controller_id == 1) {
+ mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
+ val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
+ PCI_EXP_TYPE_ROOT_PORT);
+ } else {
+ mask = IMX6Q_GPR12_DEVICE_TYPE;
+ val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE,
+ PCI_EXP_TYPE_ROOT_PORT);
+ }
+
+ gpr12 = readl(imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
+ gpr12 &= ~mask;
+ gpr12 |= val;
+ writel(gpr12, imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
+}
+
+static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
+{
+ u32 gpr12, gpr8, gpr1x;
+ unsigned int offset;
switch (imx6_pcie->drvdata->variant) {
+ case IMX8MQ:
+ offset = imx6_pcie_grp_offset(imx6_pcie);
+ /*
+ * TODO: Currently this code assumes external
+ * oscillator is being used
+ */
+ gpr1x = readl(imx6_pcie->iomuxc_gpr + offset);
+ gpr1x |= IMX8MQ_GPR_PCIE_REF_USE_PAD;
+ writel(gpr1x, imx6_pcie->iomuxc_gpr + offset);
+ break;
case IMX7D:
+ gpr12 = readl(imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
gpr12 &= ~IMX7D_GPR12_PCIE_PHY_REFCLK_SEL;
writel(gpr12, imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
break;
case IMX6QP:
case IMX6Q: /* FALLTHROUGH */
+ gpr12 = readl(imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
gpr12 &= ~IMX6Q_GPR12_PCIE_CTL_2;
writel(gpr12, imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
@@ -440,9 +508,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
break;
}
- gpr12 &= ~IMX6Q_GPR12_DEVICE_TYPE;
- gpr12 |= PCI_EXP_TYPE_ROOT_PORT << 12;
- writel(gpr12, imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
+ imx6_pcie_configure_type(imx6_pcie);
}
static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
@@ -481,6 +547,7 @@ static void imx6_pcie_ltssm_enable(struct device_d *dev)
writel(gpr12, imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
break;
case IMX7D:
+ case IMX8MQ:
reset_control_deassert(imx6_pcie->apps_reset);
break;
}
@@ -668,10 +735,17 @@ static int imx6_pcie_probe(struct device_d *dev)
return PTR_ERR(imx6_pcie->pcie);
}
+
switch (imx6_pcie->drvdata->variant) {
+ case IMX8MQ:
+ imx6_pcie->iomuxc_gpr = IOMEM(MX8MQ_IOMUXC_GPR_BASE_ADDR);
+ if (iores->start == IMX8MQ_PCIE2_BASE_ADDR)
+ imx6_pcie->controller_id = 1;
+
+ goto imx7d_init;
case IMX7D:
imx6_pcie->iomuxc_gpr = IOMEM(MX7_IOMUXC_GPR_BASE_ADDR);
-
+ imx7d_init:
imx6_pcie->pciephy_reset = reset_control_get(dev, "pciephy");
if (IS_ERR(imx6_pcie->pciephy_reset)) {
dev_err(dev, "Failed to get PCIEPHY reset control\n");
@@ -775,12 +849,16 @@ static const struct imx6_pcie_drvdata drvdata[] = {
[IMX7D] = {
.variant = IMX7D,
},
+ [IMX8MQ] = {
+ .variant = IMX8MQ,
+ },
};
static struct of_device_id imx6_pcie_of_match[] = {
{ .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
{ .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
{ .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
+ { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } ,
{},
};
--
2.20.1
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^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v2 00/15] PCIE support for i.MX8MQ
2019-02-05 21:53 [PATCH v2 00/15] PCIE support for i.MX8MQ Andrey Smirnov
` (14 preceding siblings ...)
2019-02-05 21:54 ` [PATCH v2 15/15] PCI: imx6: Add support for i.MX8MQ Andrey Smirnov
@ 2019-02-07 7:53 ` Sascha Hauer
15 siblings, 0 replies; 17+ messages in thread
From: Sascha Hauer @ 2019-02-07 7:53 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: barebox
On Tue, Feb 05, 2019 at 01:53:56PM -0800, Andrey Smirnov wrote:
> This series contains port of the various Linux patches needed to
> enable support of PCIE IP block on i.MX8MQ SoCs.
>
> Feedback is welcome!
>
> Changes since [v1]:
>
> - Added proper SHA1s and removed RFC tag from last four patches
> since their Linux counterparts were accepted to PCI tree
>
> Thanks,
> Andrey Smirnov
Applied, thanks
Sascha
>
> [v1] http://lists.infradead.org/pipermail/barebox/2019-January/036899.html
>
> Andrey Smirnov (15):
> PCI: dwc: Fix pointer width cast problem
> ARM: aarch64: Add PCI fixups section to linker script
> soc: imx: gpcv2: use A_CORE instread of A7 for more i.MX platforms
> soc: imx: gpcv2: make pgc driver more generic for other i.MX platforms
> soc: imx: gpcv2: Switch to SPDX identifier
> soc: imx: gpcv2: prefix i.MX7 specific defines
> soc: imx: gpcv2: add support for i.MX8MQ SoC
> reset: Constify "ops" in struct reset_controller_dev
> reset: imx7: Add plubming to support multiple IP variants
> include: Import dt-bindings/reset/imx8mq-reset.h
> reset: imx7: Add support for i.MX8MQ IP block variant
> PCI: imx6: Introduce drvdata
> PCI: imx6: Mark PHY functions as i.MX6 specific
> PCI: imx6: Convert DIRECT_SPEED_CHANGE quirk code to use a flag
> PCI: imx6: Add support for i.MX8MQ
>
> arch/arm/lib64/barebox.lds.S | 12 +
> arch/arm/mach-imx/Kconfig | 1 +
> drivers/pci/Kconfig | 4 +-
> drivers/pci/pci-imx6.c | 149 ++++++++++--
> drivers/pci/pcie-designware-host.c | 6 +-
> drivers/reset/reset-imx7.c | 172 +++++++++++--
> drivers/reset/reset-socfpga.c | 2 +-
> drivers/soc/imx/Kconfig | 8 +-
> drivers/soc/imx/Makefile | 2 +-
> drivers/soc/imx/gpcv2.c | 297 ++++++++++++++++++-----
> include/dt-bindings/reset/imx8mq-reset.h | 64 +++++
> include/linux/reset-controller.h | 2 +-
> 12 files changed, 614 insertions(+), 105 deletions(-)
> create mode 100644 include/dt-bindings/reset/imx8mq-reset.h
>
> --
> 2.20.1
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
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^ permalink raw reply [flat|nested] 17+ messages in thread