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From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: barebox@lists.infradead.org
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Subject: [PATCH 4/7] ARM: imx8mq: Add nodes for PCIE1 and PCIE2 IP blocks
Date: Tue, 26 Feb 2019 19:16:54 -0800	[thread overview]
Message-ID: <20190227031657.19896-5-andrew.smirnov@gmail.com> (raw)
In-Reply-To: <20190227031657.19896-1-andrew.smirnov@gmail.com>

Add node for PCE1 and PCIE2 IP block that is missing in upstream DTS. This patch
should be reverted once that changes.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/dts/imx8mq.dtsi | 89 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 89 insertions(+)

diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index eece19a7a..153808b1c 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -4,6 +4,7 @@
  * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
  */
 
+#include <dt-bindings/reset/imx8mq-reset.h>
 #include <dt-bindings/thermal/thermal.h>
 
 / {
@@ -126,6 +127,35 @@
 				pgc {
 					#address-cells = <1>;
 					#size-cells = <0>;
+
+					/*
+					 * As per comment in ATF source code:
+					 *
+					 * PCIE1 and PCIE2 share the
+					 * same reset signal, if we power
+					 * down PCIE2, PCIE1 will be held
+					 * in reset too.
+					 *
+					 * So instead of creating two
+                                         * separate power domains for
+                                         * PCIE1 and PCIE2. We create
+                                         * a link between 1 and 10 and
+                                         * use what was supposed to be
+                                         * domain 1 as a shared PCIE
+                                         * power domain powering both
+                                         * PCIE1 and PCIE2 at the same
+                                         * time
+					 */
+					pgc_pcie_phy: gpc_power_domain@1 {
+						#power-domain-cells = <0>;
+						reg = <1>;
+						power-domains = <&pgc_pcie2_phy>;
+					};
+
+					pgc_pcie2_phy: gpc_power_domain@10 {
+						#power-domain-cells = <0>;
+						reg = <10>;
+					};
 				};
 			};
 		};
@@ -141,6 +171,65 @@
 				status = "disabled";
 			};
 		};
+
+		pcie0: pcie@33800000 {
+			compatible = "fsl,imx8mq-pcie";
+			reg = <0x33800000 0x400000>,
+			      <0x1ff00000 0x80000>;
+			reg-names = "dbi", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
+		        	  0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+			num-lanes = <1>;
+			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+		        		<0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+		        		<0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+		        		<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,max-link-speed = <2>;
+			power-domains = <&pgc_pcie_phy>;
+			resets = <&src IMX8MQ_RESET_PCIEPHY>,
+		        	 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+		        	 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+			reset-names = "pciephy", "apps", "turnoff";
+			fsl,controller-id = <0>;
+			status = "disabled";
+		};
+
+		pcie1: pcie@33c00000 {
+			compatible = "fsl,imx8mq-pcie";
+			reg = <0x33c00000 0x400000>,
+			      <0x27f00000 0x80000>;
+			reg-names = "dbi", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges =  <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
+				  0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
+			num-lanes = <1>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,max-link-speed = <2>;
+			power-domains = <&pgc_pcie_phy>;
+			resets = <&src IMX8MQ_RESET_PCIEPHY2>,
+		        	 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
+		        	 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
+			reset-names = "pciephy", "apps", "turnoff";
+			fsl,controller-id = <1>;
+			status = "disabled";
+		};
 	};
 };
 
-- 
2.20.1


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  parent reply	other threads:[~2019-02-27  3:17 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-27  3:16 [PATCH 0/7] i.MX8MQ PCIe/USB DT changes Andrey Smirnov
2019-02-27  3:16 ` [PATCH 1/7] PCI: imx6: Add code to request/control "pcie_aux" clock for i.MX8MQ Andrey Smirnov
2019-02-27  3:16 ` [PATCH 2/7] ARM: imx8mq: Add node for SRC IP block Andrey Smirnov
2019-02-27  3:16 ` [PATCH 3/7] ARM: imx8mq: Add node for GPC " Andrey Smirnov
2019-02-27  3:16 ` Andrey Smirnov [this message]
2019-02-27  3:16 ` [PATCH 5/7] ARM: imx8mq-zii-ultra: Enable PCIE1 and PCIE2 Andrey Smirnov
2019-02-27 11:18   ` Lucas Stach
2019-02-28  2:42     ` Andrey Smirnov
2019-02-27  3:16 ` [PATCH 6/7] ARM: dts: imx8mq: Add nodes for USB IP blocks Andrey Smirnov
2019-02-27  3:16 ` [PATCH 7/7] ARM: imx8mq-zii-ultra: Add USB related nodes Andrey Smirnov
2019-02-27 11:10   ` Lucas Stach
2019-02-28  2:43     ` Andrey Smirnov
2019-02-27  7:43 ` [PATCH 0/7] i.MX8MQ PCIe/USB DT changes Sascha Hauer

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